CN116564985B - Composite dielectric grid photosensitive detector for reducing dark current and working method thereof - Google Patents
Composite dielectric grid photosensitive detector for reducing dark current and working method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
- H01L27/14605—Structural or functional details relating to the position of the pixel elements, e.g. smaller pixel elements in the center of the imager compared to pixel elements at the periphery
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/63—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to dark current
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a composite dielectric gate photosensitive detector capable of effectively reducing dark current and a working method thereof. The detector unit comprises a composite dielectric gate MOS capacitor and a composite dielectric gate MOSFET part which are formed above the same P-type semiconductor substrate, an N-type doped region is formed in the P-type semiconductor substrate, and a part of the P-type semiconductor substrate is reserved only between the N-type doped region and the bottom of a source electrode and a drain electrode of the composite dielectric gate MOSFET part. According to the invention, the photoelectron collecting area is changed from the surface of the substrate to the inside of the substrate, and the gate oxide interface and the side wall of the isolation structure are in a hole accumulation shape, so that the photoelectron collecting area is far away from the gate oxide interface and the shallow groove isolation side wall with serious dark excitation, the dark current is inhibited, and the full well capacity is not lost.
Description
Technical Field
The invention relates to an imaging detection device, in particular to a structure and a working mechanism of the imaging detection device from infrared wave band to visible wave band, and particularly relates to a composite dielectric gate photosensitive detector capable of effectively reducing dark current and a working method thereof.
Background
The solid-state imaging sensor market is prospering and experiencing an exponential growth due to the demands of digital and video cameras, mobile imaging, monitoring and biometric fields. Traditionally, CCDs are the dominant imaging technology. However, with the rapid development of CMOS technology, CMOS image sensor (CMOS image sensor, CIS) technology is widely used in various fields, such as PC camera, mobile phone, high-end digital camera, etc., and with the iterative optimization of technology, it is comparable to CCD in some performance aspects, and it has become an alternative product of CCD. However, a common CMOS-APS is composed of a photodiode and a readout gating transistor, typically four to five transistors, and as the pixel size decreases, it is difficult for the CIS to maintain a larger full well charge and a larger signal-to-noise ratio is obtained, which makes it difficult to ensure image quality.
Patent CN102938409a and patent CN107658321a propose a dual transistor photo detector based on a composite dielectric gate MOSFET, which comprises a composite dielectric gate MOS capacitor and a composite dielectric gate MOSFET portion formed over the same P-type semiconductor substrate, the substrate (collection region) of the photo transistor and the substrate (readout region) of the readout transistor being separated by shallow trench isolation (Shallow Trench Isolation, STI), wherein the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET portion share a composite dielectric gate, comprising bottom dielectric layer, floating gate, top dielectric layer and control gate from bottom to top. The photodetector can achieve a higher signal-to-noise ratio and higher full well charge at the same pixel size than a CCD and CIS.
However, in order to obtain a smaller-sized back-illuminated photosensitive array, the photosensitive detectors proposed in the two patents at present lack an array structure capable of effectively reducing crosstalk and simultaneously facilitating the application of voltage to the substrate of each pixel for equipotential operation, so that patent CN115732523a proposes a back-illuminated photosensitive array based on a composite dielectric gate and an imaging device thereof, which integrally control the voltage of a pixel body region, save the area of pixels, make crosstalk between pixels as small as possible, and simultaneously do not affect the application of voltage to the substrate of each pixel for equipotential operation. The distribution resistance between the pixel body regions is greatly reduced, and the potential distribution between the pixel body regions in the array is more uniform.
However, since the detector structures proposed in CN102938409A, CN107658321a and CN115732523a have depletion layers on the surface of the P-type substrate during exposure, and since the gate oxide surface and the STI sidewall have many defects, when the depletion layers contact with the two, strong dark electron excitation is caused under the auxiliary effect of interface traps, so that the dark characteristic of the device is poor, and a serious fixed pattern noise is brought by a large dark signal. To reduce dark excitation, a photosensitive detector based on improved dark characteristics of a composite dielectric gate structure is proposed in patent CN111554699 a. Each detection unit of the detector comprises a composite dielectric gate MOS-C part, a composite dielectric gate MOSFET part and a reset tube part, the composite dielectric gate MOS capacitor part is utilized for photosensitive, an optical signal obtained by photosensitive of the MOS-C part is coupled to the composite dielectric gate MOSFET part through the charge coupling effect so as to read, and the reset tube is utilized for resetting the MOS capacitor part. An N-type injection region is arranged below the MOS capacitor, reset is carried out by using a reset tube before exposure, and negative bias is applied to a control gate of a photosensitive detection unit during exposure, so that the surface of a P-type substrate of the MOS capacitor part is in a hole accumulation state, a photoelectron collecting region is far away from a gate oxide interface, and the side wall of an STI (shallow trench isolation) is also in the P+ type injection region, thereby effectively inhibiting dark electron excitation caused by an interface trap at a heterojunction and reducing the dark noise of the photosensitive detector. However, the reset tube introduced in the patent reduces the area of the MOC-C part, reduces the full well capacity of the photosensitive detector, meanwhile, the P+ wrapping mode structure adopted by the STI is not suitable for small-size pixels, the wrapping effect on the side wall of the STI is difficult to ensure after a series of anneals in the process, and the full well capacity is also reduced to a certain extent by the doping.
Disclosure of Invention
The invention aims to provide a composite dielectric gate photosensitive detector which simultaneously reduces dark current and maintains high full well capacity. It is another object of the present invention to provide a method of operating the above photosensitive detector.
The detector adopts the following technical scheme:
the detector unit of the composite dielectric gate photosensitive detector for reducing dark current comprises a composite dielectric gate MOS capacitor and a composite dielectric gate MOSFET part which are formed above the same P-type semiconductor substrate, wherein an N-type doped region is formed in the P-type semiconductor substrate, and a part of the P-type semiconductor substrate is reserved only between the N-type doped region and the bottom of a source electrode and a drain electrode of the composite dielectric gate MOSFET part.
Further, the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET part share a composite dielectric gate, and the composite dielectric gate comprises a bottom dielectric layer, a floating gate, a top dielectric layer and a control gate from bottom to top.
Further, a second isolation structure is arranged between the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET part; the N-type doped region has a certain concentration gradient, and the maximum doping concentration position is positioned at a depth of 0.1-0.5 um below the bottom of the second isolation structure and gradually decreases from the maximum doping concentration position to the upper side and the lower side.
Further, the second isolation structure comprises a second isolation structure dielectric layer and a second isolation structure grid electrode, and the second isolation structure dielectric layer wraps the second isolation structure grid electrode.
Further, when a plurality of the detector units are arranged, a first isolation structure is arranged between the adjacent detector units, and penetrates through the P-type substrate.
Further, the first isolation structure comprises a first isolation structure dielectric layer and a first isolation structure grid electrode, and the first isolation structure dielectric layer wraps the first isolation structure grid electrode.
Further, a conductive layer is disposed below the P-type semiconductor substrate for transferring a substrate voltage.
Further, the conductive layer is doped P-type monocrystalline silicon or polycrystalline silicon, or intrinsic monocrystalline silicon or polycrystalline silicon.
Further, a high dielectric constant layer having a characteristic of forming hole accumulation on a lower surface of the conductive layer is provided under the conductive layer.
The invention also provides a working method of the composite dielectric gate photosensitive detector for reducing dark current, wherein a plurality of detector units are arranged, a first isolation structure is arranged between adjacent detector units, and the first isolation structure comprises a first isolation structure dielectric layer and a first isolation structure gate; a second isolation structure is arranged between the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET part, and comprises a second isolation structure dielectric layer and a second isolation structure grid; the working method comprises the following steps:
1) Standby stage: the voltage of the control grid is V Hold, and the size is 0V; the voltage of the substrate is V sub, and the size is-1 to-20V; the grid voltage of the first isolation structure is V CDTI, and the size of the first isolation structure is less than or equal to V sub; the grid voltage of the second isolation structure is V STI_1, and the size of the second isolation structure is less than or equal to V sub; the source voltage is V s, and the size is 0V; the drain voltage is V d, and the size is 0.1-1.0V;
2) And (3) a reset stage: the substrate voltage is kept unchanged at V sub, the first isolation structure grid voltage is unchanged at V CDTI, the control grid voltage is reduced to V RST, and the size is required to be smaller than or equal to the substrate voltage at V sub; the grid voltage of the second isolation structure is increased to V STI_2, the size of the second isolation structure needs to meet the threshold voltage of a reset transistor of the detector unit or more, the grid of the reset transistor is the grid of the second isolation structure, the grid oxide dielectric layer is the dielectric layer of the second isolation structure, the source electrode is an N-type doped region which is partially depleted by holes, the drain electrode is the source electrode/drain electrode of the composite dielectric grid MOSFET part, and after the reset transistor is started, electrons in the N-type doped region flow away from the source electrode/drain electrode of the photoelectron composite dielectric grid MOSFET part until the reset transistor is completely emptied, so that a completely depleted photoelectron collecting region is formed, and a reset process is realized;
3) Exposure stage: the grid voltage of the second isolation structure is reduced to V STI_1, and the voltages of all other electrodes keep the voltage in the reset stage unchanged;
4) Reading: the control grid starts to add ramp voltage until the composite dielectric grid MOSFET part is completely started, at the moment, the composite dielectric grid MOS capacitor also generates a depletion region and is connected with the depletion region of the photoelectron collecting region, electrons in the photoelectron collecting region are extracted to the surface of the substrate of the composite dielectric grid MOS capacitor, the potential of the floating gate is changed, the threshold value of the composite dielectric grid MOSFET part is finally changed, and a subsequent readout circuit quantifies the threshold value to obtain a gray value; in the read phase, all other electrode voltages except the gate voltage remain unchanged at the exposure phase voltage.
According to the invention, the photoelectron collecting area is changed from the surface of the substrate to the inside of the substrate, and the gate oxide interface and the side wall of the isolation structure are in a hole accumulation shape, so that the photoelectron collecting area is far away from the gate oxide interface and the STI side wall with serious dark excitation, the dark current is inhibited, and the full well capacity of the structure proposed in CN115732523A is not lost.
Drawings
FIG. 1 is a two-dimensional block diagram of a photosensitive detector of the present invention;
FIG. 2 is a cross-sectional view taken along the direction X 1-X1' in FIG. 1;
FIG. 3 is a graph showing the N-type doping concentration profile in the AA' direction of FIG. 2;
FIG. 4 is a cross-sectional view taken along the direction Y 1-Y1' in FIG. 1;
FIG. 5 is a cross-sectional view taken along the direction Y 2-Y2' in FIG. 1;
FIG. 6 is a timing diagram of the voltages at each port of the photosensitive detector during operation;
FIG. 7 is a schematic diagram showing the electron and hole distribution of a photosensitive detector in standby;
FIG. 8 is a schematic diagram showing the distribution of electrons and holes and the direction of flow of electrons when the photodetector is reset;
FIG. 9 is a schematic diagram of electron and hole distribution when a photosensitive detector is exposed;
FIG. 10 is a schematic diagram of electron and hole distribution for a photodetector reading.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
Fig. 1 schematically shows a representative photo detector of a composite dielectric gate structure, which includes 4 photo detection units, and fig. 2 is a cross section of the photo detector at X 1-X′1, where the cross section includes two photo detection unit structures, and the two photo detection unit structures are identical left and right, and the MOS capacitor 17 and the MOSFET portion 18 of the photo detection unit are formed on the same P-type substrate 14, and the two are separated by the second isolation structure 12 to implement separation of functional areas; the P-type substrate 14 is subjected to 1-3 times of N-type ion implantation, such as phosphorus doping, arsenic doping, etc., to finally form an N-type doped region 15 with a certain concentration gradient, and the doped region is emptied of electrons to become a depletion region through a resetting process and then is used as an photoelectron collecting region in an exposure stage of the photosensitive detection unit; the N-type doping concentration distribution of the N-type doping region 15 along the AA' direction is shown in FIG. 3, and the depth of the maximum value of the doping concentration is 0.1-0.5 um below the bottom of the second isolation structure; a P-type substrate 16 is reserved between the N-type doped region 15 and the MOSFET part source/drain 5; the second isolation structure 12 includes a second isolation structure dielectric layer 11 and a second isolation structure gate 10, and the second isolation structure dielectric layer 11 wraps the second isolation structure gate 10.
The MOS capacitor 17 and the MOSFET part 18 share a composite dielectric gate structure, and the composite dielectric gate structure comprises a bottom dielectric layer 4, a floating gate 3, a top dielectric layer 2 and a control gate 1 from bottom to top. When a plurality of photosensitive detection units are arranged, a first isolation structure 13 penetrating through the P-type substrate 14 is arranged between the adjacent detection units along the depth direction of the substrate, so that the P-type substrates of the adjacent photosensitive detection units are completely separated; the first isolation structure 13 comprises a first isolation structure dielectric layer 6 and a first isolation structure grid electrode 7, the first isolation structure dielectric layer 6 is next to the source electrode/drain electrode 5, and the first isolation structure grid electrode 7 is wrapped by the first isolation structure dielectric layer 6.
A lightly doped P-type monocrystalline silicon or polycrystalline silicon epitaxial layer is formed on the lower surface of the P-type substrate 14 as the first conductive layer 8. The photosensitive detection unit structure realizes the transmission of substrate voltage through the first conductive layer 8, and the first isolation structure grid electrode 7 and the first conductive layer 8 are electrically isolated through the first isolation structure dielectric layer 6. A high dielectric constant layer 9 is disposed below the first conductive layer 8, and the high dielectric constant layer 9 forms hole accumulation on the upper surface of the first conductive layer 8, which is also helpful for substrate voltage transmission.
Fig. 4 is a cross section of the photosensitive detector at Y 1-Y′1, which contains only the MOSFET portion structure of two photosensitive detection cells, which are identical from side to side. The MOSFET portion 17 is formed on the same P-type substrate 14, and the two are completely separated by the first isolation structure 13; the P-type substrate 14 is subjected to 1-3 times of N-type ion implantation, such as phosphorus doping, arsenic doping, etc., to finally form an N-type doped region 15 with a certain concentration gradient, and the doped region is emptied of electrons to become a depletion region through a resetting process and then is used as an photoelectron collecting region in an exposure stage of the photosensitive detection unit; the first isolation structure 13 comprises a first isolation structure dielectric layer 6 and a first isolation structure grid electrode 7, the first isolation structure dielectric layer 6 is next to the source electrode/drain electrode 5, and the first isolation structure grid electrode 7 is wrapped by the first isolation structure dielectric layer 6. The source electrode of the MOSFET part can be 21 and 19, the drain electrode is 20 and 5 or the source electrode is 20 and 5, and the drain electrode is 21 and 19; a P-type substrate 16 is maintained between the N-doped region 15 and the source/drain of the MOSFET portion.
The composite dielectric gate structure comprises a bottom dielectric layer 4, a floating gate 3, a top dielectric layer 2 and a control gate 1 which are shared from bottom to top. A lightly doped P-type monocrystalline silicon or polycrystalline silicon epitaxial layer is formed on the lower surface of the P-type substrate 14 as the first conductive layer 8. The photosensitive detection unit structure realizes the transmission of substrate voltage through the first conductive layer 8, and the first isolation structure grid electrode 7 and the first conductive layer 8 are electrically isolated through the first isolation structure dielectric layer 6. A high dielectric constant layer 9 is disposed below the first conductive layer 8, and the high dielectric constant layer 9 forms hole accumulation on the upper surface of the first conductive layer 8, which is also helpful for substrate voltage transmission.
Fig. 5 is a cross-section of the photosensitive detector at Y 2-Y′2, showing the intersection of the first isolation structure 13 and the second isolation structure 12. In fig. 2 and 4, the height of the first isolation structure 13 is H 1, the height of the first isolation structure 13 is H 2 in fig. 5, and H 1>H2 is satisfied mainly because the first isolation structure 13 presents a grid-like distribution in the photodetector array, the second isolation structure 12 presents a stripe-like structure in the photodetector array, there is an intersecting portion between the two, and the height of the intersecting portion is the depth of the second isolation structure. The first isolation structure 13 and the second isolation structure 12 are electrically isolated by the second isolation structure dielectric layer 11.
The composite dielectric gate structure comprises a bottom dielectric layer 4, a floating gate 3, a top dielectric layer 2 and a control gate 1 which are shared from bottom to top. The first conductive layer 8 and the first isolation structure grid electrode 7 are electrically isolated by the first isolation structure dielectric layer 6. A high dielectric constant layer 9 is provided below the first conductive layer 8. 15 in the figure is the substrate N-type doped region, integral with 15 in fig. 2 and 15 in fig. 4.
In fig. 2, fig. 4 and fig. 5, the bottom dielectric layer is silicon dioxide, silicon nitride or other high dielectric constant dielectric, the top dielectric layer is a silicon dioxide single-layer structure or a silicon dioxide/silicon nitride double-layer structure or a silicon dioxide/silicon nitride/silicon dioxide/aluminum oxide/silicon dioxide three-layer structure, the thickness of the dielectric layer is less than 10 nanometers, the floating gate and the control gate are made of N-type doped polysilicon, the first isolation structure dielectric layer and the second isolation structure dielectric layer are made of silicon dioxide, silicon nitride or other high dielectric constant dielectric, the thickness is 5-10 nm, the first isolation structure grid electrode and the second isolation structure grid electrode are made of N-type doped polysilicon, the first conductive layer is made of lightly doped P-type monocrystalline silicon epitaxial layer or polysilicon epitaxial layer, and the thickness is about 10-100 nm. The high dielectric constant material may include one or more combinations of aluminum oxide, tantalum oxide, hafnium silicon oxide, hafnium aluminum oxide, or hafnium tantalum oxide.
Another object of the present invention is to provide a working method of the above photosensitive detector, wherein each port voltage timing is shown in fig. 6, and specifically described as follows:
1) Standby stage: fig. 7 is a state illustration of the composite dielectric gate structure in the standby phase. The voltage of the control grid electrode 1 is V Hold, and the size is 0V; the voltage of the substrate is V sub, and the size can be-1 to-20V; the voltage of the grid electrode 7 of the first isolation structure is V CDTI, the size of the grid electrode is required to be smaller than or equal to V sub, and hole accumulation 23 is formed on the side wall of the first isolation structure, so that excitation of dark electrons at an interface can be effectively inhibited; the voltage of the grid electrode 10 of the second isolation structure is V STI_1, the size of the grid electrode is required to be smaller than or equal to V sub, and hole accumulation 22 is formed on the side wall of the second isolation structure at the moment, so that excitation of dark electrons at an interface can be effectively inhibited; the source voltage is V s, and the size is 0V; the drain voltage is V d, and the size can be 0.1-1.0V. Hole accumulation 25 is also present on the surface of the first conductive layer 8, and excitation of dark electrons at the interface can be suppressed.
2) And (3) a reset stage: fig. 8 is a state illustration of the composite dielectric gate structure during the reset phase. The substrate voltage maintains the standby state voltage V sub unchanged, and the size can be-1 to-20V; the voltage of the grid electrode 7 of the first isolation structure maintains the voltage V CDTI in the standby state unchanged, the size of the voltage is required to be smaller than or equal to V sub, and hole accumulation 23 is formed on the side wall of the first isolation structure, so that excitation of dark electrons at an interface can be effectively inhibited; the voltage of the control grid electrode 1 is reduced to V RST, the voltage of the control grid electrode is required to be smaller than or equal to the voltage of the substrate and is V sub, and at the moment, hole accumulation 27 is formed on the surface of the grid oxide, so that excitation of dark electrons at the interface of the grid oxide can be effectively inhibited; the voltage of the second isolation structure gate 10 is increased to V STI_2, the magnitude needs to satisfy the threshold voltage of the parasitic MOSFET26 (reset transistor) shown in fig. 8, the gate of the parasitic MOSFET26 is the second isolation structure gate 10, the source is the N-type doped region 15 that is partially depleted by holes, the drain is the source/drain of the photosensitive detection unit MOSFET portion, when the parasitic MOSFET is turned on, electrons in the N-type doped region flow away from the source/drain of the optoelectronic photosensitive detection unit MOSFET portion in the direction indicated by the arrow in fig. 8 until the parasitic MOSFET is completely emptied, forming the completely depleted optoelectronic collecting region 24, thereby implementing the reset process. Hole accumulation 25 is also present on the surface of the first conductive layer 8, and excitation of dark electrons at the interface can be suppressed.
3) Exposure stage: fig. 9 is an illustration of the state of the composite dielectric gate structure during the exposure phase. The voltage of the second isolation structure grid electrode 10 is reduced to V STI_1, the voltage of the first isolation structure grid electrode 7 maintains the reset state voltage V CDTI unchanged, the voltage is required to be smaller than or equal to V sub, and at the moment, the side wall of the first isolation structure forms hole accumulation 23, so that the excitation of dark electrons at an interface can be effectively inhibited; the voltage of the control grid electrode 1 maintains the reset state V RST unchanged, the voltage of the control grid electrode 1 is required to be smaller than or equal to the voltage of the substrate V sub, and at the moment, hole accumulation 27 is formed on the surface of the grid oxide, so that the excitation of dark electrons at the grid oxide interface can be effectively inhibited; hole accumulation 25 is also present on the surface of the first conductive layer 8, and excitation of dark electrons at the interface can be suppressed. The accumulation of holes results in a very small excitation rate of dark electrons at the interface and little increase in the total charge of the photoelectron signal in the photoelectron collection region 24 during exposure.
4) Reading: FIG. 10 is a state illustration of a composite dielectric gate structure during a read phase. The control gate 1 starts to add a ramp voltage until the channel of the MOSFET portion 18 of the photodetector is fully turned on, at which time the MOS capacitor portion 17 also generates a depletion region and is connected to the photoelectron collection region 24, extracting electrons in the photoelectron collection region 24 to the surface of the substrate of the MOS capacitor 17, thereby changing the floating gate potential, finally changing the threshold of the MOSFET portion 18, and the subsequent readout circuit quantifies the threshold to obtain a gray value. In this process, although the gate oxide interface generates the depletion region 28, since the reading process is very fast, on the order of microseconds, the dark current contributed by the gate oxide interface is very small. The voltage of the second isolation structure grid electrode 10 maintains the exposure state V STI_1 unchanged, the voltage of the first isolation structure grid electrode 7 maintains the exposure state voltage V CDTI unchanged, the size is required to be smaller than or equal to V sub, and at the moment, the side wall of the first isolation structure forms hole accumulation 23, so that excitation of dark electrons at an interface can be effectively inhibited; hole accumulation 25 is also present on the surface of the first conductive layer 8, and excitation of dark electrons at the interface can be suppressed. The accumulation of dark electrons during reading is therefore very small and negligible.
According to the invention, the photoelectron collecting area of the photosensitive detector is transferred from the surface of the substrate to the inside of the substrate in the exposure process, and meanwhile, the grid-oxygen interface, the side wall of the first isolation structure, the side wall of the second isolation structure and the lower surface of the substrate are in a hole accumulation state, so that dark electron excitation in the exposure process is effectively reduced, the dynamic range of the photosensitive detector is increased, and the imaging quality is effectively improved.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (10)
1. The detector unit of the composite dielectric gate photosensitive detector for reducing dark current comprises a composite dielectric gate MOS capacitor and a composite dielectric gate MOSFET part which are formed above the same P-type semiconductor substrate, and is characterized in that an N-type doping region is formed in the P-type semiconductor substrate, and only a part of the P-type semiconductor substrate is reserved between the N-type doping region and the source drain electrode of the composite dielectric gate MOSFET part and the bottom of the composite dielectric gate.
2. The dark current reducing composite dielectric gate photosensitive detector of claim 1, wherein the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET portion share a composite dielectric gate comprising, from bottom to top, a bottom dielectric layer, a floating gate, a top dielectric layer, and a control gate.
3. The dark current reducing composite dielectric gate photosensitive detector of claim 1, wherein a second isolation structure is provided between the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET portion; the N-type doped region has a certain concentration gradient, and the maximum doping concentration position is positioned at a depth of 0.1-0.5 um below the bottom of the second isolation structure and gradually decreases from the maximum doping concentration position to the upper side and the lower side.
4. The dark current reducing composite dielectric gate photosensitive detector of claim 3, wherein the second isolation structure comprises a second isolation structure dielectric layer and a second isolation structure gate, the second isolation structure dielectric layer surrounding the second isolation structure gate.
5. The dark current reducing composite dielectric gate photosensitive detector of claim 1, wherein when a plurality of said detector cells are arranged, a first isolation structure is disposed between adjacent detector cells, said first isolation structure extending through the P-type semiconductor substrate.
6. The dark current reducing composite dielectric gate photosensitive detector of claim 5, wherein the first isolation structure comprises a first isolation structure dielectric layer and a first isolation structure gate, the first isolation structure dielectric layer surrounding the first isolation structure gate.
7. The dark current reducing composite dielectric gate photodetector of claim 1, wherein a conductive layer is disposed below said P-type semiconductor substrate for transmitting a substrate voltage.
8. The dark current reducing composite dielectric gate photodetector of claim 7, wherein said conductive layer is doped P-type monocrystalline or polycrystalline silicon or intrinsic monocrystalline or polycrystalline silicon.
9. The dark current reducing composite dielectric gate photodetector of claim 7 or 8, wherein a high dielectric constant layer is disposed under said conductive layer, said high dielectric constant layer having the property of forming hole accumulation on a lower surface of said conductive layer.
10. The method of claim 1, wherein a plurality of said detector units are arranged with a first isolation structure between adjacent detector units, the first isolation structure comprising a first isolation structure dielectric layer and a first isolation structure gate; a second isolation structure is arranged between the composite dielectric gate MOS capacitor and the composite dielectric gate MOSFET part, and comprises a second isolation structure dielectric layer and a second isolation structure grid; the working method comprises the following steps:
1) Standby stage: the voltage of the control grid is V Hold, and the size is 0V; the voltage of the substrate is V sub, and the size is-1 to-20V; the grid voltage of the first isolation structure is V CDTI, and the size of the first isolation structure is less than or equal to V sub; the grid voltage of the second isolation structure is V STI_1, and the size of the second isolation structure is less than or equal to V sub; the source voltage is V s, and the size is 0V; the drain voltage is V d, and the size is 0.1-1.0V;
2) And (3) a reset stage: the substrate voltage is kept unchanged at V sub, the first isolation structure grid voltage is unchanged at V CDTI, the control grid voltage is reduced to V RST, and the size is required to be smaller than or equal to the substrate voltage at V sub; the grid voltage of the second isolation structure is increased to V STI_2, the size of the second isolation structure needs to meet the threshold voltage of a reset transistor of the detector unit or more, the grid of the reset transistor is the grid of the second isolation structure, the grid oxide dielectric layer is the dielectric layer of the second isolation structure, the source electrode is an N-type doped region which is partially depleted by holes, the drain electrode is the source electrode/drain electrode of the composite dielectric grid MOSFET part, and after the reset transistor is started, electrons in the N-type doped region flow away from the source electrode/drain electrode of the photoelectron composite dielectric grid MOSFET part until the reset transistor is completely emptied, so that a completely depleted photoelectron collecting region is formed, and a reset process is realized;
3) Exposure stage: the grid voltage of the second isolation structure is reduced to V STI_1, and the voltages of all other electrodes keep the voltage in the reset stage unchanged;
4) Reading: the control grid starts to add ramp voltage until the composite dielectric grid MOSFET part is completely started, at the moment, the composite dielectric grid MOS capacitor also generates a depletion region and is connected with the depletion region of the photoelectron collecting region, electrons in the photoelectron collecting region are extracted to the surface of the substrate of the composite dielectric grid MOS capacitor, the potential of the floating gate is changed, the threshold value of the composite dielectric grid MOSFET part is finally changed, and a subsequent readout circuit quantifies the threshold value to obtain a gray value; in the read phase, all other electrode voltages except the gate voltage remain unchanged at the exposure phase voltage.
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