CN116190436B - Two-dimensional homojunction logic inverter and preparation method thereof - Google Patents
Two-dimensional homojunction logic inverter and preparation method thereof Download PDFInfo
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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Abstract
The invention discloses a two-dimensional homojunction logic inverter and a preparation method thereof, wherein the two-dimensional homojunction logic inverter comprises the following steps: an insulating substrate, a first electrode group, a dielectric layer, a two-dimensional semiconductor layer and a second electrode group; forming the suspended channel region based on the two-dimensional semiconductor layer, the dielectric layer and the first electrode group, wherein the suspended channel region is used for inhibiting static current; the first electrode group includes: an output electrode and an input electrode, the dielectric layer comprising: a first dielectric layer and a second dielectric layer, the second electrode set comprising: a drive electrode and a ground electrode. The preparation method of the homojunction logic inverter is simple, convenient and feasible, has universality, can effectively inhibit the rising of the quiescent current of the logic inverter during operation, thereby reducing the power consumption and improving the service life and the service stability of the logic inverter.
Description
Technical Field
The invention relates to the field of application of two-dimensional semiconductor materials, in particular to a homojunction logic inverter and a preparation method thereof.
Background
The logic inverter is a core element of a digital integrated circuit design, and the key characteristic of the logic inverter is that the phase of an input signal is inverted by 180 degrees to output, namely binary '0' to '1' mutual conversion is realized, wherein the complementary inverter is widely applied to the digital integrated circuit by virtue of extremely low static power consumption and large noise margin, but the complementary inverter needs to prepare two semiconductor materials with different polarities simultaneously to realize a complementary structure consisting of a p-type channel transistor and an n-type channel transistor, and the complexity of circuit manufacturing is increased. In conventional silicon-based semiconductor designs, complementary inverters typically utilize heavily doped techniques to control semiconductor carrier concentration and type, such that the semiconductor exhibits complementary structure formed by both polarities, however, as transistor dimensions continue to shrink, increased leakage current and performance degradation due to short channel effects limit further development of digital integrated circuits. Compared with the three-dimensional bulk structure of a silicon-based material, a two-dimensional material represented by a transition metal chalcogenide has been used for manufacturing electronic chips with smaller specification and higher energy efficiency because of the unique physical characteristics of the two-dimensional layered structure with nano-scale, and has been shown by theoretical research in recent years to be a bright prospect of the next-generation nano-electronic device. However, when the channel dimensions are very small, the number of doping atoms will be greatly reduced on the nanometer scale, and achieving stable and controlled doping is a serious challenge. Therefore, the traditional silicon-based doping technology can not effectively realize the polarity control of the nanoscale ultrathin two-dimensional material, and can not fully play the application potential of the two-dimensional material in the low-power consumption integrated circuit layer.
Currently, based on two-dimensional materials, several emerging logic inverter construction schemes have been proposed in succession, which can be classified into unipolar and bipolar according to the type of material. The inverter based on the unipolar channel is simple in structure, but is not a complementary structure, so that static current of the inverter in operation cannot be effectively restrained, and static power consumption is increased. Whereas bipolar channel based inverters require two opposite polarity semiconductor materials, such structures require consideration of the matching between the two materials, existing main construction schemes can be divided into two categories: 1. the polarity of the material is changed through a mild doping mode, and the principle is that the interaction between the semiconductor material and the dopant is utilized to change the majority carrier type participating in conduction in the semiconductor material, but the ultra-thin two-dimensional semiconductor limits the doping effectiveness, and a stable and accurate doping method is still lacking. 2. The defect regulation and control principle is to control the unavoidable defects of the material, and the polarity regulation and control of the semiconductor is realized by repairing or manufacturing the characteristics of the defect regulation and control semiconductor and changing the concentration and the type of carriers. However, the method is difficult to realize accurate regulation and control of large-area defects, other uncontrollable defects are likely to be introduced due to poor controllability, unavoidable effects are likely to be generated with surrounding active substances, the polarity control force is insufficient, the polarity of a semiconductor cannot be thoroughly changed, and the quiescent current of the inverter during operation cannot be effectively restrained.
Disclosure of Invention
In order to solve the above problems, from the structural aspect, there is an urgent need for a low power inverter construction scheme suitable for two-dimensional semiconductor materials. The invention provides a homojunction logic inverter and a preparation method thereof. The homojunction logic inverter has the excellent performances of low power consumption, good service stability, good universality and the like, and meanwhile, the processing technology is simple. The preparation method provided by the invention aims to solve the problem of unstable polarity of materials caused by chemical doping, physical doping, defect regulation and other means, and provides a novel way for constructing a low-power inverter, which is simple, convenient and feasible, and has no damage and reversibility.
In order to achieve the above object, the present invention provides a two-dimensional homojunction logic inverter, comprising: an insulating substrate, a first electrode group, a dielectric layer, a two-dimensional semiconductor layer and a second electrode group which are sequentially upwards from the insulating substrate;
forming a suspended area based on the two-dimensional semiconductor layer, the dielectric layer and the first electrode group;
Optionally, the first electrode group includes: the output electrode and the input electrode are not connected; the output electrode is L-shaped, one side of the output electrode is connected with the two-dimensional semiconductor layer, the upper part of the other side of the output electrode is connected with the dielectric layer, and the output electrode, the dielectric layer and the two-dimensional semiconductor layer form the suspended area.
Optionally, the dielectric layer includes: a first dielectric layer and a second dielectric layer, wherein the length of the first dielectric layer is shorter than the length of the output electrode, and the length of the second dielectric layer is slightly longer than the length of the input electrode.
Optionally, the second electrode group includes: a driving electrode and a ground electrode; wherein the left side of the driving electrode is aligned with the left side of the two-dimensional semiconductor layer, the length of the driving electrode is shorter than that of the first dielectric layer, the right side of the grounding electrode is aligned with the right side of the two-dimensional semiconductor layer, and the length of the grounding electrode is shorter than that of the input electrode.
Optionally, the insulating substrate is a silicon wafer with an oxide layer, and the flexible insulating PET or sapphire substrate is adopted.
Optionally, the first electrode group and the second electrode group are metal electrodes or two-dimensional semi-metals, and the thickness of the first electrode group and the second electrode group is 30-50nm;
The dielectric layer is made of silicon oxide, aluminum oxide or hafnium oxide, and the thickness of the dielectric layer is 20-50nm.
Optionally, the two-dimensional semiconductor layer is a two-dimensional transition metal chalcogenide nanosheet, wherein the two-dimensional transition metal chalcogenide nanosheet comprises: and the thickness of the two-dimensional semiconductor layer is 0.7-10nm.
In order to achieve the above object, the present invention provides a method for preparing a two-dimensional homojunction logic inverter, comprising the steps of:
s1, preparing a two-dimensional semiconductor layer;
s2, depositing a first electrode group on the insulating substrate, wherein the first electrode group comprises an output electrode and an input electrode, and the output electrode is not connected with the input electrode;
S3, depositing a dielectric layer above the first electrode group, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, the length of the first dielectric layer is shorter than that of the output electrode, and the length of the second dielectric layer is slightly longer than that of the input electrode;
S4, assembling the two-dimensional semiconductor layer above the dielectric layer, and contacting one side of the output electrode and leaving a suspended area;
And S5, depositing a second electrode group above the two-dimensional semiconductor layer to finish the preparation of the two-dimensional homojunction logic inverter, wherein the second electrode group comprises a driving electrode and a grounding electrode.
Optionally, the wet transfer process includes:
Spin-coating PMMA glue on a substrate with the two-dimensional semiconductor layer material, and controlling the drying temperature to 120 ℃ and the drying time to 1-2min to obtain a PMMA film;
Immersing the substrate into deionized water and hydrofluoric acid solution in a preset proportion, etching off a silicon dioxide oxide layer on the surface of the silicon wafer, and obtaining a PMMA film with the two-dimensional semiconductor layer material;
Immersing the PMMA film into deionized water solution to clean hydrofluoric acid solution remained on the PMMA film, fishing out the cleaned PMMA film, precisely stacking the cleaned PMMA film on the upper surface of the dielectric layer by utilizing a precise transfer platform and contacting with the output electrode, and finally immersing the PMMA film with the two-dimensional semiconductor layer material into acetone solution to remove PMMA glue, thereby completing transfer.
The beneficial technical effects of the invention are as follows:
An adjustable homojunction potential barrier is formed between the suspended channel region and the non-suspended channel region under the action of an electrostatic field, so that the rising of static current in the operation of the logic inverter is effectively inhibited, and the power consumption is reduced;
the invention skillfully avoids the change of the polarity of channel materials by complex processes such as doping, defect regulation and the like through structural design, avoids the damage to the crystal structure of the materials, improves the service life and service stability of the logic inverter, and is a lossless and reversible preparation method;
The logic inverter of the invention has excellent voltage conversion characteristic and ultra-low quiescent current (less than 10 pA), and can be used as a low-power-consumption circuit element in the field of integrated circuits;
The preparation method provided by the invention is simple, convenient and feasible, and has universality.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application. In the drawings:
FIG. 1 is a schematic diagram of a homojunction logic inverter according to the present invention;
FIG. 2 is a graph showing the voltage transfer characteristics of a single-layer molybdenum disulfide homojunction logic inverter according to example 1;
FIG. 3 is a graph showing the current output characteristics of a single-layer molybdenum disulfide homojunction logic inverter according to example 1;
FIG. 4 is a graph showing the current output characteristics of a low-layer tungsten disulfide homojunction logic inverter according to example 2;
FIG. 5 is a schematic diagram of a conventional inverter of a comparative example;
FIG. 6 is a graph showing the current output characteristics of a conventional inverter with a small number of tungsten disulfide layers according to the comparative example;
1, an insulating substrate; 2. an output electrode; 3. a first dielectric layer; 4. a driving electrode; 5. a suspended area; 6. a two-dimensional semiconductor layer; 7. a ground electrode; 8. an input electrode; 9. a second dielectric layer; 10. and interconnecting the electrodes.
Detailed Description
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
As shown in fig. 1, the present invention provides a two-dimensional homojunction logic inverter comprising: an insulating substrate 1, a first electrode group, a dielectric layer, a two-dimensional semiconductor layer 6, and a second electrode group;
Forming a suspension area 5 based on the two-dimensional semiconductor layer 6, the dielectric layer and the first electrode group;
Further, the first electrode group includes: the output electrode 2 and the input electrode 8 are not connected with each other; the output electrode 2 is L-shaped, one side of the output electrode 2 is connected with the two-dimensional semiconductor layer 6, the upper side of the other side of the output electrode 2 is connected with the dielectric layer, and the output electrode 2, the dielectric layer and the two-dimensional semiconductor layer 6 form the suspension area.
Further, the dielectric layer includes: a first dielectric layer 3 and a second dielectric layer 9, the length of the first dielectric layer 3 being shorter than the output electrode 2, the length of the second dielectric layer 9 being slightly longer than the length of the input electrode 8.
Further, a two-dimensional semiconductor layer 6 is located above the dielectric layer 3 and in contact with the output electrode 2 leaving a portion of the suspended region 5.
Further, the second electrode group includes: a driving electrode 4 and a ground electrode 7; wherein the driving electrode 4 and the ground electrode 7; wherein the left side of the driving electrode 4 is aligned with the left side of the two-dimensional semiconductor layer 6, the length of the driving electrode 4 is shorter than the first dielectric layer 3, the right side of the ground electrode 7 is aligned with the right side of the two-dimensional semiconductor layer 6, and the length of the ground electrode 7 is shorter than the input electrode 8.
Further, the insulating substrate 1 is a silicon wafer with an oxide layer, a flexible insulating PET or sapphire substrate.
Further, the first electrode group and the second electrode group are metal electrodes or two-dimensional semi-metals, and the thickness of the first electrode group and the second electrode group is 30-50nm;
The dielectric layer is made of silicon oxide, aluminum oxide or hafnium oxide, and the thickness of the dielectric layer is 20-50nm.
Further, the material of the two-dimensional semiconductor layer 6 is a two-dimensional transition metal chalcogenide nanosheet, wherein the two-dimensional transition metal chalcogenide nanosheet includes: the two-dimensional material with semiconductor characteristics such as molybdenum disulfide, molybdenum diselenide, tungsten disulfide and the like, and the thickness of the two-dimensional semiconductor layer is 0.7-10nm.
The structure of the homojunction logic inverter of the invention comprises: the insulating substrate 1, the input electrode 8, the output electrode 2, the dielectric layer, the two-dimensional semiconductor layer 6, the driving electrode 4, and the ground electrode 7 are stacked in this order, wherein the two-dimensional semiconductor layer 6 needs to be in contact with the output electrode 2, the driving electrode 4, and the ground electrode 7.
The suspended region 5 of the present invention is critical to suppress quiescent current during operation of the homojunction inverter.
When the homojunction inverter operates, the driving electrode 4 always keeps high potential, the grounding electrode 7 keeps low potential as soon as the grounding electrode is directly grounded, and the potential of the output electrode 2 changes along with the change of the potential of the input electrode 8, namely, the input low potential (defined as binary logic '0') state and the output high potential (defined as binary logic '1') state; the high potential (defined as binary logic '1' state) is input and the low potential (defined as binary logic '0' state) is output.
The invention hangs the channel part and locates at the above the extended output electrode 2 and does not hang the channel part, will form an adjustable homojunction potential barrier under the function of electrostatic field that the output electrode 2 exerts, and the magnitude of the potential barrier changes along with the electric potential change of the output electrode 2, namely when the output electrode 2 is high electric potential, with the drive electrode 4 the same electric potential, there is no electrostatic field to act on the channel, there is almost no potential barrier between the channel part and the non-hanging channel part that hangs at this moment; when the output electrode 2 is at low potential, a potential difference is generated between the output electrode and the driving electrode 4, so that an electrostatic field can be generated to act on the channel, and a homojunction potential barrier can be formed between the suspended channel part and the non-suspended channel part at the moment, and the potential barrier can inhibit static current when the inverter operates, so that power consumption is reduced.
The invention also provides a preparation method of the two-dimensional homojunction logic inverter, which comprises the following steps:
S1, preparing a two-dimensional semiconductor layer 6;
S2, depositing a first electrode group on the insulating substrate 1, wherein the first electrode group comprises an output electrode 2 and an input electrode 8, and the output electrode 2 is not connected with the input electrode 8;
S3, depositing a dielectric layer above the first electrode group, wherein the dielectric layer comprises a first dielectric layer 3 and a second dielectric layer 9, the length of the first dielectric layer 3 is shorter than that of the output electrode 2, and the length of the second dielectric layer 9 is slightly longer than that of the input electrode 8;
s4, assembling the two-dimensional semiconductor layer 6 above the dielectric layer, contacting one side of the output electrode 2 and leaving a suspended area 5;
And S5, depositing a second electrode group above the two-dimensional semiconductor layer 6 to finish the preparation of the two-dimensional homojunction logic inverter, wherein the second electrode group comprises a driving electrode 4 and a grounding electrode 7.
Further, the wet transfer process includes:
Spin-coating PMMA adhesive on a substrate with a two-dimensional semiconductor layer material, and controlling the drying temperature to 120 ℃ and the drying time to 1-2min to obtain a PMMA film;
immersing a substrate into deionized water and hydrofluoric acid solution in a preset proportion, etching a silicon dioxide oxide layer on the surface of a silicon wafer, and obtaining a PMMA film with a two-dimensional semiconductor layer material;
immersing the PMMA film into deionized water solution to clean hydrofluoric acid solution remained in the PMMA film, fishing out the cleaned PMMA film, precisely stacking the cleaned PMMA film on the upper surface of the dielectric layer by utilizing a precise transfer platform and contacting with the output electrode 2, and finally immersing the PMMA film with the two-dimensional semiconductor layer material into acetone solution to remove PMMA glue, thereby completing transfer.
Example 1
Preparation of a single-layer molybdenum disulfide homojunction logic inverter:
(1) Preparing a two-dimensional semiconductor layer 6 (single-layer molybdenum disulfide nanosheets) by using a chemical vapor deposition method: molybdenum trioxide powder (10 mg) and sulfur powder (1 g, excessive, the sulfur powder is placed at the upstream and can be used repeatedly) are used as precursors, and single-layer molybdenum disulfide with the thickness of 0.7nm is generated by reaction under the growth temperature of 850 ℃ and the oxygen auxiliary condition. Sulfur powder was placed upstream of the vent and turned into sulfur vapor at 175 c and reacted with carrier gas (Ar) to a midstream (where molybdenum trioxide powder was placed) at 850 c to produce a monolayer of molybdenum disulfide.
(2) Pre-deposition of output electrode 2 and input electrode 8: spin-coating a layer of PMMA colloid on an insulating substrate 1, drying at 180 ℃ for 1min, carrying out patterning treatment by using an electron beam exposure technology, depositing a metal electrode by a thermal evaporation process, wherein the electrode material is pure gold, and completing the pre-deposition of an output electrode 2 and an input electrode 8, wherein the thickness is 30nm.
(3) Deposition of dielectric layer 3: and spin-coating PMMA colloid on a substrate with an output electrode 2 and an input electrode 8, drying at 180 ℃ for 1min, carrying out patterning treatment by utilizing an electron beam alignment technology, growing a dielectric layer 3 by an atomic layer deposition process, wherein the material of the dielectric layer is hafnium oxide, and finishing the processing of partially covering the output electrode 2 and completely covering the input electrode 8, wherein the thickness of the dielectric layer 3 is 30nm.
(4) Assembly of two-dimensional semiconductor layer 6: spin-coating a layer of PMMA adhesive serving as a carrier layer on a silicon wafer on which a single-layer molybdenum disulfide nano sheet grows, drying at 120 ℃ for 1min to form a film, immersing in a solution with the ratio of deionized water to hydrofluoric acid being 5:1, and etching off a silicon dioxide oxide layer on the surface of the silicon wafer to obtain a PMMA film with the molybdenum disulfide nano sheet floating on the surface of the solution; cleaning hydrofluoric acid solution remained on the surface of the film in deionized water solution, and then fishing the film to a customized carrier plate with PDMS; finally, the molybdenum disulfide nano-sheets on the PMMA film are precisely stacked on the upper surface of the dielectric layer 3 by utilizing a precise transfer platform, are contacted with the output electrode 2, leave a suspension area 5, and are then put into an acetone solution to remove PMMA residual glue, so that the assembly of the two-dimensional semiconductor layer 6 is completed and the two-dimensional semiconductor layer is used as a conducting channel material.
(5) Deposition driving electrode 4 and ground electrode 7: and depositing a metal electrode on the single-layer molybdenum disulfide by using an electron beam exposure technology and a thermal evaporation process to serve as a contact electrode, wherein the electrode material is pure gold, the thickness is 30nm, and finally the single-layer molybdenum disulfide homojunction logic inverter is completed.
The voltage transfer characteristic curve of the single-layer molybdenum disulfide homojunction logic inverter prepared in example 1 is shown in fig. 2. As can be seen from the graph of FIG. 2, when the input voltage changes from low potential to high potential, the output voltage realizes the conversion from high potential to low potential, and the output voltage shows excellent logical NOT gate function, which proves that the method successfully constructs a logical inverter. Wherein the inverter is operated with the drive electrode 4 always applying a high potential and the ground electrode 7 always being grounded at a low potential.
The current output characteristic curve of the single-layer molybdenum disulfide homojunction logic inverter prepared in example 1 is shown in fig. 3. As can be seen from the graph in fig. 3, the maximum quiescent operating current of the inverter is less than 10pA (1 na=1000 pA), which is far lower than the quiescent current of the existing inverter (greater than 1 nA), and the inverter exhibits a great low power consumption advantage.
Example 2
Preparation of a few-layer tungsten disulfide homojunction logic inverter:
(1) Preparation of two-dimensional semiconductor layer 6 (few-layer tungsten disulfide nanoplatelets) using mechanical lift-off: and (3) sticking a 3M blue film adhesive tape on the tungsten disulfide bulk material, slowly tearing off, then, pressing the adhesive tape with the tungsten disulfide thin sheet on a silicon wafer, slowly uncovering, enabling a few tungsten disulfide nano sheet to be left on the silicon wafer, repeating the previous operation for multiple times, and obtaining tungsten disulfide nano sheets with different thicknesses, wherein the tungsten disulfide nano sheet with the thickness of 2nm is selected as the two-dimensional semiconductor layer 6.
(2) Pre-deposition of output electrode 2 and input electrode 8: spin-coating a layer of PMMA colloid on an insulating substrate 1, drying at 180 ℃ for 1min, performing patterning treatment by using an electron beam exposure technology, depositing a metal electrode by a thermal evaporation process, wherein the electrode material is pure gold, and completing the pre-deposition of an output electrode and an input electrode, wherein the thickness is 30nm.
(3) Deposition of dielectric layer 3: and spin-coating PMMA colloid on a substrate with an output electrode 2 and an input electrode 8, drying at 180 ℃ for 1min, carrying out patterning treatment by utilizing an electron beam alignment technology, growing a dielectric layer 3 by an atomic layer deposition process, wherein the material of the dielectric layer is hafnium oxide, and finishing the processing of partially covering the output electrode 2 and completely covering the input electrode 8, wherein the thickness of the dielectric layer 3 is 30nm.
(4) Assembly of two-dimensional semiconductor layer 6: and spin-coating a PPC colloid on a silicon wafer with a few layers of tungsten disulfide nano sheets, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly tearing off the PPC film with boron nitride from the silicon wafer by using a 3M adhesive tape, precisely stacking the tungsten disulfide nano sheets on the PPC film on the upper surface of the dielectric layer 3 by using a precise transfer platform, contacting with the output electrode 2 and leaving a suspended area 5, and then putting into an acetone solution to remove PPC residual adhesive to complete the assembly of the two-dimensional semiconductor layer 6 as a conducting channel material.
(5) Deposition driving electrode 4 and ground electrode 7: and depositing a metal electrode on the few layers of tungsten disulfide by using an electron beam exposure technology and a thermal evaporation process to serve as a contact electrode, wherein the electrode material is pure gold, the thickness is 30nm, and finally the few layers of tungsten disulfide homojunction logic inverter is completed.
The current output characteristics of the low-layer tungsten disulfide homojunction logic inverter prepared in example 2 are shown in fig. 4. As can be seen from the graph of FIG. 4, the maximum quiescent current of the inverter is less than 10pA, and is also far lower than that of the conventional inverter (more than 1 nA), and the method is proved to be applicable to the few-layer tungsten disulfide nano-sheets.
Comparative example 1
In order to prove that the realization of ultra-low quiescent current of the homojunction logic inverter benefits from the unique floating region 5, the invention designs a comparative experiment of the traditional logic inverter without the floating channel region.
The schematic structure of the device in the comparison experiment is shown in fig. 5, wherein 1 is an insulating substrate, 2 is an output electrode, 3 is a first dielectric layer, 4 is a driving electrode, 6 is a two-dimensional semiconductor layer, 7 is a ground electrode, 8 is an input electrode, 9 is a second dielectric layer, and 10 is an interconnection electrode.
Preparation of comparative logical inverter:
(1) The comparative example uses the very same few-layer tungsten disulfide nanoplatelets as example 2 as the two-dimensional semiconductor layer 6, with a thickness of 2nm;
(2) The same process is used for the pre-deposition of the output electrode 2 and the input electrode 8: spin-coating a layer of PMMA colloid on an insulating substrate 1, drying at 180 ℃ for 1min, carrying out patterning treatment by utilizing an electron beam exposure technology, depositing a metal electrode by a thermal evaporation process, wherein the electrode material is pure gold, and completing the pre-deposition of an output electrode 2 and an input electrode 8, wherein the thickness is 30nm;
(3) The deposition of the first dielectric layer 3 and the second dielectric layer 9 is completed using the same atomic layer deposition process: the dielectric layer material is hafnium oxide with a thickness of 30nm. Note in particular that the first dielectric layer 3 and the second dielectric layer 9 completely cover the output electrode 2 and the input electrode 8 at this time;
(4) The assembly of the two-dimensional semiconductor layer 6 is completed using the same transfer process: the few-layer tungsten disulfide nano-sheets are precisely stacked on the upper surfaces of the first dielectric layer 3 and the second dielectric layer 9 and serve as conductive channel materials. Note in particular that at this time the tungsten disulfide nanoplatelets are not in contact with both the output electrode 2 and the input electrode 8 and no suspended area is formed;
(5) The deposition of the driving electrode 4, the ground electrode 7 and the interconnect electrode 10 is completed using the same process: the electrode material was pure gold and was in contact with the two-dimensional semiconductor layer 6, with a thickness of 30nm. The interconnection electrode 10 needs to short-circuit the output electrode 2 to be used as an output signal end together, and finally the preparation of the proportional logic inverter is completed.
The current output characteristic curve of the conventional logic inverter prepared in the comparative example is shown in fig. 6. As can be seen from the graph of FIG. 6, the maximum quiescent current of the inverter is greater than 5nA, which is far higher than the quiescent current (less than 10 pA) of the homojunction logic inverter according to the embodiment of the invention, thus proving that the homojunction logic inverter can effectively inhibit the quiescent current during operation.
The present application is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present application are intended to be included in the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (6)
1. A two-dimensional homojunction logic inverter, comprising: an insulating substrate, from which a first electrode group, a dielectric layer, a two-dimensional semiconductor layer, and a second electrode group are sequentially upward;
The dielectric layer includes: a first dielectric layer and a second dielectric layer;
The first electrode group includes: the output electrode is not connected with the input electrode; the output electrode is L-shaped, the upper part of the short side of the output electrode is connected with the two-dimensional semiconductor layer, the upper part of the long side of the L-shaped left side of the output electrode is connected with the first dielectric layer, and the output electrode, the first dielectric layer and the two-dimensional semiconductor layer form a suspension area; an adjustable homogeneous junction potential barrier is formed between the suspended channel region and the non-suspended channel region under the action of an electrostatic field;
the length of the first dielectric layer is shorter than that of the output electrode, the length of the second dielectric layer is slightly longer than that of the input electrode, and the second dielectric layer is arranged above the input electrode and between the input electrode and the output electrode;
the second electrode group includes: a driving electrode and a ground electrode; wherein a left side of the driving electrode is aligned with a left side of the two-dimensional semiconductor layer, a length of the driving electrode being shorter than the first dielectric layer;
the right side of the ground electrode is aligned with the right side of the two-dimensional semiconductor layer, and the length of the ground electrode is shorter than the input electrode.
2. The two-dimensional homojunction logic inverter according to claim 1, wherein the insulating substrate is a silicon wafer with an oxide layer, a flexible insulating PET or a sapphire substrate.
3. The two-dimensional homojunction logic inverter according to claim 1, wherein the first electrode group and the second electrode group are metal electrodes or two-dimensional semi-metals, and the thickness of the first electrode group and the second electrode group is 30-50nm;
The dielectric layer is made of silicon oxide, aluminum oxide or hafnium oxide, and the thickness of the dielectric layer is 20-50nm.
4. The two-dimensional homojunction logic inverter of claim 1, wherein said two-dimensional semiconductor layer is a two-dimensional transition metal chalcogenide nanoplatelet, wherein said two-dimensional transition metal chalcogenide nanoplatelet comprises: and the thickness of the two-dimensional semiconductor layer is 0.7-10nm.
5. A method of fabricating a two-dimensional homojunction logic inverter as claimed in any one of claims 1 to 4, comprising the steps of:
S1, preparing an insulating substrate and a two-dimensional semiconductor layer;
s2, depositing a first electrode group on the insulating substrate, wherein the first electrode group comprises an output electrode and an input electrode, and the output electrode is not connected with the input electrode;
S3, depositing a dielectric layer above the first electrode group, wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, the length of the first dielectric layer is shorter than that of the output electrode, and the length of the second dielectric layer is slightly longer than that of the input electrode;
S4, assembling the two-dimensional semiconductor layer above the dielectric layer by adopting a wet transfer process, and contacting one side of the output electrode and leaving a suspended area;
And S5, depositing a second electrode group above the two-dimensional semiconductor layer to finish the preparation of the two-dimensional homojunction logic inverter, wherein the second electrode group comprises a driving electrode and a grounding electrode.
6. The method for manufacturing a two-dimensional homojunction logic inverter according to claim 5, wherein the wet transfer process comprises:
Spin-coating PMMA glue on a substrate with the two-dimensional semiconductor layer material, and controlling the drying temperature to 120 ℃ and the drying time to 1-2min to obtain a PMMA film;
Immersing the substrate into deionized water and hydrofluoric acid solution in a preset proportion, etching off a silicon dioxide oxide layer on the surface of the silicon wafer, and obtaining a PMMA film with the two-dimensional semiconductor layer material;
Immersing the PMMA film into deionized water solution to clean hydrofluoric acid solution remained on the PMMA film, fishing out the cleaned PMMA film, precisely stacking the cleaned PMMA film on the upper surface of the dielectric layer by utilizing a precise transfer platform and contacting with the output electrode, and finally immersing the PMMA film with the two-dimensional semiconductor layer material into acetone solution to remove PMMA glue, thereby completing transfer.
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