CN116110483B - Method, apparatus and storage medium for testing semiconductor device - Google Patents
Method, apparatus and storage medium for testing semiconductor device Download PDFInfo
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- CN116110483B CN116110483B CN202310387274.XA CN202310387274A CN116110483B CN 116110483 B CN116110483 B CN 116110483B CN 202310387274 A CN202310387274 A CN 202310387274A CN 116110483 B CN116110483 B CN 116110483B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1202—Word line control
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The present disclosure provides a method, apparatus and storage medium for testing a semiconductor device, the method comprising: first data is written into a first memory cell connected to a test word line, second data is written into a second memory cell connected to an edge dummy word line, and the test word line is adjacent to the edge dummy word line. Controlling the opening of the edge virtual word line, and electrically connecting the first memory cell with the second memory cell through a preset bit line so as to enable the first memory cell to share charges with the second memory cell, and forming test data in the first memory cell; when the test data is opposite to the first data, it is determined that the edge dummy word line is in a potential controllable state. In the disclosure, when the test data formed in the first memory cell is opposite to the first data, it is indicated that the second memory cell successfully writes the second data, and it can be determined that the edge dummy word line is in a potential controllable state. The testing method can accurately test the state of the edge virtual word line so as to ensure the normal performance of the aging test.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method and apparatus for testing a semiconductor device, and a storage medium.
Background
Before the semiconductor device is shipped, burn-in test is required to be performed on the semiconductor device to ensure good reliability of the semiconductor device after shipment. Before the semiconductor device is subjected to burn-in test, it is necessary to determine whether a dummy word line provided at the edge of the memory array in the semiconductor device is in a potential controllable state to ensure normal progress of the burn-in test.
Currently, when determining the state of an edge dummy word line, the edge dummy word line is generally operated, and whether leakage current is generated in a test word line near the edge of a memory array of the edge dummy word line is detected to indirectly determine the state of the edge dummy word line. However, this test method is part of the burn-in test and does not determine the state of the edge dummy word line; in addition, in the operation process of the semiconductor device, the test word line is easily influenced by the opening and closing of other word lines in the memory array to generate leakage current, and the accuracy of the test method is not high.
Disclosure of Invention
The following is a summary of the subject matter of the detailed description of the present disclosure. This summary is not intended to limit the scope of the claims.
The present disclosure provides a method, apparatus and storage medium for testing a semiconductor device.
In a first aspect of the present disclosure, the present disclosure provides a method for testing a semiconductor device, the method for testing a semiconductor device including:
writing first data to a first memory cell connected to a test word line, the first data being one of low level data and high level data;
writing second data into a second memory cell connected with an edge virtual word line, wherein the second data is the other one of the low-level data and the high-level data, the first memory cell and the second memory cell are connected with a preset bit line, and the test word line is adjacent to the edge virtual word line;
controlling the opening of the edge virtual word line, wherein the first memory cell is electrically connected with the second memory cell through the preset bit line so as to enable the first memory cell and the second memory cell to share charges, and test data are formed in the first memory cell;
reading the test data in the first storage unit;
when the test data is opposite to the first data, determining that the edge virtual word line is in a potential controllable state.
According to some embodiments of the present disclosure, the controlling the opening of the edge dummy word line, the first memory cell is electrically connected to the second memory cell through the preset bit line, so that the first memory cell and the second memory cell share charges, and test data is formed in the first memory cell, including:
Controlling the edge virtual word line to be opened, and conducting the second memory cell and the preset bit line so as to enable the second memory cell to share charges with the preset bit line;
controlling a sense amplifier to be turned on and controlling the edge dummy word line to be turned off so as to enable the preset bit line to be kept at a high potential or enable the preset bit line to be kept at a low potential;
and controlling the conduction of the preset bit line and the first storage unit so as to enable the preset bit line and the first storage unit to share charges and form test data in the first storage unit.
According to some embodiments of the present disclosure, controlling the edge dummy word line to be turned on, and turning on the second memory cell and the preset bit line to enable the second memory cell to share charges with the preset bit line includes:
precharging the preset bit line;
and controlling the edge virtual word line to be opened for a first preset time period so as to enable the second memory cell to share charges with the preset bit line.
According to some embodiments of the present disclosure, controlling the preset bit line to be turned on with the first memory cell so that the preset bit line and the first memory cell share charges, and forming test data in the first memory cell includes:
Controlling the test word line to be opened for a second preset time period so as to enable the preset bit line to be in charge sharing with the first storage unit;
and controlling the test word line and the sense amplifier to be closed, and forming the test data in the first memory cell.
According to some embodiments of the present disclosure, writing second data to a second memory cell connected to an edge dummy word line includes:
precharging the preset bit line;
controlling the opening of the edge virtual word line;
controlling the preset bit line to be in a high potential, and writing the high-level data into the second storage unit; or controlling the preset bit line to be at a low potential, and writing the low-level data into the second memory cell;
and controlling the edge virtual word line to be closed.
According to some embodiments of the present disclosure, reading the test data in the first memory cell includes:
precharging the preset bit line;
and controlling the test word line to be started and controlling the sense amplifier to be started so as to read the test data in the first memory cell.
According to some embodiments of the present disclosure, the semiconductor device is burn-in tested when the edge dummy word line is determined to be in a potential controllable state.
According to some embodiments of the present disclosure, the method for testing a semiconductor device further includes:
and when the test data is the same as the first data, determining that the edge virtual word line is in a potential uncontrollable state.
In a second aspect of the present disclosure, there is provided a test apparatus for a semiconductor device, the test apparatus for a semiconductor device including:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the method of testing a semiconductor device according to the first aspect of the present disclosure.
In a third aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium, which when executed by a processor of a test apparatus of a semiconductor device, enables the test apparatus of a semiconductor device to perform the test method of a semiconductor device according to the first aspect of the present disclosure.
In the testing method, the testing device and the storage medium of the semiconductor device, first data are written into a first storage unit connected with a testing word line, second data are written into a second storage unit connected with an edge virtual word line, the first storage unit is controlled to share charges with the second storage unit through a preset bit line, and when the testing data formed in the first storage unit are opposite to the first data written in advance, the second storage unit is indicated to successfully write the second data, so that the edge virtual word line can be determined to be in a potential controllable state. The testing method provided by the invention can accurately test the state of the edge virtual word line so as to ensure the normal operation of the aging test.
Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to identify like elements. The drawings, which are included in the description, are some, but not all embodiments of the disclosure. Other figures can be obtained from these figures without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart illustrating a method of testing a semiconductor device according to an exemplary embodiment.
FIG. 2 is a schematic diagram of a memory array shown according to an example embodiment.
Fig. 3 is a circuit diagram illustrating a test method employed in accordance with an exemplary embodiment.
Fig. 4 is a block diagram showing a structure of a test apparatus of a semiconductor device according to an exemplary embodiment.
Fig. 5 is a block diagram of a test apparatus for semiconductor devices according to an exemplary embodiment.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person skilled in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be arbitrarily combined with each other.
Before the semiconductor device is shipped, burn-in test is required to be performed on the semiconductor device to ensure good reliability of the semiconductor device after shipment. Before the semiconductor device is subjected to the burn-in test, it is required to determine whether an edge dummy word line provided at an edge of the memory array in the semiconductor device is in a potential controllable state to ensure normal progress of the burn-in test.
Currently, when determining the state of an edge dummy word line, the edge dummy word line is generally operated, and whether leakage current is generated in a test word line near the edge of a memory array of the edge dummy word line is detected to indirectly determine the state of the edge dummy word line. However, this test method is part of the burn-in test and does not determine the state of the edge dummy word line; in addition, in the operation process of the semiconductor device, the test word line is easily influenced by the opening and closing of other word lines in the memory array to generate leakage current, and the accuracy of the test method is not high.
In view of this, the present disclosure provides a method for testing a semiconductor device, the method for testing a semiconductor device including: first data is written into a first memory cell connected to the test word line, wherein the first data is one of low-level data and high-level data. And writing second data into a second memory cell connected with the edge virtual word line, wherein the second data is the other one of low-level data and high-level data, the first memory cell and the second memory cell are connected with a preset bit line, and the test word line is adjacent to the edge virtual word line. Controlling the opening of the edge virtual word line, and electrically connecting the first memory cell with the second memory cell through a preset bit line so as to enable the first memory cell to share charges with the second memory cell, and forming test data in the first memory cell; reading test data in the first storage unit; when the test data is opposite to the first data, it is determined that the edge dummy word line is in a potential controllable state. According to the method, the second data is written into the second memory cell connected with the edge virtual word line, the first data is written into the first memory cell connected with the test word line, the first memory cell is controlled to share charges with the second memory cell through the preset bit line, and when the test data formed in the first memory cell is opposite to the first data written in advance, the second memory cell is indicated to successfully write the second data, so that the edge virtual word line can be determined to be in a potential controllable state. The testing method provided by the invention can accurately test the state of the edge virtual word line so as to ensure the normal operation of the aging test.
The disclosure is described below with reference to the drawings and specific embodiments. Exemplary embodiments of the present disclosure provide a method of testing a semiconductor device, as shown in fig. 1, fig. 1 is a flowchart illustrating a method of testing a semiconductor device according to an exemplary embodiment, the method of testing including the steps of:
step S100, writing first data into a first memory cell connected with a test word line, wherein the first data is one of low-level data and high-level data;
step 200, writing second data into a second memory cell connected with the edge virtual word line, wherein the second data is the other one of low level data and high level data, the first memory cell and the second memory cell are connected with a preset bit line, and the test word line is adjacent to the edge virtual word line;
step S300, controlling the opening of the edge virtual word line, wherein the first memory cell is electrically connected with the second memory cell through a preset bit line so as to enable the first memory cell and the second memory cell to share charges and form test data in the first memory cell;
step S400, reading test data in a first storage unit;
and S500, when the test data are opposite to the first data, determining that the edge virtual word line is in a potential controllable state.
In the method for testing a semiconductor device according to the present embodiment, a test machine is used as an execution body, and the test machine may be a machine for testing a memory function of the semiconductor device, for example, an ATE (Automatic Test Equipment, automatic semiconductor integrated circuit tester). The semiconductor device may be, for example, a memory such as DRAM (Dynamic Random Access Memory ), SRAM (Static RAM), RDRAM (Rambus DRAM), SDRAM (Synchronous DRAM), or the like, which is not limited by the present disclosure. In the following embodiments, a semiconductor device is described as a DRAM.
In step S100, the test word line may be a Word Line (WL) corresponding to row0 of the memory array edge shown in fig. 2, i.e., WL0, and the first memory cell may be a memory cell connected to WL0, for example, when the memory array is a two-dimensional array of 8×8, referring to fig. 2. When first data is written into a first memory cell connected to a test word line, the first data may be written into one first memory cell or may be written into a plurality of first memory cells. The first data is one of low level data and high level data, and since the data stored in the semiconductor device is binary data "0" and "1", the first data is data "0" when the first data is low level data, and the first data is data "1" when the first data is high level data.
In step S200, an edge Dummy Word Line (DWL) is a wiring that is provided in the semiconductor device and is provided at the edge of the memory array and does not perform an actual memory function, and the edge dummy word line may be provided around the memory array or may be provided in parallel with an actual word line in the memory array, as shown in fig. 2, and the edge dummy word line is adjacent to the test word line. The circuit structure of the edge dummy word line may be the same as the actual word line in the memory array with the second memory cell connected thereto. Since the object of the present disclosure is to test the state of the edge dummy word line, in this embodiment, the writing of the second data to the second memory cell connected to the edge dummy word line is performed regardless of whether the state of the edge dummy word line is in the potential controllable state, and in the subsequent step, the state of the edge dummy word line is determined by determining whether the writing of the second data is successful.
Since the first data written in the first memory cell is one of the low-level data and the high-level data, the second data written in the second memory cell is the other of the low-level data and the high-level data, and when the first data is the low-level data, namely, the data "0", the second data is the high-level data, namely, the data "1", and when the first data is the high-level data, namely, the data "1", the second data is the low-level data, namely, the data "0". When second data is written into a second memory cell connected to the edge dummy word line, the second memory cell corresponds to a position of the first memory cell where the first data is written. For example, referring to fig. 2, when writing data "0" in a first memory cell connected to WL0, an edge dummy word line is an edge dummy word line close to WL0, and writing high level data "1" in a first second memory cell connected to the edge dummy word line, at this time, a predetermined bit line is a first bit line in a memory array connecting the first memory cell and the second memory cell. When writing data 0 in all first memory cells connected with WL0, the edge virtual word line is an edge virtual word line close to WL0, and writing high-level data 1 in all second memory cells connected with the edge virtual word line, at this time, the preset bit lines are all bit lines in the memory array, and each preset bit line is connected with the corresponding first memory cell and second memory cell. The second memory cell connected to the edge dummy word line can only write data and cannot read data based on the characteristics of the second memory cell connected to the edge dummy word line.
In step S300, "on" of the signal line generally means that enable is enabled, for example, the transistor is turned on. Since the memory cell is composed of the transistor and the storage capacitor, when the gate of the transistor in the second memory cell is connected with the edge dummy word line, the opening of the edge dummy word line means that the level signal output by the edge dummy word line makes the transistor conduct.
Referring to fig. 3, after the edge dummy word line is turned on, the T2 transistor of the second memory cell is turned on, and at this time, the test word line may be controlled to be turned on, so that the T1 transistor of the first memory cell is turned on, and the second memory cell is electrically connected to the first memory cell through a preset bit line. In some embodiments, when the second data stored in the second memory cell is high-level data, the first data stored in the first memory cell is low-level data, and the storage capacitor C2 in the second memory cell may charge the preset bit line, so that the voltage of the preset bit line increases. The preset bit line is connected with the sense amplifier, the sense amplifier can start to raise the voltage of the preset bit line to a high potential (which will be described in detail later), and meanwhile, as the preset bit line is electrically connected with the first memory cell, the preset bit line at the high potential stores charges of the storage capacitor C1 in the first memory cell, so that test data is formed in the first memory cell, and the process of charge sharing between the first memory cell and the second memory cell is completed.
In other embodiments, when the second data stored in the second memory cell is low-level data, the first data stored in the first memory cell is high-level data, and the storage capacitor C2 in the second memory cell may discharge to the preset bit line, so that the voltage of the preset bit line is reduced. The preset bit line is connected with the sense amplifier, the sense amplifier can start to pull down the voltage of the preset bit line to a low potential (which will be described in detail later), meanwhile, as the first memory cell is electrically connected with the preset bit line, the charge stored in the storage capacitor C1 of the first memory cell is released through the preset bit line, and the preset bit line at the low potential stores the charge of the storage capacitor C1 in the first memory cell, so that test data is formed in the first memory cell, and the process of charge sharing between the first memory cell and the second memory cell is completed.
In step S400, the test data in the first memory cell in the test word line is read, for example, by controlling the test word line and a preset bit line corresponding to the first memory cell to read the test data, to determine whether the second data is stored in the second memory cell connected to the edge dummy word line, thereby determining whether the state of the edge dummy word line is in a potential controllable state.
In step S500, when the test data is opposite to the first data, for example, in some embodiments, when the first data written in the first memory cell is low-level data and the test data is high-level data, it is indicated that the low-level data originally written in the first memory cell is back-written as high-level data after charge sharing, it may be determined that the high-level data is written in the second memory cell connected to the edge virtual word line, and the charge sharing process is implemented, that is, it may be determined that the edge virtual word line is in a potential controllable state.
In other embodiments, when the first data written in the first memory cell is high-level data and the test data is low-level data, it is indicated that the high-level data originally written in the first memory cell is reversely written into the low-level data after charge sharing, and it can be determined that the low-level data is written in the second memory cell connected with the edge virtual word line, and the charge sharing process is implemented, that is, it can be determined that the edge virtual word line is in a potential controllable state. When the edge virtual word line is in a potential controllable state, the edge virtual word line has normal functions and can normally operate in a subsequent aging test.
In some possible implementations, the semiconductor device is burn-in tested when the edge dummy word line is determined to be in a potential controlled state.
The burn-in test is an electrical stress test method that uses voltage and high temperature to accelerate the electrical failure of a semiconductor device. The electrical stimulus applied during burn-in test reflects the worst case of operation of the semiconductor device and may simulate the entire life cycle of operating the semiconductor device. Burn-in testing may be used as a device reliability test, or as a production window to discover early failures of devices.
The state of the edge dummy word line mainly affects the voltage test conditions of the burn-in test. When the edge dummy word line is in a potential controllable state, a potential defect between the edge dummy word line and the test word line in the semiconductor device, such as a defect of a manufacturing material or an error in a manufacturing process, is tested by setting a high voltage difference between the edge dummy word line and the test word line adjacent to the edge dummy word line in the burn-in test. The high voltage difference is set, for example, high level voltage can be applied to the edge virtual word line, low level voltage can be applied to the test word line at the same time, after a certain duration, the high level voltage on the edge virtual word line can be pulled down, the low level voltage on the test word line can be pulled up at the same time, and a specific duration or period is circulated, so that the burn-in test is completed.
In one exemplary embodiment, the method of testing a semiconductor device further includes:
step S600, when the test data are the same as the first data, determining that the edge virtual word line is in a potential uncontrollable state.
In this embodiment, when the test data is the same as the first data, for example, when the first data written in the first memory cell is low-level data, the test data is also low-level data, or when the first data written in the first memory cell is high-level data, the test data is also high-level data, which means that in the foregoing embodiment, writing the second data into the second memory cell connected to the edge dummy word line fails, so that the first memory cell and the second memory cell cannot share charges. At this time, it can be determined that the edge dummy word line is in a fault state with uncontrollable potential, and the edge dummy word line does not have its normal function and cannot perform subsequent aging test.
In some possible implementations, a hint is issued when it is determined that the edge virtual word line is in a potential uncontrollable state.
In this embodiment, when it is determined that the edge virtual word line is in a fault state with uncontrollable potential, it is indicated that the edge virtual word line does not have its normal function, and cannot perform subsequent burn-in test, and at this time, the test machine sends out prompt information, where the prompt information may be information indicating that the edge virtual word line is in a fault state, or may be information for repairing or repairing the edge virtual word line. The prompt information can be sent in a prompt tone or can be sent out by popping up a prompt window on a display screen of the test machine to remind technicians.
In an exemplary embodiment, in step S300, controlling the edge dummy word line to be turned on, the first memory cell is electrically connected to the second memory cell through a preset bit line, so that the first memory cell and the second memory cell share charges, and test data is formed in the first memory cell, including:
step S310, controlling the opening of the edge virtual word line, and conducting the second memory cell and the preset bit line so as to enable the second memory cell and the preset bit line to share charges;
step S320, controlling the sense amplifier to be turned on and controlling the edge dummy word line to be turned off so as to keep the preset bit line at a high potential or to keep the preset bit line at a low potential;
in step S330, the preset bit line is controlled to be conducted with the first memory cell, so that the preset bit line and the first memory cell share charges, and test data is formed in the first memory cell.
In step S310, referring to fig. 3, the control edge dummy word line is turned on, and the T2 transistor in the second memory cell is turned on, at this time, the second memory cell is electrically connected to the predetermined bit line. In some embodiments, when the first data written in the second memory cell connected to the edge dummy word line is high level data, the storage capacitor C2 in the second memory cell may charge the preset bit line, so that the voltage of the preset bit line is increased, and the process of charge sharing between the second memory cell and the preset bit line is completed. In other embodiments, when the first data written in the second memory cell is low-level data, the storage capacitor C2 in the second memory cell may discharge to the preset bit line, so that the voltage of the preset bit line is reduced, and the process of charge sharing between the second memory cell and the preset bit line is completed.
In some possible embodiments, in step S310, controlling the edge dummy word line to be turned on to turn on the second memory cell and the predetermined bit line, so that the second memory cell and the predetermined bit line share charges, including:
step S311, pre-charging (precharge) the preset bit line;
in step S312, the edge dummy word line is controlled to be turned on for a first predetermined period of time, so that the second memory cell and the predetermined bit line share charges.
In step S311, referring to fig. 3, the test word Line and the edge dummy word Line are turned off, the sense amplifier is turned off, and the equalizer is turned on (hereinafter, the Precharge process may be understood as the same steps, which will not be repeated), where the equalizer may be a voltage equalizing circuit (Voltage Equalization Circuit), and the equalizer is controlled to be turned on, for example, the Precharge signal Line EQ may be controlled to send a Precharge signal to the equalizer so that the transistors T7, T8, and T9 are in a conductive state, so as to Precharge the preset Bit Line and the Bit Bar (Bit Line Bar, BLB) corresponding to the preset Bit Line, so that the voltages on the preset Bit Line and the Bit Bar are stabilized at a Precharge voltage (Vpre), and the Precharge voltage is half of the operating voltage VCC, that is, vpre=vcc/2. After the precharge is completed, the precharge signal line EQ is controlled to be turned off, that is, the equalizer is turned off, and the transistors T7, T8, and T9 are in the off state.
In step S312, with continued reference to fig. 3, the edge dummy word line is controlled to be turned on, for example, a level signal that can turn on the T2 transistor in the second memory cell may be input to the edge dummy word line so that the second memory cell is electrically connected to the preset bit line. The first preset time period may be a time period during which the storage capacitor C2 in the second storage unit sufficiently charges or discharges the preset bit line, and may be tRCD (RAS to CAS Delay), for example. The controlling the opening of the edge virtual word line for a first preset duration may be controlling the duration of the turn-on of the T2 transistor to be the first preset duration.
In some embodiments, when the second data written in the second memory cell is high-level data, the duration of the turn-on of the T2 transistor is controlled to be a first preset duration, so that the charge stored in the storage capacitor C2 in the second memory cell flows to the preset bit line, and the voltage of the preset bit line is pulled up to be greater than the pre-charge voltage Vpre, the voltage of the preset bit line may be denoted as vpre+Δv, and the process of performing charge sharing between the second memory cell and the preset bit line is completed, where Δv is a voltage difference affecting the preset bit line when the second memory cell performs charge sharing with the preset bit line.
In other embodiments, when the second data written in the second memory cell is low-level data, the duration of the turn-on of the T2 transistor is controlled to be a first preset duration, and the storage capacitor C2 in the second memory cell discharges to the preset bit line because the storage capacitor C2 in the second memory cell does not store charge, so that the voltage of the preset bit line is pulled down to be less than the pre-charge voltage Vpre, the voltage of the preset bit line can be expressed as Vpre- Δv, and the process of charge sharing between the second memory cell and the preset bit line is completed, where Δv is a voltage difference that affects the preset bit line when the second memory cell and the preset bit line perform charge sharing.
In step S320, with continued reference to fig. 3, the Sense Amplifier is controlled to be turned on, for example, a Sense signal line SAN (Sense-Amplifier N-Fet Control) and a Sense signal line SAP (Sense-Amplifier P-Fet Control) on the Sense Amplifier may be controlled to be turned on. In the sense amplifier, the sense signal line SAN is set to a logic 0 voltage, i.e., the ground voltage VSS, and the sense signal line SAP is set to a logic 1 voltage, i.e., the operating voltage VCC. T3 and T4 are N-type transistors that are turned on when the gate voltage is above a certain value, T5 and T6 are P-type transistors that are turned on when the gate voltage is below a certain value. The gate of the transistor T3 and the gate of the transistor T5 are connected with the inverted bit line, and the gate of the transistor T4 and the gate of the transistor T6 are connected with the preset bit line.
In some embodiments, when the second data written in the second memory cell is high level data, the voltage of the preset bit line is vpre+Δv, the voltage of the inverted bit line is the precharge voltage Vpre, and the voltage of the preset bit line is higher than the voltage of the inverted bit line. At this time, the transistor T4 is more conductive than the transistor T3, the bit bar line is electrically connected to the sense signal line SAN through the transistor T4, the voltage on the bit bar line is pulled down to the ground voltage VSS by the sense signal line SAN, and the transistor T3 is turned off. Further, since the voltage on the inverted bit line is the ground voltage VSS, the transistor T5 is turned on, the preset bit line is electrically connected to the sensing signal line SAP through the transistor T5, the voltage on the preset bit line is pulled up to the operating voltage VCC by the sensing signal line SAP, and the transistor T6 is turned off. The edge dummy word line is controlled to be closed under the condition that the sense amplifier is opened, for example, a level signal capable of turning off a T2 transistor in the second memory cell can be input to the edge dummy word line, and the second memory cell is disconnected from the edge dummy word line, so that the voltage on the preset bit line is at a stable working voltage VCC, that is, the preset bit line is kept at a high potential.
In other embodiments, when the second data written in the second memory cell is low level data, the voltage of the preset bit line is Vpre- Δv, the voltage of the inverted bit line is the precharge voltage Vpre, and the voltage of the inverted bit line is higher than the voltage of the preset bit line. At this time, the transistor T3 is more conductive than the transistor T4, the preset bit line is electrically connected to the sense signal line SAN through the transistor T3, the voltage on the preset bit line is pulled down to the ground voltage VSS by the sense signal line SAN, and the transistor T4 is turned off. Further, since the voltage on the preset bit line is the ground voltage VSS, the transistor T6 is turned on, the inverted bit line is electrically connected to the sensing signal line SAP through the transistor T6, the voltage on the inverted bit line is pulled up to the operating voltage VCC by the sensing signal line SAP, and the transistor T5 is turned off. The edge dummy word line is controlled to be turned off under the condition that the sense amplifier is turned on, for example, a level signal capable of turning off the T2 transistor in the second memory cell can be input to the edge dummy word line, and the second memory cell is disconnected from the edge dummy word line, so that the voltage on the preset bit line is at the stable ground voltage VSS, that is, the preset bit line is kept at a low potential.
In step S330, referring to fig. 3, the predetermined bit line is controlled to be turned on, for example, the test word line is controlled to be turned on, and the T1 transistor in the first memory cell is controlled to be turned on, and at this time, the first memory cell is electrically connected to the predetermined bit line.
In some embodiments, when the second data written in the second memory cell is high level data, since the sense amplifier is in an on state, the preset bit line is electrically connected to the sense signal line SAP providing the operating voltage VCC, and the voltage on the preset bit line is at the stable operating voltage VCC. The first data in the first memory cell is low-level data, the preset bit line can charge the first memory cell to store charges into the storage capacitor C1 in the first memory cell, and the process of charge sharing between the preset bit line and the first memory cell is completed, so that test data are formed in the first memory cell.
In other embodiments, when the second data written in the second memory cell is low level data, the preset bit line is electrically connected to the sense signal line SAN providing the ground voltage VSS, and the voltage on the preset bit line is at the stable ground voltage VSS because the sense amplifier is in the on state. The first data in the first memory cell is high-level data, the charges stored in the storage capacitor C1 in the first memory cell are released through the grounding of the preset bit line, the voltage of the preset bit line is still low, namely the ground voltage VSS, the storage capacitor C1 in the first memory cell does not store the charges, and the process of sharing the charges between the preset bit line and the first memory cell is completed, so that test data are formed in the first memory cell.
In some possible embodiments, in step S330, controlling the preset bit line to be turned on with the first memory cell so that the preset bit line and the first memory cell share charges, and forming test data in the first memory cell includes:
step S331, controlling the test word line to be opened for a second preset time period so as to enable the preset bit line to share charges with the first memory cell;
in step S332, the test word line and the sense amplifier are controlled to be turned off, and test data is formed in the first memory cell.
In this embodiment, referring to fig. 3, the test word line is controlled to be turned on, for example, a level signal capable of turning on the T1 transistor in the first memory cell may be input to the test word line, so that the first memory cell is electrically connected to the test word line. The second preset time period may be a time period during which the preset bit line sufficiently charges or discharges the storage capacitor C2 in the first memory cell, and may be tRCD, for example. The test word line is controlled to be turned on for a second preset duration, which may be the duration of controlling the T1 transistor to be turned on for the second preset duration.
In some embodiments, when the second data written in the second memory cell is high-level data, after the above steps, the voltage of the preset potential is the working voltage VCC, and the data written in the first memory cell is low-level data, after the test word line is turned on for a second preset period of time, the preset bit line at the high-level potential charges the storage capacitor C1 in the first memory cell, so that the storage capacitor C1 in the first memory cell stores charges, and the process of sharing charges between the preset bit line and the first memory cell is completed. Further, the test word line and the sense amplifier are turned off, for example, a level signal capable of turning off the T1 transistor in the first memory cell may be inputted to the test word line, the first memory cell is disconnected from the test word line, and at the same time, the sense signal line SAN and the sense signal line SAP on the sense amplifier are controlled to be turned off so that the charged charges remain in the storage capacitor C1 of the first memory cell, thereby forming test data in the first memory cell.
In other embodiments, when the second data written in the second memory cell is low-level data, after the above steps, the voltage of the preset potential is the ground voltage VSS, and the data written in the first memory cell is high-level data, after the test word line is turned on for a second preset period of time, the charge stored in the storage capacitor C1 in the first memory cell is released through the preset bit line grounded, and the voltage of the preset bit line is still the low potential, i.e., the ground voltage VSS. The preset bit line and the first storage unit share charges, so that the storage capacitor C1 in the first storage unit does not store charges, and the process of sharing charges between the preset bit line and the first storage unit is completed. Further, the sense amplifier and the test word line are turned off, for example, a level signal capable of turning off the T1 transistor in the first memory cell may be inputted to the test word line, and the first memory cell is turned off from the test word line, and at the same time, the sense signal line SAN and the sense signal line SAP on the sense amplifier are controlled to be turned off so that the storage capacitor C1 of the first memory cell maintains a state of not storing charges, thereby forming test data in the first memory cell.
It should be noted that, when the test word line is controlled to be turned off, the sense amplifier is still in an on state to ensure that the potential of the preset bit line is in a stable high-level potential or low-level potential state, so as to further ensure that the charge state in the storage capacitor C1 of the first memory cell maintains the state after the charge sharing with the preset bit line, ensure the accuracy of the formed test data, and avoid the charge sharing failure. That is, when the first memory cell forms the test data, the test word line is controlled to be turned off, and then the sense amplifier is controlled to be turned off.
In some possible embodiments, in step S100, writing first data to a first memory cell connected to a test word line includes:
step S110, pre-charging a preset bit line;
step S120, controlling the test word line to be opened;
step S130, controlling a preset bit line to be at a low potential, and writing low-level data into a first memory cell; or, controlling the preset bit line to be at a high potential, and writing high-level data into the first memory cell;
step S140, the test word line is controlled to be turned off.
In this embodiment, referring to fig. 3, the equalizer is controlled to be turned on, for example, the precharge signal line EQ is controlled to send a precharge signal to the equalizer, so that the transistors T7, T8, and T9 are in a conductive state, so as to precharge the preset bit line and the inverted bit line corresponding to the preset bit line, so that the voltages on the preset bit line and the inverted bit line are stabilized at a precharge voltage (Vpre), and the precharge voltage is half of the operating voltage VCC, that is, vpre=vcc/2. After the precharge is completed, the precharge signal line EQ is controlled to be turned off, that is, the equalizer is turned off, and the transistors T7, T8, and T9 are in the off state. The test word line is controlled to be turned on, so that the storage capacitor C1 in the first storage unit is conducted with the preset bit line.
In some embodiments, when the first data is low level data, the preset bit line is controlled to be at a low level, for example, the WE signal line may be controlled so that the T12 and T13 transistors are in a conducting state, and an external voltage is applied so that the voltage on the preset bit line is pulled to a logic 0 level by Input, namely, a ground voltage VSS, and at this time, the preset bit line is at a low level; the voltage on the inverted bit line is pulled by/Input to a logic 1 level, i.e., the operating voltage VCC, at which time the inverted bit line is at a high potential. At this time, the first memory cell may be discharged through the preset bit line, and after a specific time, the charge in the storage capacitor C1 of the first memory cell is discharged to a 0 state, and the test word line is controlled to be turned off, so that the first memory cell writes low level data.
In other embodiments, when the first data is high level data, the preset bit line is controlled to be at a high level, for example, the WE signal line may be controlled to make the T12 and T13 transistors in a conductive state, and an external voltage is applied to make the voltage on the preset bit line pulled to a logic 1 level by Input, that is, an operating voltage VCC, where the preset bit line is at a high level; the voltage on the inverted bit line is pulled by/Input to a logic 0 level, i.e., ground voltage VSS, at which time the inverted bit line is at a low level. At this time, the first memory cell may be charged through the preset bit line, and after a certain time, the storage capacitor C1 of the first memory cell is charged to store the charge, and the test word line is controlled to be turned off, so that the first memory cell writes high level data.
In some possible embodiments, in step S200, writing second data to a second memory cell connected to the edge dummy word line includes:
step S210, pre-charging a preset bit line;
step S220, controlling the opening of the edge virtual word line;
step S230, controlling a preset bit line to be at a high potential, and writing high-level data into a second memory cell; or, controlling the preset bit line to be at a low potential, and writing low-level data into the second memory cell;
step S240, controlling the edge virtual word line to be closed.
In this embodiment, referring to fig. 3, the equalizer is controlled to be turned on, for example, the precharge signal line EQ is controlled to send a precharge signal to the equalizer, so that the transistors T7, T8, and T9 are in a conductive state, so as to precharge the preset bit line and the inverted bit line corresponding to the preset bit line, so that the voltages on the preset bit line and the inverted bit line are stabilized at a precharge voltage (Vpre), and the precharge voltage is half of the operating voltage VCC, that is, vpre=vcc/2. After the precharge is completed, the precharge signal line EQ is controlled to be turned off, that is, the equalizer is turned off, and the transistors T7, T8, and T9 are in the off state. The edge dummy word line is controlled to be turned on, so that the storage capacitor C2 in the second memory cell is conducted with the preset bit line.
In some embodiments, when the first data is low level data, the second data written to the second memory cell is high level data. At this time, the preset bit line is controlled to be at a high potential, for example, the WE signal line can be controlled to make the transistors T12 and T13 be in a conducting state, and an external voltage is applied to make the voltage on the preset bit line be pulled to a logic 1 level by Input, namely, a working voltage VCC, and at this time, the preset bit line is at a high potential; the voltage on the inverted bit line is pulled by/Input to a logic 0 level, i.e., ground voltage VSS, at which time the inverted bit line is at a low level. At this time, the second memory cell may be charged through the preset bit line, and after a certain time, the storage capacitor C2 of the second memory cell is charged to store the charge, and the test word line is controlled to be turned off, so that the second memory cell writes high level data.
In other embodiments, when the first data is high level data, the second data written to the second memory cell is low level data. At this time, the preset bit line is controlled to be at a low potential, for example, the WE signal line can be controlled to make the transistors T12 and T13 be in a conducting state, and an external voltage is applied to make the voltage on the preset bit line pulled to a logic 0 level by Input, namely, the ground voltage VSS, and at this time, the preset bit line is at a low potential; the voltage on the inverted bit line is pulled by/Input to a logic 1 level, i.e., the operating voltage VCC, at which time the inverted bit line is at a high potential. At this time, the second memory cell may be discharged through the preset bit line, and after a specific time, the charge in the storage capacitor C2 of the second memory cell is discharged to a 0 state, and the edge dummy word line is controlled to be turned off, so that the second memory cell writes low level data.
In some possible embodiments, in step S400, reading test data in the first memory cell includes:
step S410, pre-charging a preset bit line;
in step S420, the test word line is controlled to be turned on, and the sense amplifier is controlled to be turned on, so as to read the test data in the first memory cell.
In this embodiment, referring to fig. 3, the equalizer is controlled to be turned on, for example, the precharge signal line EQ is controlled to send a precharge signal to the equalizer, so that the transistors T7, T8, and T9 are in a conductive state, so as to precharge the preset bit line and the inverted bit line corresponding to the preset bit line, so that the voltages on the preset bit line and the inverted bit line are stabilized at a precharge voltage (Vpre), and the precharge voltage is half of the operating voltage VCC, that is, vpre=vcc/2. After the precharge is completed, the precharge signal line EQ is controlled to be turned off, that is, the equalizer is turned off, and the transistors T7, T8, and T9 are in the off state. The test word line is controlled to be turned on, so that the storage capacitor C1 in the first storage unit is conducted with the preset bit line.
If the test data stored in the storage capacitor C1 in the first storage unit is low level data, the voltage of the storage unit C1 is smaller than the voltage of the preset bit line, the storage capacitor C1 in the first storage unit discharges to the preset bit line, so that the voltage on the preset bit line is smaller than Vpre, that is, the voltage of the preset bit line is Vpre- Δv, the voltage of the opposite bit line is the pre-charge voltage Vpre, and the voltage of the opposite bit line is higher than the voltage of the preset bit line. At this time, the transistor T3 is more conductive than the transistor T4, the preset bit line is electrically connected to the sense signal line SAN through the transistor T3, the voltage on the preset bit line is pulled down to the ground voltage VSS by the sense signal line SAN, and the transistor T4 is turned off. Further, since the voltage on the preset bit line is the ground voltage VSS, the transistor T6 is turned on, the inverted bit line is electrically connected to the sensing signal line SAP through the transistor T6, the voltage on the inverted bit line is pulled up to the operating voltage VCC by the sensing signal line SAP, and the transistor T5 is turned off. At this time, the voltage on the preset bit line is at a stable logic 0 voltage, and the transistors T10 and T11 are turned on by controlling the CSL signal line, so that the test data in the first memory cell is low level data by reading the logic 0 voltage of the preset bit line.
If the test data stored in the storage capacitor C1 in the first storage unit is high level data, the voltage of the storage unit C1 is greater than the voltage of the preset bit line, and the storage capacitor C1 in the first storage unit charges the preset bit line so that the voltage on the preset bit line is greater than Vpre, that is, the voltage of the preset bit line is vpre+Δv, the voltage of the opposite bit line is the pre-charge voltage Vpre, and the voltage of the preset bit line is higher than the voltage of the opposite bit line. At this time, the transistor T4 is more conductive than the transistor T3, the bit bar line is electrically connected to the sense signal line SAN through the transistor T4, the voltage on the bit bar line is pulled down to the ground voltage VSS by the sense signal line SAN, and the transistor T3 is turned off. Further, since the voltage on the inverted bit line is the ground voltage VSS, the transistor T5 is turned on, the preset bit line is electrically connected to the sensing signal line SAP through the transistor T5, the voltage on the preset bit line is pulled up to the operating voltage VCC by the sensing signal line SAP, and the transistor T6 is turned off. At this time, the voltage on the preset bit line is at a stable logic 1 voltage, and the transistors T10 and T11 are turned on by controlling the CSL signal line, so that the test data in the first memory cell is high level data by reading the logic 1 voltage of the preset bit line.
In the method for testing the semiconductor device, first data are written into a first storage unit connected with a test word line, second data are written into a second storage unit connected with an edge virtual word line, the first storage unit is controlled to share charges with the second storage unit through a preset bit line, and when the test data formed in the first storage unit are opposite to the first data written in advance, the second storage unit is indicated to successfully write the second data, so that the edge virtual word line can be determined to be in a potential controllable state. The testing method provided by the invention can accurately test the state of the edge virtual word line so as to ensure the normal operation of the aging test.
The present disclosure exemplarily provides a test apparatus for a semiconductor device, referring to fig. 4, fig. 4 is a block diagram illustrating a structure of a test apparatus for a semiconductor device according to an exemplary embodiment, the test apparatus being configured to be capable of performing a test method for a semiconductor device in the above-described embodiments of the present disclosure, the test apparatus comprising:
a first write module 100 configured to write first data, which is one of low-level data and high-level data, to a first memory cell connected to a test word line;
A second writing module 200 configured to write second data, which is the other of low level data and high level data, to a second memory cell connected to an edge dummy word line, the first memory cell and the second memory cell being connected to a preset bit line, the test word line being adjacent to the edge dummy word line;
the test data forming module 300 is configured to control the opening of the edge virtual word line, and the first memory cell is electrically connected with the second memory cell through a preset bit line, so that the first memory cell and the second memory cell share charges, and test data is formed in the first memory cell;
a reading module 400 configured to read test data in the first memory cell;
the judging module 500 is configured to determine that the edge virtual word line is in a potential controllable state when the test data is opposite to the first data.
The specific manner in which the respective modules perform the operations in the test apparatus for semiconductor devices in the above-described embodiments has been described in detail in the embodiments related to the method, and will not be described in detail herein.
Fig. 5 is a block diagram of a test apparatus for a semiconductor device, i.e., a test apparatus 600, according to an exemplary embodiment. For example, the test equipment 600 may be provided as a test station, such as an ATE station provided by the above-described embodiments. Referring to fig. 5, the test apparatus 600 includes a processor 601, and the number of the processors may be set to one or more according to necessity. The test device 600 further comprises a memory 602 for storing instructions, such as application programs, executable by the processor 601. The number of the memories can be set to one or more according to the requirement. Which may store one or more applications. The processor 601 is configured to execute instructions to perform the method of testing a semiconductor device described above.
It will be apparent to those skilled in the art that embodiments of the present disclosure may be provided as a method, apparatus (device), or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media having computer-usable program code embodied therein. Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, including, but not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
In one exemplary embodiment, a non-transitory computer readable storage medium including instructions is provided, which may be provided to a test apparatus of a semiconductor device, such that the test apparatus of the semiconductor device is capable of performing the test method of the semiconductor device provided by the exemplary embodiments of the present disclosure. The non-transitory computer readable storage medium includes, for example, a memory 602 of instructions executable by a processor 601 of the test apparatus 600 to perform the method of testing a semiconductor device described above. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.
The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (devices) and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of additional identical elements in an article or apparatus that comprises the element.
While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present disclosure without departing from the spirit or scope of the disclosure. Thus, given that such modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the intent of the present disclosure is to encompass such modifications and variations as well.
Claims (9)
1. A method of testing a semiconductor device, the method comprising:
writing first data to a first memory cell connected to a test word line, the first data being one of low level data and high level data;
writing second data into a second memory cell connected with an edge virtual word line, wherein the second data is the other one of the low-level data and the high-level data, the first memory cell and the second memory cell are connected with a preset bit line, and the test word line is adjacent to the edge virtual word line;
Controlling the opening of the edge virtual word line, wherein the first memory cell is electrically connected with the second memory cell through the preset bit line so as to enable the first memory cell and the second memory cell to share charges, and test data are formed in the first memory cell;
reading the test data in the first storage unit;
when the test data are opposite to the first data, determining that the edge virtual word line is in a potential controllable state;
the controlling the opening of the edge dummy word line, the first memory cell being electrically connected to the second memory cell through the preset bit line, so that the first memory cell and the second memory cell share charges, and test data are formed in the first memory cell, including:
controlling the edge virtual word line to be opened, and conducting the second memory cell and the preset bit line so as to enable the second memory cell to share charges with the preset bit line;
controlling a sense amplifier to be turned on and controlling the edge dummy word line to be turned off so as to enable the preset bit line to be kept at a high potential or enable the preset bit line to be kept at a low potential;
And controlling the conduction of the preset bit line and the first storage unit so as to enable the preset bit line and the first storage unit to share charges and form test data in the first storage unit.
2. The method of claim 1, wherein controlling the edge dummy word line to turn on the second memory cell and the predetermined bit line to charge share the second memory cell and the predetermined bit line comprises:
precharging the preset bit line;
and controlling the edge virtual word line to be opened for a first preset time period so as to enable the second memory cell to share charges with the preset bit line.
3. The method of claim 1, wherein controlling the predetermined bit line to be turned on with the first memory cell to charge share the predetermined bit line with the first memory cell, and forming test data in the first memory cell, comprises:
controlling the test word line to be opened for a second preset time period so as to enable the preset bit line to be in charge sharing with the first storage unit;
And controlling the test word line and the sense amplifier to be closed, and forming the test data in the first memory cell.
4. The method for testing a semiconductor device according to claim 1, wherein writing second data to a second memory cell connected to an edge dummy word line comprises:
precharging the preset bit line;
controlling the opening of the edge virtual word line;
controlling the preset bit line to be in a high potential, and writing the high-level data into the second storage unit; or controlling the preset bit line to be at a low potential, and writing the low-level data into the second memory cell;
and controlling the edge virtual word line to be closed.
5. The method according to any one of claims 1 to 4, wherein reading the test data in the first memory cell comprises:
precharging the preset bit line;
and controlling the test word line to be started and controlling the sense amplifier to be started so as to read the test data in the first memory cell.
6. The method for testing a semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is subjected to a burn-in test when it is determined that the edge dummy word line is in a potential controllable state.
7. The method for testing a semiconductor device according to any one of claims 1 to 4, further comprising:
and when the test data is the same as the first data, determining that the edge virtual word line is in a potential uncontrollable state.
8. A test apparatus for a semiconductor device, the test apparatus comprising:
a processor;
a memory for storing processor-executable instructions;
wherein the processor is configured to perform the method of testing a semiconductor device of any of claims 1-7.
9. A non-transitory computer readable storage medium, characterized in that instructions in the non-transitory computer readable storage medium, when executed by a processor of a testing apparatus of a semiconductor device, enable the testing apparatus of a semiconductor device to perform the testing method of a semiconductor device of any one of claims 1-7.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0397200A (en) * | 1989-09-08 | 1991-04-23 | Fujitsu Ltd | Decode circuit for semiconductor storage device |
| JP2001093297A (en) * | 1999-09-24 | 2001-04-06 | Toshiba Corp | Test device for semiconductor |
| JP2001256800A (en) * | 2000-03-14 | 2001-09-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| CN1700356A (en) * | 2004-05-18 | 2005-11-23 | 富士通株式会社 | Semiconductor memory |
| KR20080000842A (en) * | 2006-06-28 | 2008-01-03 | 주식회사 하이닉스반도체 | A circuit for detecting defect of semiconductor memory device |
| CN101127242A (en) * | 2006-08-17 | 2008-02-20 | 富士通株式会社 | Semiconductor memory and system |
| KR20120018452A (en) * | 2010-08-23 | 2012-03-05 | 주식회사 하이닉스반도체 | Burn-in test circuit of semiconductor memory apparatus |
| CN108597550A (en) * | 2018-07-11 | 2018-09-28 | 睿力集成电路有限公司 | Sense amplifier and apply its storage device and sequential control method |
| CN109065090A (en) * | 2018-07-11 | 2018-12-21 | 长鑫存储技术有限公司 | Sense amplifier and the storage device and sequential control method for applying it |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100454259B1 (en) * | 2001-11-02 | 2004-10-26 | 주식회사 하이닉스반도체 | Semiconductor Memor Device having a Monitoring Circuit |
-
2023
- 2023-04-12 CN CN202310387274.XA patent/CN116110483B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0397200A (en) * | 1989-09-08 | 1991-04-23 | Fujitsu Ltd | Decode circuit for semiconductor storage device |
| JP2001093297A (en) * | 1999-09-24 | 2001-04-06 | Toshiba Corp | Test device for semiconductor |
| JP2001256800A (en) * | 2000-03-14 | 2001-09-21 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
| CN1700356A (en) * | 2004-05-18 | 2005-11-23 | 富士通株式会社 | Semiconductor memory |
| KR20080000842A (en) * | 2006-06-28 | 2008-01-03 | 주식회사 하이닉스반도체 | A circuit for detecting defect of semiconductor memory device |
| CN101127242A (en) * | 2006-08-17 | 2008-02-20 | 富士通株式会社 | Semiconductor memory and system |
| KR20120018452A (en) * | 2010-08-23 | 2012-03-05 | 주식회사 하이닉스반도체 | Burn-in test circuit of semiconductor memory apparatus |
| CN108597550A (en) * | 2018-07-11 | 2018-09-28 | 睿力集成电路有限公司 | Sense amplifier and apply its storage device and sequential control method |
| CN109065090A (en) * | 2018-07-11 | 2018-12-21 | 长鑫存储技术有限公司 | Sense amplifier and the storage device and sequential control method for applying it |
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