CN115691632B

CN115691632B - Test control system and method

Info

Publication number: CN115691632B
Application number: CN202211280194.6A
Authority: CN
Inventors: 石昊明; 刘明; 杨媛媛; 李彦
Original assignee: Sunlune Technology Beijing Co Ltd
Current assignee: Shenglong Singapore Pte Ltd
Priority date: 2022-10-19
Filing date: 2022-10-19
Publication date: 2023-07-07
Anticipated expiration: 2042-10-19
Also published as: CN115691632A

Abstract

The invention provides a test control system and a test control method. The register is used for acquiring N first test instructions in a first test mode from the upper computer; the test vector conversion unit is used for pulling N first test instructions from the register, generating a first address corresponding to the first test instructions, and sending the first address and the first test instructions to the BIST unit according to a preset time sequence; the BIST unit is used for testing the memory according to the actions indicated by the N first test instructions after detecting the N first test instructions and the first addresses corresponding to the N first test instructions respectively. According to the method and the device, the memory can be tested at any moment, and when the first test instruction is written into the register, the time sequence is not required to be considered, so that the test efficiency of the memory is improved.

Description

Test control system and method

Technical Field

The embodiment of the application relates to the technical field of integrated circuits, in particular to a test control system and a test control method.

Background

With the development of integrated circuits, the scale of the chip is larger and the integration level is higher, and meanwhile, the failure rate of the memory in the chip is also improved. Any bit defect in the memory can cause the adverse phenomena of system crash, restarting application program breakdown and the like when the chip is applied to devices such as mobile phones, tablets and the like. Therefore, how to perform fault test on the memory in the chip and how to improve the efficiency of fault test on the memory are important in the research of the integrated circuit field.

The existing memory test method is to introduce a BIST (Built in Self Test, built-in self-test) unit into a chip, send a test excitation signal to the BIST unit by an external device of the chip, and perform fault test on a memory in the chip by running built-in self-test software and hardware after the BIST unit receives the test excitation signal sent by the external device.

However, on the one hand, the BIST test pins of the chip are not usually packaged during mass production of the chip, so when the memory in the chip needs to be tested after the chip is packaged, a test excitation signal cannot be introduced from an external device, and therefore, the memory in the chip cannot be subjected to fault test; on the other hand, the external device needs to serially transmit all information of the test excitation signal to the BIST unit according to a strict time sequence, so that the signal transmission efficiency is low, errors are easy to transmit, the test efficiency is reduced, and the test resources are wasted.

Disclosure of Invention

The embodiment of the application provides a test control system and a test control method, which can realize high-efficiency test of a memory at any time.

In a first aspect, an embodiment of the present application provides a test control system, including a register, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit;

The register is used for acquiring N first test instructions in a first test mode from the upper computer, wherein the first test mode is one test mode in M preset test modes, and N, M is a positive integer;

the test vector conversion unit is used for pulling N first test instructions from the register, generating a first address corresponding to the first test instruction aiming at each first test instruction in the N first test instructions, and sending the first address and the first test instruction to the BIST unit according to a preset time sequence;

the BIST unit is used for testing the memory according to the actions indicated by the N first test instructions after detecting the N first test instructions and the first addresses corresponding to the N first test instructions respectively.

In a second aspect, an embodiment of the present application provides a test control method applied to a test control system, where the system includes a register, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit.

The register acquires N first test instructions in a first test mode from the upper computer, wherein the first test mode is one test mode in M preset test modes, and N, M is a positive integer;

The test vector conversion unit pulls N first test instructions from the register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to the BIST unit according to a preset time sequence;

after detecting N first test instructions and first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to actions indicated by the N first test instructions.

In summary, through the technical scheme of the application, when testing the memory, N first test instructions in the first test mode are written into the register through the upper computer; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to a BIST unit according to a preset time sequence; after detecting N first test instructions and first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to actions indicated by the N first test instructions. Compared with the existing test method, the test excitation signal is input to the BIST unit from the test pin corresponding to the BIST unit through the external equipment, and the embodiment of the application writes the first test instruction into the register through the pin of the register, so that the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during mass production of chips is avoided; meanwhile, in the existing test method, the external device needs to transmit all information of the test stimulus signal required by the memory to the BIST unit according to a strict timing, so that the signal transmission efficiency is low and errors are easy to transmit. According to the embodiment of the application, only the first test instruction is required to be written in the corresponding position of the register, the time sequence is not required to be considered, the efficiency of testing the memory is improved, and the operation complexity of a tester is reduced.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a conventional memory test system according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a test control system according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a control module according to an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of another control module according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of another control module according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of another control module according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of another control module according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of another test control system provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of another test control system provided in an embodiment of the present application;

Fig. 10 is a flow chart of a test control method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or server that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The test control system and the test control method provided by the embodiment of the application can be applied to any field needing to test the memory.

With the development of integrated circuits, the density and speed of integrated circuits are higher and higher, and meanwhile, the failure rate of the integrated circuits is also improved. In the case of a memory in an integrated circuit chip, when ECC (Error Correcting Code, error checking and correction) is not performed on the memory, production defects of any bit in the memory can cause problems such as system crashes and application program crashes when the chip including the memory is used in a mobile phone, a tablet and other devices.

The current test projects for chips mainly include:

CP (Circuit Probing) testing, which is a test object between wafer fabrication and packaging throughout the chip fabrication process, is directed to each Die (Die before chip unpackaged) in a whole wafer (wafer) in order to ensure that each Die in the whole wafer substantially meets the device's characteristics or design specifications, typically including verification of voltage, current, timing and function. Can be used to detect the process level of factory manufacture.

The FT (Final Test) Test is the Final function and performance Test performed after the chip is packaged. After the CP test is finished, the chip is packaged, and the test object of the FT test is the packaged chip. The level of technology of the packaging plant can be detected by the FT test.

At present, in the CP and FT test stages, a method for testing a memory in a chip is to introduce a BIST unit into the chip, send a test excitation signal to the BIST unit by external equipment of the chip, and perform fault test on the memory in the chip by running built-in self-test software and hardware after the BIST unit receives the test excitation signal sent by the external equipment.

The BIST test is to embed a test circuit and a test algorithm into a chip to be tested, and the test circuit can be controlled to automatically generate test excitation and obtain test response only by introducing a control signal, and the test circuit can automatically compare the test response with an expected response to determine whether the tested circuit has faults.

Fig. 1 is a schematic diagram of a conventional memory test system according to an embodiment of the present application.

As shown in FIG. 1, a built-in self-test BIST unit is added to the chip design. In the CP and FT test stage, all information of the test excitation signal required by the memory is generated by external equipment (such as a computer, an upper computer and the like), all information of the test excitation signal required by the memory is serially input into the BIST unit through a test probe or a test pin led out by the BIST unit, the BIST unit issues test data to the memory through running built-in self-test hardware and software according to the received test excitation signal, the defect or fault of a tested circuit is checked, test result data is obtained, and the test result data is fed back to the external equipment through the test probe or the test pin led out by the BIST unit; after receiving the test result data, the external equipment analyzes the test result data to obtain the bad point condition in the memory.

As described above, on the one hand, in the prior art, the test pins corresponding to the BIST unit are not usually packaged during mass production of the chip, so when the chip is packaged and the memory inside the chip needs to be tested, the test excitation signal cannot be introduced from the external device, and therefore, the fault test cannot be performed on the memory; on the other hand, the prior art does not consider the repeated information in the test excitation signal required by the memory, and all the information of the test excitation signal required by the memory is required to be serially transmitted to the BIST unit according to strict time sequence requirements every time the test excitation signal is input to the BIST unit, so that the signal transmission efficiency is low, errors are easy to transmit, the test efficiency is reduced, and the test resources are wasted.

In order to solve the above technical problems, an embodiment of the present application provides a test control system and a method, where the system includes a register disposed inside a chip, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit. When testing the memory, writing N first test instructions in a first test mode into the register through the upper computer; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to a BIST unit according to a preset time sequence; after detecting N first test instructions and first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to actions indicated by the N first test instructions. Compared with the existing test method, the method has the advantages that all information of the test excitation signals required by the memory is input to the BIST unit from the test pins corresponding to the BIST unit through the external equipment, and the first test instructions are written into the register through the pins of the register, so that the problem that the memory cannot be tested any more due to the fact that the test pins corresponding to the BIST unit are not packaged during chip mass production is avoided; meanwhile, in the existing test method, the external device needs to transmit all information of the test stimulus signal required by the memory to the BIST unit according to a strict timing, so that the signal transmission efficiency is low and errors are easy to transmit. According to the embodiment of the application, only the first test instruction is required to be written in the corresponding position of the register, the time sequence is not required to be considered, the efficiency of testing the memory is improved, and the operation complexity of a tester is reduced.

The following describes the technical solutions of the embodiments of the present application in detail through some embodiments. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Fig. 2 is a schematic diagram of a test control system according to an embodiment of the present application.

As shown in FIG. 2, a test control system includes a register, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit;

It should be noted that the M test modes are test modes required by the BIST unit to perform a complete test on the memory.

It should be noted that the number of registers in fig. 2 is merely exemplary, and the number of registers is not specifically limited in the present application.

Memory testing requires the use of a large number of test instructions, and therefore, under the constraint of limited test time, it is important to select an efficient test method.

The existing test method utilizes external equipment to operate a signal line connected to a serial input pin of the BIST unit, and sends all information of test excitation signals to the BIST unit by forming high and low levels through power on and off. However, in the conventional test method, the bandwidth of the signal line connected to the serial input pin of the BIST unit is small, and only 1 bit can be transmitted per clock, so that the transmission efficiency of the test stimulus signal is low and an error is easily transmitted. According to the embodiment of the application, the test excitation signals required by the BIST unit are analyzed to obtain repeated information in the test excitation signals, the repeated information in the test excitation signals is led into the test vector conversion unit, the test vector conversion unit generates the repeated information in the test excitation signals, different information in the test excitation signals is written into the register by the upper computer, and the test vector conversion unit sends the repeated information in the generated test excitation signals and the different information in the test excitation signals acquired from the register to the BIST unit according to the time sequence and the bandwidth required by the BIST unit, so that the BIST unit tests the memory based on the test excitation signals. When a tester operates the upper computer to write different information in the test excitation signals into the register, the time sequence does not need to be considered, the complexity of test operation is reduced, and the test efficiency is improved.

In the embodiment of the application, a first test instruction is configured to a register by an upper computer, and in consideration of that repeated information in test excitation signals required by a BIST unit is address information, address information corresponding to N first test instructions in each first test mode is the same, and a first address corresponding to the first test instruction is automatically generated by a test vector conversion unit; and sending a first address corresponding to the first test instruction and the first test instruction to the BIST unit. When an instruction is sent to the BIST unit, a tester only needs to operate the upper computer, N first test instructions in a first test mode are written into the register, the time sequence is not needed to be considered, and under each clock signal, a multi-bit first test instruction can be written into the register, for example, the first test instruction is 32 bits, and under one clock signal, 32 bits can be written into the register, so that the issuing time of the test instruction is shortened; the address information is not required to be sent by operating the external device to continuously send high and low levels to the serial input pin of the BIST unit, and the test vector conversion unit can automatically generate the first address corresponding to each first test instruction, so that the test method is more efficient and simpler for testers.

The embodiment of the present application does not specifically limit the type of memory.

In one example, the memory is DRAM (Dynamic Random Access Memory ).

In another example, the memory is SDRAM (Synchronous Dynamic Random Access Memory ).

The order in which the test vector conversion unit sends the first address corresponding to the first test instruction and the first test instruction to the BIST unit is not particularly limited in the embodiments of the present application.

In one example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction, and sends the first address to the BIST unit first, and then sends the first test instruction to the BIST unit.

In another example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction, and sends the first test instruction to the BIST unit first, and then sends the first address to the BIST unit.

In another example, for each of the N first test instructions, the test vector conversion unit generates a first address corresponding to the first test instruction, and sends the first test instruction and the first address corresponding to the first test instruction to the BIST unit simultaneously.

The manner in which the test vector conversion unit sends the first address corresponding to the first test instruction and the first test instruction to the BIST unit is not particularly limited in the embodiments of the present application.

In one example, the test vector conversion unit sends a first address corresponding to a first test instruction to the BIST unit through an address signal line; the first test instruction is sent to the BIST unit through 32 data signal lines.

In another example, the test vector conversion unit sends a first address corresponding to a first test instruction to the BIST unit through a signal line, and then sends the first test instruction to the BIST unit.

In some embodiments, the test vector conversion unit is specifically configured to generate, when a first signal is detected, a first address corresponding to a first test instruction, where the first signal is used to instruct the host computer to successfully write N first test instructions into the register.

Specifically, after writing N first test instructions in a first test mode into the register, the upper computer sends a first signal to the test vector conversion unit through the register; when the test vector conversion unit detects a first signal, a first address corresponding to a first test instruction is generated; for each first test instruction of the N first test instructions, the test vector conversion unit sends the generated first address corresponding to the first test instruction and the first test instruction to the BIST unit.

In the prior art, an external device is operatively connected to a signal line of a serial input pin of a BIST unit, and sends address information and instruction information to the BIST unit by forming high and low levels by power on and off, and once data is sent in error, the BIST unit cannot be prevented from receiving, so that the BIST unit receives the error information. According to the embodiment of the application, the upper computer controls the test vector conversion unit, when the upper computer writes the first test instruction into the register, if an error is written, the first signal can not be sent to the test vector conversion unit, so that the test vector conversion unit can not send the first test instruction to the BIST unit, the BIST unit is prevented from receiving the error information, and the error operation is performed on the register.

It should be noted that the test vector conversion unit may be used as an independent functional unit in the test control system, or may be integrated with other functional units in the control module, which is not specifically limited in this application.

The following embodiments illustrate the present application by taking the test vector conversion unit integrated in the control module as an example.

Fig. 3 is a schematic diagram of a control module according to an embodiment of the present application.

As shown in fig. 3, the control module includes a test vector conversion unit and a result acquisition unit.

In some embodiments, the BIST unit is configured to send a third signal to the test vector conversion unit after receiving a last test instruction in the first test mode;

and the test vector conversion unit is used for sending a fourth signal to the register based on the third signal, so that when the upper computer determines that the first test mode is the last test mode in the M test modes based on the fourth signal, the upper computer sends a second signal to the result acquisition unit.

Writing a first test instruction corresponding to the last test mode in the M test modes into a register by the upper computer, and sending a first signal to the test vector conversion unit, wherein after the first signal is detected by the test vector conversion unit, a first address corresponding to the first test instruction is generated for each first test instruction in N first test instructions in the last test mode, and the first address corresponding to the first test instruction and the first test instruction are sent to the BIST unit; the BIST unit sends a third signal to the test vector conversion unit when receiving the last first test instruction in the N first test instructions; the test vector conversion unit sends a fourth signal to the register based on the third signal, and after the upper computer connected with the register detects the fourth signal, the BIST unit is determined to successfully receive a first test instruction corresponding to the last test mode in the M test modes, and a second signal is sent to the result acquisition unit.

In some embodiments, the result acquisition unit is configured to send a first request to the BIST unit when a second signal is detected, where the first request is used to request a test result of the memory, and the second signal is triggered after each test instruction in the M test modes is tested;

and the BIST unit is used for acquiring the test result from the memory based on the first request and sending the test result to the result acquisition unit.

In some embodiments, the result obtaining unit is configured to generate a result obtaining instruction and a second address corresponding to the result obtaining instruction when the second signal is detected, and send the second address corresponding to the result obtaining instruction and the result obtaining instruction to the BIST unit;

and the BIST unit is used for acquiring the test result from the memory according to the result acquisition instruction after receiving the result acquisition instruction and the second address, and sending the test result to the result acquisition unit.

The number of bits of the test result obtained by the result obtaining unit at a time from the memory by the BIST unit according to the embodiment of the present application is not particularly limited.

In one example, the result acquisition unit sends a result acquisition instruction to the BIST unit upon detecting the second signal, the BIST unit acquires 32-bit test result data from the memory each time based on the result acquisition instruction, and sends the test result data to the result acquisition unit.

In another example, the result acquisition unit sends a result acquisition instruction to the BIST unit upon detecting the second signal, the BIST unit acquires 64-bit test result data from the memory each time based on the result acquisition instruction, and sends the test result data to the result acquisition unit.

Fig. 4 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 4, the control module includes a test vector conversion unit, a result acquisition unit, and a result processing unit.

In some embodiments, the result processing unit is configured to obtain a test result from the result obtaining unit, analyze the test result, obtain problem data of the memory, and send the problem data to the register.

The problem data comprises at least one of the number of rows with dead pixels in the memory, the row number of the front P rows in the rows with dead pixels in the memory, and the total dead pixel number of the memory, wherein P is a positive integer.

In one example, the result processing unit is configured to obtain a test result from the result obtaining unit, analyze the test result, obtain a line number of a line where a bad point exists in the memory and a line number of a previous P line in the line where the bad point exists in the memory, and send the line number of the line where the bad point exists in the memory and the line number of the previous P line in the line where the bad point exists in the memory to the register.

In another example, the result processing unit is configured to obtain a test result from the result obtaining unit, and analyze the test result to obtain a line number of a line where a bad point exists in the memory, a line number of a previous P line in the line where the bad point exists in the memory, and a total number of bad points in the memory; and the number of the rows with the dead pixels in the memory, the row numbers of the front P rows in the rows with the dead pixels in the memory and the total dead pixels of the memory are sent to a register.

In the prior art, only the test result is fed back to the external device by the BIST unit, and in order to obtain the condition that the dead pixel exists in the memory, the test result needs to be analyzed by a tester. According to the embodiment of the invention, the result processing unit is introduced into the control module in the chip, the test result of the memory can be directly subjected to statistical analysis in the chip, the row number of the row with the dead pixel in the memory, the row number of the front P row in the row with the dead pixel in the memory and the total dead pixel number in the memory are obtained, the row number of the row with the dead pixel in the memory, the row number of the front P row in the row with the dead pixel in the memory and the total dead pixel number in the memory are sent to the register, and a tester can directly obtain the dead pixel condition of the memory through the upper computer.

Fig. 5 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 5, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, and a timeout detection unit.

When the BIST unit has a defect or an abnormality, the BIST unit can not send a third signal to the test vector conversion unit or delay sending the third signal when receiving the last first test instruction in the N first test instructions in the first test mode; the test vector conversion unit cannot receive the third signal in time, and sends a fourth signal to the register based on the third signal, so that the control module is blocked, and the test of the memory is affected. According to the embodiment of the application, the timeout detection unit is introduced to time the execution time of the first test mode, and when the execution time of the first test mode exceeds the preset execution time, the test is stopped, so that the control module is prevented from being blocked.

In some embodiments, the timeout detecting unit is configured to start timing after detecting the first signal, stop timing after receiving the third signal sent by the BIST unit, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector converting unit when the execution time of the first test mode is greater than a preset execution time, where the fifth signal is used to instruct to stop testing the memory.

In some embodiments, the timeout detecting unit is configured to start timing after detecting the first signal, stop timing when the timing time of the timeout detecting unit reaches a preset execution time of the first test mode or after receiving the third signal sent by the BIST unit, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector converting unit when the execution time is greater than the preset execution time, where the fifth signal is used to instruct to stop testing the memory.

In some embodiments, the test vector conversion unit is further configured to send a tenth signal to the timeout detecting unit when the first signal is detected, where the tenth signal is used to instruct the timeout detecting unit to start timing;

the timeout detecting unit is used for stopping timing when detecting that the tenth signal starts timing, and stopping timing when the timing time of the timeout detecting unit reaches the preset execution time of the first test mode or after receiving the third signal sent by the BIST unit, so as to obtain the execution time corresponding to the first test mode, and sending a fifth signal to the test vector converting unit when the execution time is greater than the preset execution time, wherein the fifth signal is used for indicating to stop testing the memory.

In some embodiments, the timeout detecting unit is further configured to send a sixth signal to the register when the execution time corresponding to the first test mode is greater than the preset execution time, where the sixth signal is used to indicate that the execution time of the first test mode exceeds the preset execution time.

In some embodiments, the preset execution time is a maximum execution time corresponding to the first test mode sent by the register.

In some embodiments, the preset execution time is an average execution time corresponding to the first test mode sent by the register.

Due to the structural nature of memory cells, it is necessary to refresh for a period of time, referred to as a refresh cycle, to maintain the stored data information.

In order to avoid the problem that in the process of acquiring the test result, when the refresh period of the memory is close, the acquisition of the test result is not stopped, and the memory is refreshed, so that the test result in the memory is lost and the test result cannot be acquired any more, the embodiment of the application introduces a refresh control unit into the control module.

Fig. 6 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 6, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, and a refresh control unit.

And the refresh control unit is used for sending a seventh signal to the result acquisition unit when detecting that the difference value between the starting time and the current time of the next refresh cycle of the memory is smaller than a preset value, wherein the seventh signal is used for indicating to stop acquiring the test result.

The refresh control unit is further configured to send an eighth signal to the test vector conversion unit when detecting that the difference between the start time and the current time of the next refresh cycle of the memory is smaller than a preset value, where the eighth signal is used to instruct the test vector conversion unit to send a refresh instruction to the BIST unit;

and the BIST unit is used for refreshing the memory once based on the refresh command.

Fig. 7 is a schematic diagram of another control module according to an embodiment of the present application.

As shown in fig. 7, the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, a refresh control unit, and a storage unit.

The result acquisition unit is used for sending the test result to the storage unit when the test result is received, the storage unit stores the test result, and after the storage unit finishes storing the test result, a ninth signal is sent to the register and used for indicating that the test result is stored.

The embodiment of the present application does not specifically limit the type of the memory cell.

In one example, the memory cell is an SRAM (Static Random Access Memory ).

In another example, the memory unit is Flash (Flash memory).

In the prior art, when the external device reads the test result from the BIST unit, it is required to read one bit of test result at a time in a serial manner, and the reading efficiency is low. According to the embodiment of the application, the storage unit is introduced, the test data of the BIST unit are stored in the storage unit, and when the external equipment needs to read the test result, the multi-bit test result can be read from the storage unit at one time, so that the reading efficiency of the test result is improved.

After the result processing unit sends the problem data to the register, the problem data comprises at least one of the number of rows with the dead pixels in the memory, the number of the rows with the front P rows in the rows with the dead pixels in the memory, and the total number of the dead pixels in the memory, P is a positive integer, and after the upper computer connected with the register receives the problem data, the storage unit with the dead pixels in the memory indicated in the problem data can be turned off, and the storage unit with the dead pixels in the memory can be repaired. In order to repair a storage unit with a bad point in a memory, the embodiment of the application introduces a repair unit in a test control system.

Fig. 8 is a schematic diagram of another test control system according to an embodiment of the present application.

As shown in fig. 8, the test system includes a repair unit, a register, a control module connected with the register, and a built-in self-test BIST unit connected with the control module, where the control module includes a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, a storage unit, and a refresh control unit.

In some embodiments, the memory includes P redundant rows and P redundant columns.

When the number of the rows with the dead pixels in the memory is smaller than or equal to P, the repair unit is used for sending the row numbers with the dead pixels in the memory to the memory so that the memory repairs the rows with the dead pixels in the memory by using P redundant rows.

When the number of lines with bad points in the memory is larger than P, only the line repairing function is used, and all the memory units with bad points in the memory cannot be repaired. In the embodiment of the present application, when the number of rows of the dead pixel in the memory is greater than P, the row-column repair function is used.

When the number of rows of the dead pixel in the memory is greater than P, the repair unit is used for determining column information of Q redundant columns used for repairing the dead pixel from P redundant columns based on the dead pixel position in the test result, determining row information of R redundant rows used for repairing the dead pixel from P redundant columns, transmitting the column information of the Q redundant columns and the row information of the R redundant rows to the memory, so that the memory determines Q redundant columns from the P redundant columns based on the column information of the Q redundant columns and the row information of the R redundant rows, determining R redundant rows from the P redundant columns, and repairing the memory unit with the dead pixel in the memory by using the Q redundant columns and the R redundant rows, wherein Q, R is a positive integer.

In summary, through the technical scheme of the application, when testing the memory, N first test instructions in the first test mode are written into the register through the upper computer; then, a test vector conversion unit connected with the register automatically generates a first address corresponding to the first test instruction when receiving a first signal, and sends the first address corresponding to the first test instruction and the first test instruction to a BIST unit according to a preset time sequence; the BIST unit tests the memory according to the N first test instructions. Compared with the existing test method, the method has the advantages that all information of the test excitation signals required by the memory is input to the BIST unit from the test pins corresponding to the BIST unit through the external equipment, and the first test instructions are written into the register through the pins of the register, so that the problem that the memory cannot be tested any more due to the fact that the test pins corresponding to the BIST unit are not packaged during chip mass production is avoided; meanwhile, in the existing test method, the external equipment needs to send all information of the test excitation signals required by the memory to the BIST unit according to a strict time sequence, and in the embodiment of the application, only the first test instruction is written in the corresponding position of the register without considering the time sequence, so that the test efficiency of the memory is improved, and the operation complexity of a tester is reduced.

Fig. 9 is a schematic diagram of a test control system according to an embodiment of the present application.

Taking a test control system as an example, the test control system comprises a repair unit, a register, a control module (LTC) connected with the register, and a built-in self-test BIST unit connected with the control module, wherein the control module comprises a test vector conversion unit, a result acquisition unit, a result processing unit, a timeout detection unit, a storage unit and a refresh control unit; taking the memory to be tested as DRAM for example.

Table 1 shows the test patterns required to perform a complete test on a DRAM.

TABLE 1

As shown in table 1, the M preset test patterns include 3 first test patterns, a first test pattern 1, a first test pattern 2, and a first test pattern 3. The first test pattern 1 includes first test instructions P1, P2, P3, P4, and P5, and first addresses A, B, C, D and E corresponding to the first test instructions P1, P2, P3, P4, and P5; the first test pattern 2 includes first test instructions P6, P7, P8, P9, and P10, and corresponding first addresses A, B, C, D and E; the first test pattern 3 includes first test instructions P11, P12, P13, P14, and P15, and corresponding first addresses A, B, C, D and E.

The above-mentioned P1 to P15 are 32-bit data.

The address information corresponding to the three first test modes is A, B, C, D and E, so that the host computer only needs to write 5 first test instructions P1 to P5 (ltc_cmd= { P5, P4, P3, P2, P1 }) corresponding to the first test mode 1, 5 first test instructions P6 to P10 (ltc_cmd= { P10, P9, P8, P7, P6 }) corresponding to the first test mode 2, and 5 first test instructions P11 to P15 (ltc_cmd= { P15, P14, P13, P12, P11 }) corresponding to the first test mode 3 into the registers in a divided manner, and the test vector conversion unit generates the first addresses A, B, C, D and E corresponding to the first test instructions in the three first test modes.

The test procedure for the memory is as follows:

the upper computer writes the preset execution time corresponding to the first test mode 1 into the super-time detection unit through a register.

After writing the preset execution time corresponding to the first test mode 1 into the register, the upper computer writes 5 first test instructions P1 to P5 corresponding to the first test mode 1 into the register (ltc_cmd= { P5, P4, P3, P2, P1 }), and after writing the last first test instruction, pulls up the test enable signal (the test enable signal after pulling up corresponds to the first signal in the above embodiment).

When the test vector conversion unit detects that the test enabling signal is pulled high, generating a first address A corresponding to P1 and sequentially sending the first address A and the first address P1 to the BIST unit; generating a first address B corresponding to the P2 and sequentially sending the first address B and the P2 to the BIST unit; generating a first address C corresponding to the P3 and sequentially sending the first address C and the P3 to the BIST unit; generating a first address D corresponding to the P4 and sequentially sending the first address D and the P4 to the BIST unit; generating a first address E corresponding to the P5 and sequentially sending the first address E and the P5 to the BIST unit.

When the upper computer writes the last first test instruction in the first test mode 1, and pulls up the test enabling signal through the register, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled up test enabling signal, and the tenth signal is used for indicating the timeout detection unit to start timing.

When the BIST unit receives the last first test instruction P5 of the 5 first test instructions, the test busy signal is pulled down (the pulled down test busy signal corresponds to the third signal in the above embodiment); when detecting the first addresses corresponding to the 5 first test instructions P1 to P5 and the first test instructions P1 to P5 in the first test mode 1, the BIST unit performs corresponding operation on the memory according to the actions indicated by the P1, P2, P3, P4 and P5.

And stopping timing when the timeout detection unit detects that the test busy signal after being pulled down or the timing time of the timeout detection unit reaches the preset execution time of the first test mode 1.

If the timeout detection unit does not detect the pulled-down test busy signal when the timing time reaches the preset execution time of the first test mode 1, a fifth signal is sent to the test vector conversion unit, and the fifth signal is used for indicating to stop testing the memory; the timeout detecting unit also feeds back timeout information (corresponding to the sixth signal in the above embodiment) of the first test mode 1 to the register.

After the test vector conversion unit detects that the test busy signal is pulled down, the test completion signal is pulled up (the pulled up test completion signal corresponds to the fourth signal in the above embodiment).

After the upper computer connected with the register detects that the test completion signal is pulled high, the upper computer writes the preset execution time corresponding to the first test mode 2 into the super-time detection unit through the register.

After writing the preset execution time corresponding to the first test mode 2 into the register, the upper computer writes 5 first test instructions P6-P10 in the first test mode 2 into the register, (ltc_cmd= { P10, P9, P8, P7, P6 }), and after writing the last first test instruction P10, pulls up a test enable signal (the pulled up test enable signal is equivalent to the first signal in the above embodiment), when the test vector conversion unit detects that the test enable signal is pulled up, generates a first address a corresponding to P6 and sequentially sends the first address a and P6 to the BIST unit; generating a first address B corresponding to the P7 and sequentially sending the first address B and the P7 to the BIST unit; generating a first address C corresponding to the P8 and sequentially sending the first address C and the P8 to the BIST unit; generating a first address D corresponding to the P9 and sequentially sending the first address D and the P9 to the BIST unit; generating a first address E corresponding to the P10 and sequentially sending the first address E and the P10 to the BIST unit.

When the upper computer writes the last first test instruction P10 in the first test mode 2 and pulls up the test enabling signal through the register, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled up test enabling signal, and the tenth signal is used for indicating the timeout detection unit to start timing.

When the BIST unit receives the last first test instruction P10 of the 5 first test instructions, the test busy signal is pulled down (the pulled down test busy signal corresponds to the third signal in the above embodiment); when detecting the first addresses corresponding to the 5 first test instructions P6 to P10 and the first test instructions P6 to P10 in the first test mode 1, the BIST unit performs corresponding operation on the memory according to the actions indicated by the P6, P7, P8, P9 and P10.

And stopping timing when the timeout detection unit detects that the test busy signal after being pulled down or the timing time of the timeout detection unit reaches the preset execution time of the first test mode 2.

If the timeout detection unit does not detect the pulled-down test busy signal when the timing time reaches the preset execution time of the first test mode 2, a fifth signal is sent to the test vector conversion unit, and the fifth signal is used for indicating to stop testing the memory; the timeout detecting unit also feeds back timeout information of the first test mode 2 to the register.

And after the test vector conversion unit detects that the test busy signal is pulled down, the test completion signal is pulled up.

After the upper computer connected with the register detects that the test completion signal is pulled high, the upper computer writes the preset execution time corresponding to the first test mode 3 into the super-time detection unit through the register.

After writing the preset execution time corresponding to the first test mode 3 into the register, the upper computer writes 5 first test instructions P11-P15 in the first test mode 3 into the register, (ltc_cmd= { P15, P14, P13, P12, P11 }), and after writing the last first test instruction P15, pulls up a test enable signal (the pulled up test enable signal is equivalent to the first signal in the above embodiment), when the test vector conversion unit detects that the test enable signal is pulled up, generates a first address a corresponding to P11 and sequentially sends the first address a and P11 to the BIST unit; generating a first address B corresponding to the P12 and sequentially sending the first address B and the P12 to the BIST unit; generating a first address C corresponding to the P13 and sequentially sending the first address C and the P13 to the BIST unit; generating a first address D corresponding to the P14 and sequentially sending the first address D and the P14 to the BIST unit; generating a first address E corresponding to the P15 and sequentially sending the first address E and the P15 to the BIST unit.

When the upper computer writes the last first test instruction P15 in the first test mode 3, and pulls up the test enabling signal through the register, the test vector conversion unit sends a tenth signal to the timeout detection unit based on the pulled up test enabling signal, where the tenth signal is used to instruct the timeout detection unit to start timing.

When the BIST unit receives the last first test instruction P15 of the 5 first test instructions, the test busy signal is pulled down (the pulled down test busy signal corresponds to the third signal in the above embodiment); the BIST unit performs a corresponding operation on the memory according to actions indicated by P11, P12, P13, P14 and P15 when detecting the first addresses corresponding to the 5 first test instructions P11 to P15 in the first test mode 3 and the first test instructions P11 to P15 respectively.

The timeout detecting unit stops timing when detecting that the test busy signal after being pulled down or the timing time of the timeout detecting unit reaches the preset execution time of the first test mode 3.

If the timeout detection unit does not detect the pulled-down test busy signal when the timing time reaches the preset execution time of the first test mode 3, a fifth signal is sent to the test vector conversion unit, and the fifth signal is used for indicating to stop testing the memory; the timeout detecting unit also feeds back timeout information of the first test mode 3 to the register.

The method comprises the steps that 5 first test instructions in each of three first test modes required by the DRAM and first addresses corresponding to the first test instructions are sent to a BIST unit according to time sequences required by the BIST unit, the BIST unit respectively performs three operations on the DRAM according to the three first test modes, and after the three operations are completed, the BIST unit performs a complete test on the DRAM.

After the upper computer connected with the register detects that the test completion signal is pulled high, the upper computer confirms that the first test instruction in the last first test mode of the three first test modes required by the DRAM is successfully received by the BIST unit, and the upper computer pulls up the result acquisition enabling signal (the pulled-up result acquisition enabling signal is equivalent to the second signal in the embodiment) through the register, generates a result acquisition instruction and a second address corresponding to the result acquisition instruction after the result acquisition enabling signal is detected to be pulled high by the result acquisition unit, and sends the second address and the result acquisition instruction to the BIST unit.

Mode	Second address (F)	Second address (G)	Second address (H)
				Result acquisition mode	P16	P17	P18

TABLE 2

Table 2 shows an instruction for obtaining test results by the BIST required by the DRAM, as shown in Table 2, the result obtaining unit generates a second address F corresponding to the result obtaining instruction P16 and the result obtaining instruction P16, and sends the second address F and the result obtaining instruction P16 to the BIST unit; the result acquisition unit generates a second address G corresponding to the result acquisition instruction P17 and the result acquisition instruction P17, and sends the second address G and the result acquisition instruction P17 to the BIST unit; the result obtaining unit generates a second address H corresponding to the result obtaining instruction P18 and the result obtaining instruction P18, and sends the second address H and the result obtaining instruction P18 to the BIST unit.

When the BIST unit detects 3 result acquisition instructions P16, P17, P18 and second addresses F, G and H corresponding to P16, P17 and P18 respectively, the BIST unit acquires test results from the memory according to actions indicated by P16, P17 and P18 and sends the test results to the result acquisition unit.

The DRAM is exemplified as comprising 2048 rows, each row comprising 128 bits.

The BIST unit acquires 32-bit test result data from the memory every time, and the test result of each row in the DRAM is returned to the result acquisition unit for 4 times, wherein 0 in the test result indicates that the corresponding position in the DRAM is normal, and 1 indicates that the corresponding position in the DRAM is a dead point.

When the result acquisition unit receives the test result, the test result is sent to a storage unit (SRAM) and a result processing unit, respectively.

After the memory cell completes the storage of the test result, a result read completion signal (corresponding to the ninth signal in the above embodiment) for indicating that the memory cell completes the storage of the test result is sent to the register.

After detecting the result reading completion signal, the external device may read the test result from the memory cell, and may read the multi-bit test result from the memory cell each time.

When detecting that the difference value between the starting time and the current time of the next refresh cycle of the memory is smaller than a preset value, the refresh control unit sends a seventh signal to the result acquisition unit, wherein the seventh signal is used for indicating to stop the acquisition of the test result; simultaneously sending an eighth signal to the test vector conversion unit, the eighth signal being used to instruct the test vector conversion unit to send a refresh instruction to the BIST unit; and the BIST unit is used for refreshing the memory once based on the refresh command.

In the embodiment of the application, the memory DRAM includes 16 redundant rows and 16 redundant columns.

The result processing unit analyzes the received test result to obtain problem data of the memory, wherein the problem data comprises: the number of rows with dead pixels in the DRAM, the row number of the first 16 rows in the rows with dead pixels in the DRAM and the total dead pixels of the DRAM; and sends the issue data to the register.

When the number of lines with the dead pixel in the DRAM is less than or equal to 16, the repair unit sends the line number with the dead pixel to the DRAM so that the DRAM repairs the line with the dead pixel in the DRAM by using 16 redundant lines.

When the number of lines of bad points in the DRAM is larger than 16, the upper computer acquires a test result from the storage unit and sends the test result to the repair unit; the repair unit determines column information of a plurality of redundant columns for repairing bad points from 16 redundant columns based on the bad point information of the storage units in the DRAM indicated by the test result, determines row information of a plurality of redundant rows for repairing bad points from 16 redundant rows, and sends the column information of the redundant columns for repairing bad points and the row information of the redundant rows for repairing bad points to the DRAM, so that the DRAM determines the redundant columns for repairing bad points from 16 redundant columns based on the column information of the redundant columns for repairing bad points and the row information of the redundant rows, determines the redundant rows for repairing bad points from 16 redundant rows, and repairs the storage units with bad points in the DRAM by using the redundant columns for repairing bad points and the redundant rows.

In summary, through the technical scheme of the application, when testing the memory, N first test instructions in a first test mode are written into the register through the upper computer, wherein the first test mode is one of preset M test modes; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to a BIST unit according to a preset time sequence; after detecting N first test instructions and first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to actions indicated by the N first test instructions. When the memory is tested, all information of test excitation signals required by the memory is not required to be generated according to a strict time sequence, only first test instructions belonging to different parts in the test excitation signals are required to be written into a register by an upper computer, the time sequence is not required to be considered, and first addresses belonging to the same parts in the test excitation signals are automatically generated by a test vector conversion unit; the test vector conversion unit sends the generated first address and the first test instruction to the BIST unit according to a preset time sequence; the BIST unit tests the memory based on the received first test instruction. The testing efficiency of the memory is improved, and the operation complexity of the tester is reduced. Compared with the existing test method, the test excitation signal is input to the BIST unit from the test pin corresponding to the BIST unit through the external equipment, and the first test instruction is written into the register through the pin of the register, so that the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during mass production of chips is avoided.

FIG. 10 is a flow chart of a test control method according to an embodiment of the present application, which is applied to a test control system including a register, a test vector conversion unit connected to the register, and a built-in self-test BIST unit connected to the test vector conversion unit. As shown in fig. 10, the test control method includes the steps of:

s101, a register acquires N first test instructions in a first test mode from an upper computer, wherein the first test mode is one test mode in M preset test modes, and N, M is a positive integer;

s102, a test vector conversion unit pulls N first test instructions from a register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to a BIST unit according to a preset time sequence;

s103, after detecting N first test instructions and first addresses corresponding to the N first test instructions respectively, the BIST unit tests the memory according to actions indicated by the N first test instructions.

In some embodiments, after the upper computer successfully writes the N first test instructions into the register, sending a first signal to the test vector conversion unit; when the test vector conversion unit detects the first signal, a first address corresponding to the first test instruction is generated.

In some embodiments, the test control system further includes a result acquisition unit.

The BIST unit sends a third signal to the test vector conversion unit after receiving the last test instruction in the first test mode; the test vector conversion unit sends a fourth signal to the register based on the third signal; when the upper computer detects a fourth signal corresponding to the last test mode in the M test modes, the upper computer sends a second signal to the result acquisition unit; the result acquisition unit sends a first request to the BIST unit when detecting the second signal, and the BIST unit acquires a test result from the memory based on the first request and sends the test result to the result acquisition unit.

In some embodiments, the test control system further comprises a timeout detection unit.

The operation modes of the timeout detecting unit include mode 1 and mode 2.

Mode 1: the timeout detection unit starts timing after detecting the first signal, stops timing after receiving the third signal sent by the BIST unit, obtains the execution time corresponding to the first test mode, and sends a fifth signal to the test vector conversion unit when the execution time is greater than the preset execution time; the test vector conversion unit stops the test of the memory when detecting the fifth signal.

Mode 2: when the execution time corresponding to the first test mode is longer than the preset execution time, the timeout detection unit sends a fifth signal to the test vector conversion unit and also sends a sixth signal to the register; when the register detects the sixth signal, it is determined that the execution time of the first test mode exceeds the preset execution time.

In some embodiments, the preset execution time is a maximum execution time corresponding to the first test mode that the register sends to the timeout detecting unit.

In some embodiments, the test control system further comprises a refresh control unit.

The operation mode of the refresh control unit comprises the following steps: mode 1 and mode 2.

Mode 1: when detecting that the difference value between the starting time and the current time of the next refresh period of the memory is smaller than a preset value, the refresh control unit sends a seventh signal to the result acquisition unit; the result acquisition unit stops acquiring the test result when the seventh signal is detected.

Mode 2: when detecting that the difference value between the starting time and the current time of the next refresh cycle of the memory is smaller than a preset value, the refresh control unit sends a seventh signal to the result acquisition unit and also sends an eighth signal to the test vector conversion unit; the test vector conversion unit sends a refresh instruction to the BIST unit when detecting the eighth signal; the BIST unit refreshes the memory based on the refresh instruction.

In some embodiments, the test control system further comprises a memory unit.

The result acquisition unit sends the test result to the storage unit when receiving the test result; after the storage unit finishes receiving the test result, a ninth signal is sent to the register; the register determines that the test result storage is complete upon detection of the ninth signal.

In some embodiments, the test control system further comprises a result processing unit.

The result processing unit acquires a test result from the result acquisition unit, analyzes the test result to obtain problem data of the memory, and sends the problem data to the register;

the problem data includes at least one of the number of rows with bad points in the memory, the row number of the front P rows in the rows with bad points in the memory, and the total number of the bad points in the memory, wherein P is a positive integer.

In some embodiments, the test control system further includes a repair unit, where the memory includes P redundant rows and P redundant columns.

The repair method of the memory by the repair unit includes a method 1 and a method 2.

Mode 1: when the line number of the bad point in the memory is less than or equal to P, the repair unit sends the line number of the bad point in the memory to the memory; when the memory receives the line number with the dead pixel, P redundant lines are used for repairing the line with the dead pixel in the memory.

Mode 2: when the number of the rows of the dead pixel in the memory is larger than P, the repair unit determines column information of Q redundant columns used for dead pixel repair from P redundant columns based on the dead pixel position in the test result, determines row information of R redundant rows used for dead pixel repair from P redundant rows, and sends the column information of the Q redundant columns and the row information of the R redundant rows to the memory; the memory is based on column information of Q redundant columns and row information of R redundant rows, Q redundant columns are determined from P redundant columns, R redundant rows are determined from P redundant rows, and the Q redundant columns and the R redundant rows are used for repairing storage units with bad points in the memory, wherein Q, R is a positive integer.

According to the technical scheme, when the memory is tested, N first test instructions in a first test mode are written into a register through an upper computer, wherein the first test mode is one of M preset test modes; then, a test vector conversion unit connected with the register pulls N first test instructions from the register, generates a first address corresponding to the first test instruction for each first test instruction in the N first test instructions, and sends the first address and the first test instruction to a BIST unit according to a preset time sequence; after detecting N first test instructions and first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to actions indicated by the N first test instructions. When the memory is tested, all information of test excitation signals required by the memory is not required to be generated according to a strict time sequence, only first test instructions belonging to different parts in the test excitation signals are required to be written into a register by an upper computer, the time sequence is not required to be considered, and first addresses belonging to the same parts in the test excitation signals are automatically generated by a test vector conversion unit; the test vector conversion unit sends the generated first address and the first test instruction to the BIST unit according to a preset time sequence; the BIST unit tests the memory based on the received first test instruction. The testing efficiency of the memory is improved, and the operation complexity of the tester is reduced. Compared with the existing test method, the test excitation signal is input to the BIST unit from the test pin corresponding to the BIST unit through the external equipment, and the first test instruction is written into the register through the pin of the register, so that the problem that the memory cannot be tested any more due to the fact that the test pin corresponding to the BIST unit is not packaged during mass production of chips is avoided.

The preferred embodiments of the present application have been described in detail above with reference to the accompanying drawings, but the present application is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the present application within the scope of the technical concept of the present application, and all the simple modifications belong to the protection scope of the present application. For example, the specific features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various possible combinations are not described in detail. As another example, any combination of the various embodiments of the present application may be made without departing from the spirit of the present application, which should also be considered as disclosed herein.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In the several embodiments provided in this application, it should be understood that the disclosed system may be implemented in other ways. For example, the system embodiments described above are merely illustrative, e.g., the partitioning of the elements is merely a logical functional partitioning, and there may be additional partitioning in actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not implemented. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, circuits or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. For example, functional units in various embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The test control system is characterized by comprising a register, a test vector conversion unit connected with the register, and a built-in self-test BIST unit connected with the test vector conversion unit;

the register is used for acquiring N first test instructions in a first test mode from the upper computer, wherein the first test mode is one test mode in preset M test modes, and N, M is a positive integer;

the test vector conversion unit is used for pulling the N first test instructions from the register, generating a first address corresponding to each first test instruction in the N first test instructions, and sending the first address and the first test instructions to the BIST unit according to a preset time sequence, wherein the test vector conversion unit is also used for generating a first address corresponding to the first test instructions when a first signal is detected, and the first signal is used for indicating the upper computer to successfully write the N first test instructions into the register;

2. The system according to claim 1, further comprising a result acquisition unit;

the result acquisition unit is used for sending a first request to the BIST unit when a second signal is detected, wherein the first request is used for requesting the test result of the memory, and the second signal is triggered after the test of each test instruction in the M test modes is finished;

the BIST unit is used for acquiring the test result from the memory based on the first request and sending the test result to the result acquisition unit.

3. The system of claim 2, wherein the system further comprises a controller configured to control the controller,

the BIST unit is used for sending a third signal to the test vector conversion unit after receiving the last test instruction in the first test mode;

the test vector conversion unit is configured to send a fourth signal to the register based on the third signal, so that when the upper computer determines that the first test mode is the last test mode of the M test modes based on the fourth signal, send the second signal to the result acquisition unit.

4. A system according to claim 3, further comprising a timeout detection unit;

the timeout detection unit is configured to start timing after detecting the first signal, stop timing after receiving a third signal sent by the BIST unit, obtain an execution time corresponding to the first test mode, and send a fifth signal to the test vector conversion unit when the execution time is greater than a preset execution time, where the fifth signal is used to instruct to stop testing the memory.

5. The system of claim 4, wherein the timeout detection unit is further configured to send a sixth signal to the register when the execution time corresponding to the first test mode is greater than a preset execution time, the sixth signal being configured to indicate that the execution time of the first test mode exceeds the preset execution time.

6. The system of claim 5, wherein the predetermined execution time is a maximum execution time corresponding to the first test mode sent by the register.

7. The system according to claim 4, further comprising a refresh control unit configured to send a seventh signal to the result acquisition unit when detecting that a difference between a start time and a current time of a next refresh cycle of the memory is smaller than a preset value, the seventh signal being configured to instruct to stop acquisition of the test result.

8. The system of claim 7, wherein the refresh control unit is further configured to send an eighth signal to the test vector conversion unit when detecting that a difference between a start time and a current time of a next refresh cycle of the memory is less than the preset value, the eighth signal being configured to instruct the test vector conversion unit to send a refresh instruction to the BIST unit;

the BIST unit is used for refreshing the memory based on the refresh command.

9. The system of claim 7, further comprising a storage unit configured to obtain the test result from the result obtaining unit, and send a ninth signal to the register after the test result is obtained, the ninth signal being configured to indicate that the test result storage is completed.

10. The system of claim 9, further comprising a result processing unit;

the result processing unit is used for acquiring the test result from the result acquisition unit, analyzing the test result to obtain problem data of the memory, and sending the problem data to the register;

The problem data includes at least one of the number of rows with bad points in the memory, the row number of the previous P rows in the rows with bad points in the memory, and the total number of the bad points in the memory, wherein P is a positive integer.

11. The system according to claim 10, wherein the memory includes P redundant rows, and the system further includes a repair unit, when the number of rows in which the dead pixel exists in the memory is less than or equal to P, the repair unit is configured to send the row number in which the dead pixel exists in the memory to the memory, so that the memory repairs the row in which the dead pixel exists in the memory using the P redundant rows.

12. The system according to claim 11, wherein the memory further includes P redundant columns, when the number of rows of the bad pixels in the memory is greater than P, the repair unit is configured to determine, based on the position of the bad pixels in the test result, column information of Q redundant columns for bad pixel repair from the P redundant columns, and row information of R redundant rows for bad pixel repair from the P redundant columns, and send the column information of Q redundant columns and the row information of R redundant rows to the memory, so that the memory determines the Q redundant columns from the P redundant columns, determines the R redundant rows from the P redundant rows, and repairs the memory cells in the memory where the bad pixels exist using the Q redundant columns and the R redundant rows, each being a positive integer.

13. The test control method is characterized by being applied to a test control system, wherein the system comprises a register, a test vector conversion unit connected with the register, and a built-in self-test BIST unit connected with the test vector conversion unit;

the register acquires N first test instructions in a first test mode from an upper computer, wherein the first test mode is one of preset M test modes, and N, M is a positive integer;

the test vector conversion unit is used for pulling the N first test instructions from the register, generating a first address corresponding to each first test instruction in the N first test instructions, sending the first address and the first test instructions to the test vector conversion unit according to a preset time sequence, and generating a first address corresponding to the first test instructions when a first signal is detected, wherein the first signal is used for indicating the upper computer to successfully write the N first test instructions into the register, and generating a first address corresponding to the first test instructions when the first signal is detected, wherein the first signal is used for indicating the upper computer to successfully write the N first test instructions into the register;

After detecting the N first test instructions and the first addresses corresponding to the N first test instructions, the BIST unit tests the memory according to the actions indicated by the N first test instructions.