CN115547388A - Decoding method, memory storage device and memory control circuit unit - Google Patents

Decoding method, memory storage device and memory control circuit unit Download PDF

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Publication number
CN115547388A
CN115547388A CN202211273740.3A CN202211273740A CN115547388A CN 115547388 A CN115547388 A CN 115547388A CN 202211273740 A CN202211273740 A CN 202211273740A CN 115547388 A CN115547388 A CN 115547388A
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decoding
mode
memory
data
threshold
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曾士家
张议方
曹峻玮
许丞鞍
林纬
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair

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Abstract

The invention provides a decoding method, a memory storage device and a memory control circuit unit. The method comprises the following steps: starting a decoding circuit, which supports a plurality of decoding modes, wherein the decoding modes respectively correspond to a threshold value, and the distribution of the threshold value corresponds to the error correction capability of the decoding modes; reading first data from a rewritable nonvolatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value. Thus, decoding efficiency can be improved.

Description

Decoding method, memory storage device and memory control circuit unit
Technical Field
The invention relates to a decoding method, a memory storage device and a memory control circuit unit.
Background
The growth of mobile phones, tablet computers and notebook computers has been rapid over the years, resulting in a rapid increase in consumer demand for storage media. Since a rewritable non-volatile memory module (e.g., a flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices.
To ensure the correctness of the data, the data stored in the rewritable non-volatile memory module may be encoded. When data is read from the rewritable non-volatile memory module, the read data can be decoded to correct errors. However, it is one of the issues of the research efforts of those skilled in the related art to balance the error correction capability of the decoding circuit with the decoding speed.
Disclosure of Invention
The invention provides a decoding method, a memory storage device and a memory control circuit unit, which can improve the decoding efficiency.
An exemplary embodiment of the present invention provides a decoding method for a rewritable non-volatile memory module, the decoding method including: starting a decoding circuit, wherein the decoding circuit supports a plurality of decoding modes, each of the plurality of decoding modes corresponds to a threshold, and the distribution of the threshold corresponds to the error correction capability of the plurality of decoding modes; reading first data from the rewritable nonvolatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
In an exemplary embodiment of the present invention, the decoding parameter is related to a bit error rate of the first data.
In an exemplary embodiment of the present invention, the obtaining of the decoding parameter according to the execution result of the first decoding operation includes: obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and obtaining the decoding parameter according to the sum of the plurality of syndromes.
In an exemplary embodiment of the present invention, the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the threshold value comprises: comparing the decoding parameter with the critical value; and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
In an exemplary embodiment of the present invention, the first decoding mode corresponds to a first threshold, and the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the threshold comprises: performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode in response to the decoding parameter being less than the first critical value.
In an exemplary embodiment of the present invention, the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode includes: in response to the decoding parameter being greater than a second threshold corresponding to a second decoding mode of the plurality of decoding modes, the decoding circuit skips the second decoding mode and performs the second decoding operation on the first data based on the first decoding mode, wherein the second threshold is less than the first threshold, and an error correction capability of the second decoding mode is lower than an error correction capability of the first decoding operation.
In an exemplary embodiment of the present invention, the decoding method further includes: after the second decoding operation is performed on the first data based on the first decoding mode, a first critical value corresponding to the first decoding mode is adjusted according to an execution result of the second decoding operation.
In an exemplary embodiment of the present invention, the step of adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation includes: updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and adjusting the first critical value according to the decoding success rate.
An exemplary embodiment of the present invention further provides a memory storage device, which includes a connection interface unit, a rewritable nonvolatile memory module and a memory control circuit unit. The misconnection interface unit is used for connecting to a host system. The memory control circuit unit is connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit supports a plurality of decoding modes, the decoding modes respectively correspond to a threshold value, and the distribution of the threshold value corresponds to the error correction capability of the decoding modes. The memory control circuit unit is used for: sending a reading instruction sequence which indicates that first data is read from the rewritable nonvolatile memory module; performing a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
In an example embodiment of the present invention, the operation of the memory control circuit unit obtaining the decoding parameter according to the execution result of the first decoding operation includes: obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and obtaining the decoding parameter according to the sum of the plurality of syndromes.
In an exemplary embodiment of the present invention, the operation of the memory control circuit unit performing the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the threshold value comprises: comparing the decoding parameter with the critical value; and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
In an exemplary embodiment of the invention, the first decoding mode corresponds to a first threshold, and the operation of the memory control circuit unit performing the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative value relationship between the decoding parameter and the threshold comprises: performing the second decoding operation on the first data based on the first decoding mode in response to the decoding parameter being less than the first critical value.
In an example embodiment of the present invention, the operation of the memory control circuit unit performing the second decoding operation on the first data based on the first decoding mode includes: in response to the decoding parameter being greater than a second threshold corresponding to a second decoding mode of the plurality of decoding modes, skipping the second decoding mode and performing the second decoding operation on the first data based on the first decoding mode, wherein the second threshold is less than the first threshold, and an error correction capability of the second decoding mode is lower than an error correction capability of the first decoding operation.
In an exemplary embodiment of the invention, the memory control circuit unit is further configured to: after the second decoding operation is performed on the first data based on the first decoding mode, a first critical value corresponding to the first decoding mode is adjusted according to an execution result of the second decoding operation.
In an exemplary embodiment of the invention, the operation of the memory control circuit unit adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation includes: updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and adjusting the first critical value according to the decoding success rate.
An exemplary embodiment of the present invention further provides a memory control circuit unit for controlling a rewritable nonvolatile memory module. The memory control circuit unit comprises a host interface, a memory interface, a decoding circuit and a memory management circuit. The host interface is used for connecting to a host system. The memory interface is used for connecting to the rewritable nonvolatile memory module. The memory management circuit is coupled to the host interface, the memory interface, and the decoding circuit. The decoding circuit supports a plurality of decoding modes, each of the plurality of decoding modes corresponds to a threshold, and the distribution of the threshold corresponds to error correction capability of the plurality of decoding modes. The memory management circuitry to: sending a reading instruction sequence which indicates that first data is read from the rewritable nonvolatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and instructing the decoding circuit to perform a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
In an exemplary embodiment of the present invention, the operation of the memory management circuit obtaining the decoding parameter according to the execution result of the first decoding operation includes: obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and obtaining the decoding parameter according to the sum of the plurality of syndromes.
In an example embodiment of the present invention, the operation of the memory management circuit instructing the decoding circuit to perform the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the threshold value includes: comparing the decoding parameter with the critical value; and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
In an exemplary embodiment of the present invention, the first decoding mode corresponds to a first threshold, and the operation of the memory management circuit instructing the decoding circuit to perform the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative value relationship between the decoding parameter and the threshold comprises: in response to the decoding parameter being less than the first critical value, instruct the decoding circuitry to perform the second decoding operation on the first data based on the first decoding mode.
In an example embodiment of the present invention, the operation of the memory management circuit instructing the decoding circuit to perform the second decoding operation on the first data based on the first decoding mode includes: in response to the decoding parameter being greater than a second threshold corresponding to a second decoding mode of the plurality of decoding modes, skipping the second decoding mode and instructing the decoding circuit to perform the second decoding operation on the first data based on the first decoding mode, wherein the second threshold is less than the first threshold, and an error correction capability of the second decoding mode is lower than an error correction capability of the first decoding operation.
In an exemplary embodiment of the invention, the memory management circuit is further configured to: after the decoding circuit performs the second decoding operation on the first data based on the first decoding mode, the decoding circuit adjusts a first critical value corresponding to the first decoding mode according to a result of the second decoding operation.
In an exemplary embodiment of the invention, the operation of the memory management circuit adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation includes: updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and adjusting the first critical value according to the decoding success rate.
Based on the above, the decoding circuit, the memory control circuit unit and/or the memory storage device according to the exemplary embodiments of the invention can support multiple decoding modes. The decoding modes respectively correspond to a threshold, and the distribution of the threshold corresponds to the error correction capability of the decoding modes. After reading the first data from the rewritable non-volatile memory module, the first data can be subjected to a first decoding operation. Depending on the result of the execution of the first decoding operation, one decoding parameter may be obtained. Then, according to a relative numerical relationship between the decoding parameter and the threshold, the first data may be subjected to a second decoding operation based on a first decoding mode of the plurality of decoding modes. By dynamically determining the second decoding operation, the error correction capability and decoding speed of the decoding circuit, the memory control circuit unit and/or the memory storage device can be balanced, and the decoding efficiency can be improved.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to an exemplary embodiment of the present invention;
FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention;
FIG. 5 is a schematic diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic diagram of a parity check matrix according to an exemplary embodiment of the present invention;
FIG. 7 is a graph illustrating a threshold voltage distribution of memory cells according to an exemplary embodiment of the present invention;
FIG. 8 is a schematic diagram of a bipartite graph according to an exemplary embodiment of the invention;
FIG. 9 is a diagram illustrating a parity check operation according to an exemplary embodiment of the present invention;
FIG. 10 is a diagram illustrating reading soft bit information according to an exemplary embodiment of the present invention;
FIG. 11 is a diagram illustrating reading soft bit information according to an exemplary embodiment of the present invention;
FIG. 12 is a diagram illustrating different decoding modes corresponding to different threshold values according to an exemplary embodiment of the present invention;
fig. 13 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention;
fig. 14 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention.
Detailed Description
Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). The memory storage device may be used with a host system so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to an example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 may include a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be connected to a system bus (system bus) 110.
In an example embodiment, host system 11 may be connected to memory storage device 10 through data transfer interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 through data transfer interface 114. In addition, the host system 11 may be connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 over the system bus 110.
In an exemplary embodiment, the processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transmission interfaces 114 may be one or more. The motherboard 20 may be connected to the memory storage device 10 via the data transmission interface 114 by wire or wirelessly.
In an example embodiment, the memory storage device 10 may be, for example, a usb disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, near Field Communication (NFC) memory storage, wireless facsimile (WiFi) memory storage, bluetooth (Bluetooth) memory storage, or Bluetooth low energy memory storage (e.g., iBeacon) based memory storage based on various wireless Communication technologies. In addition, the motherboard 20 may also be connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, and a speaker 210 via the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an example embodiment, the host system 11 is a computer system. In an example embodiment, host system 11 may be any system that may substantially cooperate with a memory storage device to store data. In an example embodiment, the memory storage device 10 and the host system 11 may include the memory storage device 30 and the host system 31 of fig. 3, respectively.
FIG. 3 is a diagram illustrating a host system and a memory storage device according to an example embodiment of the invention.
Referring to FIG. 3, the memory storage device 30 can be used with a host system 31 to store data. For example, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer. For example, the memory storage device 30 may be a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34 used by the host system 31. The embedded memory device 34 includes embedded Multi Media Card (eMMC) 341 and/or embedded Multi Chip Package (eMCP) memory device 342, which connect the memory module directly to the substrate of the host system.
FIG. 4 is a schematic diagram of a memory storage device according to an example embodiment of the invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 41, a memory control circuit unit 42, and a rewritable nonvolatile memory module 43.
The connection interface unit 41 is used to connect the memory storage device 10 to the host system 11. The memory storage device 10 may communicate with the host system 11 through the connection interface unit 41. In an exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect local bus (PCI Express) standard. In an exemplary embodiment, the connection interface unit 41 may also be compliant with Serial Advanced Technology Attachment (SATA) standard, parallel Advanced Technology Attachment (PATA) standard, institute of Electrical and Electronic Engineers (IEEE) 1394 standard, universal Serial Bus (USB) standard, SD interface standard, ultra High Speed-I (UHS-I) interface standard, ultra High Speed-II (UHS-II) interface standard, memory Stick (Memory Stick, MS) interface standard, MCP interface standard, MMC interface standard, eMMC interface standard, flash Memory (UFS) interface standard, eMCP standard, CF interface standard, integrated Drive Electronics (IDE) standard, or other standards suitable for all types of Electronic devices. The connection interface unit 41 may be packaged with the memory control circuit unit 42 in a chip, or the connection interface unit 41 is disposed outside a chip including the memory control circuit unit 42.
The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable nonvolatile memory module 43. The memory control circuit unit 42 is used for executing a plurality of logic gates or control commands implemented in hardware or firmware and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 43 according to commands from the host system 11.
The rewritable nonvolatile memory module 43 is used for storing data written by the host system 11. The rewritable nonvolatile memory module 43 may include a Single Level Cell (SLC) NAND-type flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a second Level Cell (MLC) NAND-type flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Triple Level Cell (TLC) NAND-type flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), a Quad Level Cell (QLC) NAND-type flash memory module (i.e., a flash memory module that can store 4 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 43 stores one or more bits by a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. Each memory cell in the rewritable non-volatile memory module 43 has a plurality of memory states as the threshold voltage changes. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In an exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 43 may constitute a plurality of physical programming cells, and the physical programming cells may constitute a plurality of physical erasing cells. Specifically, memory cells on the same word line may constitute one or more physical programming cells. If a memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In an example embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page (page) or a physical fan (sector). If the physical programming units are physical pages, the physical programming units may include a data bit region and a redundancy (redundancy) bit region. The data bit area includes a plurality of physical sectors for storing user data, and the redundant bit area stores system data (e.g., management data such as error correction codes). In an exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, a physically erased cell is the smallest unit of erase. That is, each physically erased cell contains the smallest number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a diagram illustrating a memory control circuit unit according to an exemplary embodiment of the invention.
Referring to fig. 5, the memory control circuit unit 42 includes a memory management circuit 51, a host interface 52 and a memory interface 53. The memory management circuit 51 is used to control the overall operation of the memory control circuit unit 42. Specifically, the memory management circuit 51 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 51 is explained below, it is equivalent to the operation of the memory control circuit unit 42.
In an exemplary embodiment, the control instructions of the memory management circuit 51 are implemented in firmware. For example, the memory management circuit 51 has a microprocessor unit (not shown) and a read only memory (not shown), and the control commands are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In an exemplary embodiment, the control instructions of the memory management circuit 51 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 43 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 51 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit unit 42 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 43 into the RAM of the memory management circuit 51. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In an exemplary embodiment, the control instructions of the memory management circuit 51 may also be implemented in a hardware form. For example, the memory management circuit 51 includes a microcontroller, a memory cell management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are connected to the microcontroller. The cell management circuit is used to manage the cells or cell groups of the rewritable nonvolatile memory module 43. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 43 to write data into the rewritable nonvolatile memory module 43. The memory reading circuit is used for issuing a reading instruction sequence to the rewritable nonvolatile memory module 43 to read data from the rewritable nonvolatile memory module 43. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 43 so as to erase data from the rewritable nonvolatile memory module 43. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 43 and data read from the rewritable nonvolatile memory module 43. The write command sequence, the read command sequence and the erase command sequence may respectively include one or more program codes or command codes and instruct the rewritable nonvolatile memory module 43 to perform corresponding write, read and erase operations. In an exemplary embodiment, the memory management circuit 51 may issue other types of command sequences to the rewritable nonvolatile memory module 43 to instruct the corresponding operations to be performed.
The host interface 52 is connected to the memory management circuit 51. The memory management circuit 51 may communicate with the host system 11 through a host interface 52. The host interface 52 is used for receiving and recognizing commands and data transmitted by the host system 11. For example, commands and data transmitted by the host system 11 may be transmitted to the memory management circuit 51 through the host interface 52. In addition, the memory management circuit 51 may transmit data to the host system 11 through the host interface 52. In the exemplary embodiment, host interface 52 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 52 may be compatible with the SATA standard, PATA standard, IEEE 1394 standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standard.
The memory interface 53 is connected to the memory management circuit 51 and is used for accessing the rewritable nonvolatile memory module 43. For example, the memory management circuit 51 can access the rewritable nonvolatile memory module 43 through the memory interface 53. That is, the data to be written into the rewritable nonvolatile memory module 43 is converted into a format accepted by the rewritable nonvolatile memory module 43 through the memory interface 53. Specifically, if the memory management circuit 51 wants to access the rewritable nonvolatile memory module 43, the memory interface 53 transmits a corresponding command sequence. For example, the command sequences may include a write command sequence for indicating data to be written, a read command sequence for indicating data to be read, an erase command sequence for indicating data to be erased, and corresponding command sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). These instruction sequences are generated by the memory management circuit 51 and are transmitted to the rewritable non-volatile memory module 43 via the memory interface 53, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes information such as the identification code and the memory address of the read command.
In an exemplary embodiment, the memory control circuitry unit 42 further includes error checking and correction circuitry 54, buffer memory 55, and power management circuitry 56.
The error checking and correcting circuit 54 is connected to the memory management circuit 51 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 51 receives a write command from the host system 11, the error checking and correcting circuit 54 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 51 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 43. Then, when the memory management circuit 51 reads data from the rewritable nonvolatile memory module 43, the error correction code and/or the error check code corresponding to the data are/is read at the same time, and the error checking and correcting circuit 54 performs the error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 55 is connected to the memory management circuit 51 and is used for temporarily storing data. The power management circuit 56 is a power supply connected to the memory management circuit 51 and used to control the memory storage device 10.
In an example embodiment, the rewritable nonvolatile memory module 43 of fig. 4 may include a flash memory module. In an example embodiment, the memory control circuit unit 42 of FIG. 4 may include a flash memory controller. In an example embodiment, the memory management circuit 51 of FIG. 5 may include a flash memory management circuit.
In an exemplary embodiment, the ECC circuit 54 supports low-density parity-check (LDPC) codes. For example, the error checking and correcting circuit 54 may encode and decode using low density parity check codes. However, in another exemplary embodiment, the error checking and correcting circuit 54 may also support a BCH code, a convolutional code (convolutional code), a turbo code (turbo code), etc., and the invention is not limited thereto.
In low density parity check codes, a parity check matrix is used to define valid code words. The parity check matrix is hereinafter labeled matrix H and the codeword CW. If the multiplication of the matrix H and the codeword CW is a zero vector, it indicates that the codeword CW is a valid codeword, according to the following procedure (1). In equation sequence (1), operators
Figure BDA0003896197420000081
Representing matrix multiplication modulo 2 (mod 2). In other words, the null space (null space) of the matrix H contains all valid codewords. However, the invention does not limit the content of the code words CW. For example, the code word CW may also include an error correction code or an error check code generated by any algorithm.
Figure BDA0003896197420000082
In equation sequence (1), the dimension of matrix H is k-times-n (k-by-n) and the dimension of codeword CW is 1-times-n. k and n are positive integers. The code word CW includes information bits and parity bits. For example, codeword CW can be represented as [ M P ], where vector M is composed of information bits and vector P is composed of parity bits. The dimension of vector M is 1-times- (n-k) and the dimension of vector P is 1-times-k. The information bits and parity bits are collectively referred to as data bits hereinafter. In other words, there are n data bits in the codeword CW. In the codeword CW, the information bits are (n-k) bits in length, the parity bits are k bits in length, and the code rate of the codeword CW is (n-k)/n.
In general, a generation matrix (hereinafter denoted as G) is used in encoding, so that the following procedure (2) can be satisfied for an arbitrary vector M. For example, the dimension for generating matrix G is (n-k) -times-n.
Figure BDA0003896197420000091
The code word CW produced by equation (2) is a valid code word. The equation (2) can therefore be substituted into the equation (1), resulting in the following equation (3).
Figure BDA0003896197420000092
Since the vector M may be an arbitrary vector, the following procedure (4) is necessarily satisfied. That is, after determining the matrix H (i.e., parity check matrix), the corresponding generation matrix G may also be determined.
Figure BDA0003896197420000093
In decoding a codeword CW, a parity check operation is first performed on the data bits in the codeword CW, for example, by multiplying the matrix H with the codeword CW to generate a vector (hereinafter denoted as S, as shown in the following procedure (5)). Vector S is also referred to as a syndrome vector. If the vector S is a zero vector, the codeword CW can be directly output. If the vector S is not a zero vector, it indicates that the codeword CW is not a valid codeword.
Figure BDA0003896197420000094
The dimension of the vector S is k-times-1. Each element in the vector S is also referred to as a syndrome. If the codeword CW is not a valid codeword, the ECC circuit 54 may attempt to correct errors (i.e., erroneous bits) in the codeword CW by a decoding operation.
Fig. 6 is a diagram illustrating a parity check matrix according to an exemplary embodiment of the present invention.
Referring to FIG. 6, the parity check matrix 600 has dimensions of k-times-n. For example, k is 8 and n is 9. However, the present invention does not limit the values of the positive integers k and n. Each column (row) of parity-check matrix 600 may represent a constraint. Taking the first column of the parity check matrix 600 as an example, if a codeword is a valid codeword, the bits "0" will be obtained after modulo-2 (mod 2) addition of the 3 rd, 5 th, 8 th and 9 th bits in the codeword. Those skilled in the art will understand how to encode and decode the parity check matrix 600, and will not be described herein. In addition, the parity check matrix 600 is only an exemplary matrix and is not intended to limit the present invention.
When the memory management circuit 51 is to store data (including a plurality of bits) into the rewritable nonvolatile memory module 43, the error checking and correcting circuit 54 may generate k parity bits for every (n-k) bits (i.e., message bits) in the data. Next, the memory management circuit 51 can write the n bits (i.e. data bits) as a codeword into the rewritable non-volatile memory module 43.
FIG. 7 is a graph illustrating threshold voltage distributions of memory cells according to an exemplary embodiment of the present invention.
Referring to fig. 7, the horizontal axis represents the threshold voltage of the memory cells, and the vertical axis represents the number of the memory cells. For example, fig. 7 may represent the threshold voltage of each memory cell in one physical cell (also referred to as a first physical cell). For example, the first physical unit may include one or more physical programming units.
Assuming that state 710 corresponds to a bit "1" and state 720 corresponds to a bit "0", then a memory cell stores a bit "1" when its threshold voltage falls within state 710; conversely, if the threshold voltage of a memory cell belongs to state 720, the memory cell stores a bit "0". It is noted that, in the exemplary embodiment, one state in the threshold voltage distribution corresponds to one bit value, and the threshold voltage distribution of the memory cell has two possible states. However, in other exemplary embodiments, each state in the threshold voltage distribution may correspond to a plurality of bit values and the distribution of the threshold voltages of the memory cells may have four, eight or any other states. In addition, the present invention does not limit the bits represented by each state. For example, in another exemplary embodiment of fig. 7, state 710 may also correspond to a bit "0" and state 720 corresponds to a bit "1".
When data is to be read from the rewritable non-volatile memory module 43, the memory management circuit 202 can send a read command sequence to the rewritable non-volatile memory module 43. The read command sequence is used to instruct the rewritable non-volatile memory module 43 to read at least one memory cell (also referred to as a first memory cell) in the first physical unit using at least one read voltage level to obtain the data stored in the first memory cell. For example, according to the read command sequence, the rewritable nonvolatile memory module 43 can read the first memory cell by using the read voltage level 701 in FIG. 7. If the threshold voltage of one of the first memory cells is less than the read voltage level 701, the memory cell can be turned on and the memory management circuit 51 can read the bit "1". Alternatively, if the threshold voltage of one of the first memory cells is greater than the read voltage level 701, the memory cell may not be turned on and the memory management circuit 51 may read the bit "0". The read bit data may constitute one or more codewords.
In an exemplary embodiment, the states 710 and 720 include an overlap region 730 (marked by diagonal lines in FIG. 7). The overlap region 730 indicates that some of the first memory cells should store a bit "1" (which belongs to state 710) but have a threshold voltage greater than the applied read voltage level 701; also, some of the first memory cells should store a bit "0" (which belongs to state 720), but have a threshold voltage less than the applied read voltage level 701. In other words, some bits of the data read by applying the read voltage level 701 may have errors.
Generally, if the first memory cell has a short lifetime (e.g., the first memory cell has a short data retention time) and/or the first memory cell has a low lifetime (e.g., the first memory cell has a low read count, write count, and/or erase count), the area of the overlap region 730 is usually small, and even the overlap region 730 may not exist (i.e., the states 710 and 720 do not overlap). Alternatively, if the memory storage device 10 is shipped from the factory, the overlap region 730 does not normally exist. If the area of the overlap region 730 is small, there are often fewer erroneous bits in the data read from the first memory cell by applying the read voltage level 701.
However, as the usage time and/or the usage frequency of the rewritable nonvolatile memory module 43 increases, the area of the overlap region 730 may gradually increase. For example, if the first memory cell has a long lifetime (e.g., data is stored in the first memory cell for a long time) and/or the first memory cell has a high lifetime (e.g., the first memory cell has a high read count, write count, and/or erase count), the area of the overlap region 730 may become larger (e.g., the states 710 and 720 may change to flat and/or the states 710 and 720 may be closer to each other). If the area of the overlap region 730 is large, there may be more erroneous bits in the data read from the first memory cell by applying the read voltage level 701. Thus, upon receiving the read data from the rewritable non-volatile memory module 43, the error checking and correcting circuit 54 may perform a parity checking operation in a decoding operation to verify whether an error exists in the data. If it is determined that there is an error in the data, the error checking and correcting circuit 54 may correct the error in the data through the decoding operation.
In an exemplary embodiment, the error checking and correcting circuit 54 may perform an iterative (iteration) decoding operation. An iterative decoding operation may be used to decode a datum from the rewritable nonvolatile memory module 43. For example, one decoding unit in data may be one codeword. In an iterative decoding operation, a parity checking operation for checking the correctness of data and a decoding operation for correcting errors in the data may be repeated and alternately performed until a successful decoding or the number of iterations reaches a predetermined number. If the iteration count reaches the predetermined number, the error checking and correcting circuit 54 determines that the decoding has failed. Further, if it is determined by the parity check operation that there is no error in a certain data, the error check and correction circuit 54 may determine that the decoding is successful and output the successfully decoded data.
Fig. 8 is a schematic diagram of a bipartite graph according to an exemplary embodiment of the invention.
Referring to FIG. 8, in general, parity check matrix H may be represented as bipartite graph 830 including parity nodes 832 (1) -832 (k) and message nodes 834 (1) -834 (n). Each parity node 832 (1) -832 (k) corresponds to a syndrome, and each message node 834 (1) -834 (n) corresponds to a data bit. The correspondence between the data bits and the syndromes (i.e., the connections between the message nodes 834 (1) -834 (n) and the parity nodes 832 (1) -832 (k)) is generated according to the matrix H. Specifically, if the element in the ith column (row) and jth row (column) in the matrix H is 1, the ith parity node 832 (i) is connected to the jth message node 834 (j), where i and j are positive integers.
When the memory management circuit 51 reads n data bits (forming one codeword) from the rewritable non-volatile memory module 43, the memory management circuit 51 also obtains reliability information (also referred to as channel reliability information) of each data bit. The reliability information is used to indicate the probability (or confidence) that the corresponding data bit is decoded to bit "1" or "0". In bipartite graph 830, message nodes 834 (1) -834 (n) also receive corresponding reliability information. For example, the message node 834 (1) receives the reliability information L of the 1 st data bit 1 The message node 834 (j) receives the reliability information L of the jth data bit j 。
The error checking and correcting circuit 54 can be based on the structure and reliability information L of the bipartite graph 830 1 ～L n To perform a decoding operation. For example, this decoding operation may include iterative decoding. In iterative decoding, the message nodes 834 (1) -834 (n) calculate reliability information to parity nodes 832 (1) -832 (k), and the parity nodes 832 (1) -832 (k) also calculate reliability information to the message nodes 834 (1) -834 (n). The reliability information is transmitted along an edge (edge) in the bipartite graph 830. For example, parity node 832 (i) sends reliability information L to message node 834 (j) i→j The message node 834 (j) sends to the parity node 832 (i) reliability information L j→i . The reliability information is used to represent a sectionA point considers the probability (i.e., confidence) that a certain data bit is decoded as "1" or "0". E.g. reliability information L j→i The confidence level (which may be positive or negative) that the message node 834 (j) considers the jth data bit to be decoded as "1" or "0", and the reliability information L i→j Indicating the degree of confidence that parity node 832 (i) considers the ith data bit to be decoded as either a "1" or a "0". In addition, the message nodes 834 (1) -834 (n) and parity nodes 832 (1) -832 (k) may calculate the output reliability information according to the input reliability information, which is similar to the conditional probability of decoding a data bit to be "1" or "0". Therefore, the above procedure of transmitting reliability information is also called belief propagation (belief propagation).
After performing a parity check operation on the calculated data bits (e.g., multiplying the codeword formed by the data bits by a parity check matrix), it can be determined whether the codeword is a valid codeword. If the generated code word is a valid code word, the decoding is successful. However, if the generated codeword is not a valid codeword, the next iteration can be performed. If the iteration times of the iterative decoding reaches a preset value, the decoding is failed.
In an example embodiment, the reliability information includes a Log Likelihood Ratio (LLR). For example, reliability information L in fig. 8 1 ～L n 、L i→j And L j→i Respectively, may be a log likelihood ratio. Generally, the greater the absolute value of the log likelihood ratio (which may be positive or negative) for a data bit, the greater the reliability of the data bit, and thus the higher the probability that the current bit value of the data bit is considered correct. Conversely, the smaller the absolute value of the log-likelihood ratio corresponding to a data bit, the lower the reliability of the data bit, and thus the higher the probability that the current bit value of the data bit is considered to be erroneous and can be corrected in the current iterative decoding. In an exemplary embodiment, the reliability information (e.g., log likelihood ratio) used in iterative decoding is obtained by a table lookup. However, inIn another exemplary embodiment, the reliability information used in iterative decoding can also be dynamically calculated in iterative decoding according to a specific algorithm. In addition, the message nodes 834 (1) -834 (n) and/or parity nodes 832 (1) -832 (k) may also calculate different types of reliability information based on different algorithms, not limited to log likelihood ratios.
Fig. 9 is a diagram illustrating a parity checking operation according to an exemplary embodiment of the present invention.
Referring to FIG. 9, assuming that the data read from the first memory cell includes a codeword 901, in the parity check operation, the matrix 900 (i.e., parity check matrix) may be multiplied by the codeword 901 to generate a vector 902 (i.e., vector S) according to the square procedure (5). Vector 902 is also referred to as a check vector.
Each bit in codeword 901 corresponds to at least one element (i.e., a syndrome) in vector 902. For example, bit V in codeword 901 0 (corresponding to the first row in parity-check matrix 900) is a parity check matrix corresponding to a syndrome S 1 、S 4 And S 7 (ii) a Bit V 1 (corresponding to the second row in parity-check matrix 900) is a parity check matrix corresponding to S 2 、S 3 And S 6 (ii) a By analogy, bit V 8 (corresponding to the ninth row in parity-check matrix 900) is a parity check matrix corresponding to syndrome S 0 、S 4 And S 5 . If bit V 0 If it is an error bit, syndrome S is checked 1 、S 4 And S 7 May be a "1". If bit V 1 If it is an error bit, syndrome S is checked 2 、S 3 And S 6 May be a "1". By analogy, if bit V 8 If it is an error bit, syndrome S is checked 0 、S 4 And S 5 May be a "1".
In other words, if the syndrome S 0 ～S 7 Are all "0" s, indicating that there may be no error bits in codeword 901, so error checking and correction circuit 54 can directly output codeword 901. However, if there is at least one erroneous bit in codeword 901, syndrome S is checked 0 ～S 7 May be a "1" and the error checking and correction circuit 54 may correct the error by performing a decoding operation on the codeword 901.
In an exemplary embodiment, the memory management circuit 51 may activate the circuit responsible for performing the decoding operation (also referred to as the decoding circuit) of the error checking and correcting circuit 54. In particular, the decoding circuit can support a plurality of decoding modes, and the error correction capabilities of the plurality of decoding modes are different.
In an exemplary embodiment, the memory management circuit 51 can send a read command sequence (also referred to as a first read command sequence) to the rewritable nonvolatile memory module 43. The first read command sequence can instruct the rewritable non-volatile memory module 43 to read the target data (also referred to as the first data) from the first physical unit using a certain read voltage level (also referred to as the first read voltage level). For example, the first read voltage level can include the read voltage level 701 of FIG. 7. According to the first read command sequence, the rewritable nonvolatile memory module 43 can use the first read voltage level to read the first data from the first physical unit and transmit the read first data back to the memory management circuit 51.
After receiving the first data returned by the rewritable nonvolatile memory module 43, the memory management circuit 51 may instruct the decoding circuit to perform a decoding operation (also referred to as a first decoding operation) on the first data. For example, the memory management circuit 51 may instruct the decoding circuit to perform a first decoding operation based on a certain decoding mode (also referred to as a default decoding mode) to attempt to correct errors in the first data.
In an example embodiment, the first decoding operation performed based on the preset decoding mode may include hard bit mode decoding. For example, in hard bit mode decoding, the decoding circuit may employ a bit flipping (bit flipping) algorithm, a minimum sum (min-sum) algorithm, and/or a sum-product (sum-product) algorithm to decode the first data in an attempt to correct errors in the first data. Those skilled in the art should know how to decode data using LDPC decoding algorithms such as bit flipping algorithm, minimum sum-product algorithm and/or sum-product algorithm, and so on, and will not be described herein.
If the errors in the first data are all corrected, memory management circuit 51 may determine that the decoding was successful and output the successfully decoded data. However, if the partial error in the first data cannot be corrected, the memory management circuit 51 may adjust a reading voltage level (i.e., a first reading voltage level) for reading the first physical unit and send a reading command sequence to the rewritable non-volatile memory module 43 according to the adjusted reading voltage level, so as to instruct the rewritable non-volatile memory module 43 to read the first physical unit again by using the adjusted reading voltage level to obtain the first data again. Then, the memory management circuit 51 may again instruct the decoding circuit to perform the first decoding operation based on the preset decoding mode to attempt to correct the error in the first data.
In an exemplary embodiment, the memory management circuit 51 may determine whether the number of times of performing the first decoding operation reaches a predetermined value. If the number of times of performing the first decoding operation does not reach the predetermined value, the memory management circuit 51 may allow the decoding circuit to continue decoding the first data based on the predetermined decoding mode. However, if the number of times of performing the first decoding operation has reached the predetermined value, the memory management circuit 51 may instruct the decoding circuit to attempt to decode the data (i.e., the first data) read from the first physical unit based on another decoding mode (also referred to as a first decoding mode). It should be noted that the first decoding mode is different from the preset decoding mode. For example, the error correction capability of the first decoding mode is higher than that of the default decoding mode.
In an exemplary embodiment, before entering the first decoding mode, the memory management circuit 51 may further perform an optimal read voltage level search operation to attempt to optimally adjust a read voltage level (e.g., the read voltage level 701 of fig. 7) for reading the first physical unit. Those skilled in the art should know how to perform the optimum reading voltage level searching operation to adjust the reading voltage level, and the description thereof is omitted here.
In an example embodiment, after entering the first decoding mode, the memory management circuit 51 may send a read command sequence (also referred to as a second read command sequence) to the rewritable nonvolatile memory module 43. The second read command sequence may instruct the rewritable non-volatile memory module 43 to read the target data (i.e., the first data) and the auxiliary data (i.e., the soft-bit information) from the first physical unit using a plurality of read voltage levels (also referred to as second read voltage levels). The soft bit information may be used to assist in decoding the first data to increase a decoding success rate for the first data.
Fig. 10 is a diagram illustrating reading soft bit information according to an exemplary embodiment of the present invention.
Referring to FIG. 10, in an exemplary embodiment, the second read voltage levels include read voltage levels V (1) -V (3). According to the second read command sequence, the rewritable nonvolatile memory module 43 can sequentially read the first physical units by using the read voltage levels V (1) -V (3) to obtain the first data and the soft bit information 1030 corresponding to the first data. For example, one of the read voltage levels V (1) -V (3) (e.g., the read voltage level V (1)) can be used to read the first data, and the read voltage levels V (1) -V (3) can be commonly used to obtain the soft bit information 1030.
In an exemplary embodiment, the read voltage levels V (1) -V (3) are divided into voltage intervals 1001-1004, as shown in FIG. 10. Assuming that the threshold voltage distributions of the memory cells in the first physical cell include states 1010 and 1020, the soft bit information 1030 may reflect that the voltage interval in which the threshold voltages of the memory cells in the first physical cell are located is one of the voltage intervals 1001-1004. For example, suppose that the soft bit information 1030 read from a memory cell using the read voltage levels V (1) -V (3) is "011", indicating that the threshold voltage of the memory cell is in the voltage interval 1002, and so on.
Fig. 11 is a diagram illustrating reading soft bit information according to an exemplary embodiment of the present invention.
Referring to FIG. 11, in an exemplary embodiment, the second read voltage levels include read voltage levels V (1) -V (5). It should be noted that the total number (i.e. 5) of the read voltage levels V (1) -V (5) in fig. 11 is greater than the total number (i.e. 3) of the read voltage levels V (1) -V (3) in fig. 10. According to the second read command sequence, the rewritable nonvolatile memory module 43 can sequentially read the first physical units using the read voltage levels V (1) -V (5) to obtain the first data and the soft bit information 1130 corresponding to the first data. For example, one of the read voltage levels V (1) -V (5) (e.g., the read voltage level V (1)) may be used to read the first data, and the read voltage levels V (1) -V (5) may be commonly used to obtain the soft bit information 1130.
In an exemplary embodiment, the read voltage levels V (1) -V (5) are divided into voltage intervals 1101-1106, as shown in FIG. 11. Assuming that the threshold voltage distribution of the memory cells in the first physical cell includes states 1110 and 1120, the soft bit information 1130 may reflect that the voltage interval in which the threshold voltage of each memory cell in the first physical cell is located is one of the voltage intervals 1101-1106. For example, it is assumed that the soft bit information 1130 read from a certain memory cell using the read voltage levels V (1) to V (5) is "00111", which indicates that the threshold voltage of the memory cell is located in the voltage interval 1103, and so on.
It should be noted that, in general, with reference to fig. 10 and 11, a decoding success rate for decoding the first data using the soft bit information 1130 of fig. 11 may be higher than a decoding success rate for decoding the first data using the soft bit information 1030 of fig. 10. In addition, more read voltage levels can be used to read the first physical unit to increase the resolution of the divided voltage intervals (e.g., increase the total number of the voltage intervals 1101-1106), thereby further improving the subsequent decoding success rate.
After receiving the first data and the soft bit information returned by the rewritable nonvolatile memory module 43, the memory management circuit 51 may instruct the decoding circuit to perform a decoding operation (also referred to as a second decoding operation) on the first data. For example, memory management circuitry 51 may instruct decoding circuitry to perform a second decoding operation based on a first decoding mode.
In an example embodiment, the second decoding operation performed based on the first decoding mode may include soft bit mode decoding. For example, in soft bit mode decoding, the decoding circuit may also employ a bit flipping algorithm, a minimum sum-product algorithm, and/or a sum-product algorithm to decode the first data in an attempt to correct errors in the first data. It should be noted that in soft bit mode decoding, the memory management circuit 51 may update the reliability information (e.g., log likelihood ratio) according to the soft bit information (e.g., the soft bit information 1030 in fig. 10 or the soft bit information 1130 in fig. 11). Then, the decoding circuit may decode the first data according to the updated reliability information. A person skilled in the art should know how to update the reliability information (e.g., log likelihood ratio) according to the soft bit information, and the description thereof is omitted here. In particular, compared with the method that the first data is decoded by using the fixed or preset reliability information in the hard bit decoding mode, the method that the first data is decoded by using the dynamically updated reliability information in the soft bit decoding mode can effectively improve the decoding success rate of the first data. However, it takes a longer time to perform a decoding operation based on the soft bit decoding mode than the hard bit decoding mode.
Fig. 12 is a diagram illustrating different decoding modes corresponding to different thresholds according to an exemplary embodiment of the present invention.
Referring to fig. 12, it is assumed that the decoding modes that the decoding circuit can support include decoding modes (1) to (N). The memory management circuit 51 may be configured with threshold values TH (1) to TH (N) for the decoding mode (1) to the decoding mode (N), respectively. The decoding mode (i) corresponds to the threshold value TH (i). The memory management circuit 51 may record the correspondence or mapping relationship between the decoding modes (1) to (N) and the threshold values TH (1) to TH (N) in the table information 1201.
It should be noted that the distribution of the threshold values TH (1) -TH (N) (i.e., the distribution of the values of the threshold values TH (1) -TH (N)) may correspond to or reflect the error correction capability (i.e., decoding capability) of the decoding modes (1) -TH (N). Taking fig. 12 as an example, the threshold values TH (1) to TH (N) gradually increase, indicating that the decoding capabilities of the decoding modes (1) to (N) gradually increase. That is, in the decoding modes (1) to (N), the decoding capability of the decoding mode (p) is higher than that of the decoding mode (j), p is greater than j, and the threshold value TH (p) is greater than the threshold value TH (j).
Taking fig. 10 and 11 as an example, the second decoding operation performed based on the decoding mode (j) may include decoding the first data using the soft bit information 1030 of fig. 10, and the second decoding operation performed based on the decoding mode (p) may include decoding the first data using the soft bit information 1130 of fig. 11 to increase a decoding success rate. In addition, various technical means can be used to improve the decoding capability of the second decoding operation, such as further increasing the total number of the read voltage levels V (1) -V (5) in fig. 11 or instructing the rewritable nonvolatile memory module 43 to read data based on different reliability by customizing the command, and the invention is not limited thereto.
In an exemplary embodiment, the memory management circuit 51 may obtain a decoding parameter according to the execution result of the first decoding operation before the second decoding operation is executed. The decoding parameter is related to a bit error rate of the first data. For example, the value of the decoding parameter may be positively correlated to the bit error rate of the first data. That is, as the value of the decoding parameter is larger, the bit error rate representing the first data is higher.
In an example embodiment, the memory management circuit 51 may obtain the check vector (i.e., the vector S) according to the execution result of the first decoding operation. The check vector may include a plurality of syndromes. Memory management circuitry 51 may obtain the decoding parameters from a sum of the plurality of syndromes. For example, the sum of the plurality of syndromes may correspond to, reflect, or positively correlate to the bit error rate of the first data.
Taking fig. 9 as an example, in an exemplary embodiment, the memory management circuit 51 may send the read command sequence to the rewritable non-volatile memory module 43 after the first decoding operation fails and/or the optimal read voltage level searching operation is performed. The read command sequence can instruct the rewritable non-volatile memory module 43 to read at least one memory cell in the first physical unit using at least one read voltage level to obtain the codeword 901. The decoding circuitry may perform a parity check operation on codeword 901 to obtain vector 902. Memory management circuit 51 may calculate a sum of syndromes S0-S7 in vector 902 and obtain the decoding parameters based on the sum. For example, the values of the decoding parameters may be the same or positively correlated to the sum of the syndromes S0-S7.
After obtaining the decoding parameter, the memory management circuit 51 may instruct the decoding circuit to perform a second decoding operation on the first data based on a specific decoding mode (i.e., the first decoding mode) from the decoding modes (1) to (N) according to a relative numerical relationship between the decoding parameter and the threshold values TH (1) to TH (N). For example, the memory management circuit 51 may compare the decoding parameter with at least one of the threshold values TH (1) to TH (N). Then, the memory management circuit 51 may determine the first decoding mode from the decoding modes (1) to (N) based on the comparison result.
In an example embodiment, in response to the decoding parameter being smaller than the threshold TH (k) (also referred to as the first threshold), the memory management circuit 51 may instruct the decoding circuit to perform the second decoding operation on the first data based on the decoding mode (k) corresponding to the threshold TH (k) (i.e., the first decoding mode). In an exemplary embodiment, the decoding parameter is smaller than the threshold TH (k), which means that the second decoding operation performed based on the decoding mode (k) has a high probability of correcting all errors in the first data. Therefore, in the case where the decoding parameter is less than the critical value TH (k), the first data is decoded based on the decoding mode (k), which helps to improve the decoding success rate of the first data.
In an example embodiment, in response to the decoding parameter not being less than the threshold value TH(s) (also referred to as a second threshold value), the memory management circuit 51 may instruct the decoding circuit to skip (i.e., skip) the decoding mode(s) corresponding to the threshold value TH(s) (also referred to as a second decoding mode). Wherein skipping the decoding mode(s) means not performing the second decoding operation based on the decoding mode(s). For example, assume that the value of the decoding parameter is between threshold values TH(s) and TH (k), k is greater than s (e.g., k equals s + 1), and threshold value TH (k) is greater than threshold value TH(s). In this case, the memory management circuit 51 may skip the decoding mode(s) with relatively low error correction capability and directly instruct the decoding circuit to perform the second decoding operation based on the decoding mode (k) with relatively high error correction capability.
It should be noted that, in an exemplary embodiment, the decoding parameter is not less than the threshold TH(s), which means that the second decoding operation performed based on the decoding mode(s) has a high probability of not correcting all errors in the first data. Therefore, when the decoding parameter is not less than the threshold TH(s), the decoding mode(s) with lower decoding capability is directly skipped and the decoding mode (k) with higher decoding capability is used to decode the data, which also helps to improve the decoding efficiency of the first data.
In an exemplary embodiment, after performing the second decoding operation on the first data based on the decoding mode (k), if the second decoding operation is failed (i.e., the second decoding operation performed based on the decoding mode (k) cannot correct all errors in the first data), the memory management circuit 51 may instruct the decoding circuit to perform the second decoding operation again based on the decoding mode (k + 1) until the decoding mode is exhausted. In addition, if the second decoding operation performed on the first data based on the decoding mode (k) is successful (i.e., the second decoding operation performed based on the decoding mode (k) can correct all errors in the first data), the memory management circuit 51 may output the successfully decoded data.
In an example embodiment, after performing the second decoding operation on the first data based on the first decoding mode, the memory management circuit 51 may adjust the first threshold corresponding to the first decoding mode according to a result of the second decoding operation. For example, assume that the first decoding mode is decoding mode (k). After performing the second decoding operation on the first data based on the decoding mode (k), in response to the result of the second decoding operation being failed, the memory management circuit 51 may decrease the threshold value (k) corresponding to the decoding mode (k), for example, decrease the threshold value (k) from the first value to the second value. On the other hand, in response to the execution result of the second decoding operation being successful, the memory management circuit 51 may increase the threshold (k), for example, from the first value to the third value.
In an example embodiment, after performing the second decoding operation on the first data based on the first decoding mode, the memory management circuit 51 may update the decoding success rate corresponding to the first decoding mode according to the result of the performing of the second decoding operation. Then, the memory management circuit 51 may adjust the first threshold corresponding to the first decoding mode according to the updated decoding success rate. For example, assume that the first decoding mode is decoding mode (k). The memory management circuit 51 may determine whether the decoding success rate of the decoding mode (k) is lower than the success rate lower limit or higher than the success rate upper limit. In response to the decoding success rate of the decoding mode (k) being lower than the success rate lower limit, the memory management circuit 51 may decrease the threshold value (k), for example, from a first value to a second value. Alternatively, in response to the decoding success rate of the decoding mode (k) being higher than the success rate upper limit, the memory management circuit 51 may increase the threshold value (k), for example, from the first value to the third value. In an exemplary embodiment, the threshold corresponding to each decoding mode can be more suitable for the current device status by dynamically adjusting the threshold corresponding to at least one decoding mode.
Fig. 13 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention.
Referring to fig. 13, in step S1301, a decoding circuit is activated, wherein the decoding circuit supports a plurality of decoding modes, each of the plurality of decoding modes corresponds to a threshold, and a distribution of the threshold corresponds to error correction capabilities of the plurality of decoding modes. In step S1302, first data is read from the rewritable nonvolatile memory module. In step S1303, a first decoding operation is performed on the first data by the decoding circuit. In step S1304, decoding parameters are obtained according to the result of the execution of the first decoding operation. In step S1305, a second decoding operation is performed on the first data by the decoding circuit based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
Fig. 14 is a flowchart illustrating a decoding method according to an exemplary embodiment of the present invention.
Referring to fig. 14, in step S1401, data (i.e. first data) is read from the rewritable nonvolatile memory module. In step S1402, a first decoding operation is performed on the data by a decoding circuit based on a preset decoding mode. In step S1403, decoding parameters are obtained according to the execution result of the first decoding operation. In step S1404, it is determined whether the decoding parameter is smaller than a threshold value TH (1). If the decoding parameter is smaller than the threshold TH (1), in step S1405, a second decoding operation is performed on the data by the decoding circuit based on the decoding mode (1). If the decoding parameter is not less than the threshold TH (1), in step S1406, it is determined whether the decoding parameter is less than the threshold TH (2). If the decoding parameter is smaller than the threshold TH (2), in step S1407, a second decoding operation is performed on the data by the decoding circuit based on the decoding mode (2). By analogy, in step S1408, it is determined whether the decoding parameter is smaller than the threshold TH (N). If the decoding parameter is smaller than the threshold TH (N), in step S1409, a second decoding operation is performed on the data by the decoding circuit based on a decoding mode (N). In addition, if the decoding parameter is not less than the threshold TH (N), in step S1410, an error process is performed, for example, another decoding mode is activated to decode data or an error message is sent to the host system, and the invention is not limited thereto.
However, the steps in fig. 13 and fig. 14 have been described in detail above, and are not repeated herein. It is to be noted that the steps in fig. 13 and fig. 14 can be implemented as a plurality of program codes or circuits, which is not limited in this disclosure. In addition, the methods of fig. 13 and 14 may be used with the above exemplary embodiments, or may be used alone, which is not limited in this disclosure.
In summary, the exemplary embodiments of the present invention provide a method for dynamically determining a decoding mode to be used next from a plurality of decoding modes according to a relative numerical relationship between a decoding parameter and at least one threshold, so as to effectively improve decoding efficiency. In addition, the critical value corresponding to each decoding mode can be dynamically adjusted according to the decoding success rate of each decoding mode, so that the critical value corresponding to each decoding mode is more consistent with the current device state.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (24)

1. A decoding method for a rewritable non-volatile memory module, the decoding method comprising:
starting a decoding circuit, wherein the decoding circuit supports a plurality of decoding modes, each of the plurality of decoding modes corresponds to a threshold, and the distribution of the threshold corresponds to the error correction capability of the plurality of decoding modes;
reading first data from the rewritable nonvolatile memory module;
performing, by the decoding circuit, a first decoding operation on the first data;
obtaining a decoding parameter according to an execution result of the first decoding operation; and
performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
2. The decoding method of claim 1, wherein the decoding parameter relates to a bit error rate of the first data.
3. The decoding method according to claim 2, wherein the step of obtaining the decoding parameter according to the execution result of the first decoding operation comprises:
obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and
and obtaining the decoding parameters according to the sum of the plurality of syndromes.
4. The decoding method of claim 1, wherein the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the critical value comprises:
comparing the decoding parameter with the critical value; and
and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
5. The decoding method of claim 1, wherein the first decoding mode corresponds to a first threshold, and the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes according to the relative numerical relationship between the decoding parameter and the threshold comprises:
performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode in response to the decoding parameter being less than the first critical value.
6. The decoding method of claim 5, wherein the step of performing, by the decoding circuit, the second decoding operation on the first data based on the first decoding mode comprises:
skipping, by the decoding circuit, a second decoding mode of the plurality of decoding modes in response to the decoding parameter not being less than a second critical value corresponding to the second decoding mode and performing the second decoding operation on the first data based on the first decoding mode,
wherein the second threshold is smaller than the first threshold, and the error correction capability of the second decoding mode is lower than that of the first decoding operation.
7. The decoding method of claim 1, further comprising:
after the second decoding operation is performed on the first data based on the first decoding mode, a first critical value corresponding to the first decoding mode is adjusted according to an execution result of the second decoding operation.
8. The decoding method of claim 7, wherein the step of adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation comprises:
updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and
and adjusting the first critical value according to the decoding success rate.
9. A memory storage device, comprising:
a connection interface unit for connecting to a host system;
a rewritable non-volatile memory module; and
a memory control circuit unit connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit supports a plurality of decoding modes, the decoding modes respectively correspond to a threshold value, and the distribution of the threshold value corresponds to the error correction capability of the decoding modes,
the memory control circuit unit is used for:
sending a reading instruction sequence which indicates that first data is read from the rewritable nonvolatile memory module;
performing a first decoding operation on the first data;
obtaining a decoding parameter according to an execution result of the first decoding operation; and
and performing a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
10. The memory storage device of claim 9, wherein the decoding parameter relates to a bit error rate of the first data.
11. The memory storage device of claim 10, wherein the operation of the memory control circuitry unit to obtain the decoding parameter as a result of the performing of the first decoding operation comprises:
obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and
and obtaining the decoding parameter according to the sum of the plurality of syndromes.
12. The memory storage device of claim 9, wherein the operation of the memory control circuitry unit performing the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes in accordance with the relative numerical relationship between the decoding parameter and the critical value comprises:
comparing the decoding parameter with the critical value; and
and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
13. The memory storage device of claim 9, wherein the first decoding mode corresponds to a first threshold, and the memory control circuitry unit, according to the relative numerical relationship between the decoding parameter and the threshold, to perform the second decoding operation on the first data based on the first decoding mode of the plurality of decoding modes comprises:
performing the second decoding operation on the first data based on the first decoding mode in response to the decoding parameter being less than the first critical value.
14. The memory storage device of claim 13, wherein the operation of the memory control circuitry unit performing the second decoding operation on the first data based on the first decoding mode comprises:
in response to the decoding parameter not being less than a second threshold corresponding to a second decoding mode of the plurality of decoding modes, skipping the second decoding mode and performing the second decoding operation on the first data based on the first decoding mode,
wherein the second threshold is smaller than the first threshold, and the error correction capability of the second decoding mode is lower than that of the first decoding operation.
15. The memory storage device of claim 9, wherein the memory control circuitry unit is further configured to:
after the second decoding operation is performed on the first data based on the first decoding mode, a first critical value corresponding to the first decoding mode is adjusted according to an execution result of the second decoding operation.
16. The memory storage device of claim 15, wherein the operation of the memory control circuitry unit adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation comprises:
updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and
and adjusting the first critical value according to the decoding success rate.
17. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
a host interface for connecting to a host system;
a memory interface for connecting to the rewritable nonvolatile memory module;
a decoding circuit; and
memory management circuitry connected to the host interface, the memory interface, and the decoding circuitry,
wherein the decoding circuit supports a plurality of decoding modes, each of the plurality of decoding modes corresponds to a threshold, and the distribution of the threshold corresponds to the error correction capability of the plurality of decoding modes,
the memory management circuitry to:
sending a reading instruction sequence which indicates that first data is read from the rewritable nonvolatile memory module;
performing, by the decoding circuit, a first decoding operation on the first data;
obtaining a decoding parameter according to an execution result of the first decoding operation; and
instructing the decoding circuit to perform a second decoding operation on the first data based on a first decoding mode of the plurality of decoding modes according to a relative numerical relationship between the decoding parameter and the critical value.
18. The memory control circuitry unit of claim 17, wherein the decoding parameter relates to a bit error rate of the first data.
19. The memory control circuitry unit of claim 18, wherein the operation of the memory management circuitry to obtain the decoding parameter as a result of the performing of the first decoding operation comprises:
obtaining a check vector according to the execution result of the first decoding operation, wherein the check vector comprises a plurality of syndromes; and
and obtaining the decoding parameter according to the sum of the plurality of syndromes.
20. The memory control circuitry unit of claim 17, wherein the memory management circuitry, in accordance with the relative numerical relationship between the decoding parameter and the critical value, is to instruct the decoding circuitry to perform the second decoding operation on the first data based on the first one of the plurality of decoding modes comprises:
comparing the decoding parameter with the critical value; and
and deciding the first decoding mode from the plurality of decoding modes according to the comparison result.
21. The memory control circuitry unit of claim 17, wherein the first decoding mode corresponds to a first threshold, and the memory management circuitry is to instruct the decoding circuitry to perform the second decoding operation on the first data based on the first one of the plurality of decoding modes in accordance with the relative numerical relationship between the decoding parameter and the threshold comprises:
in response to the decoding parameter being less than the first critical value, instruct the decoding circuitry to perform the second decoding operation on the first data based on the first decoding mode.
22. The memory control circuitry unit of claim 21, wherein the operation of the memory management circuitry instructing the decoding circuitry to perform the second decoding operation on the first data based on the first decoding mode comprises:
in response to the decoding parameter not being less than a second threshold corresponding to a second decoding mode of the plurality of decoding modes, skip the second decoding mode and instruct the decoding circuitry to perform the second decoding operation on the first data based on the first decoding mode,
wherein the second threshold is smaller than the first threshold, and the error correction capability of the second decoding mode is lower than that of the first decoding operation.
23. The memory control circuitry of claim 17, wherein the memory management circuitry is further to:
after the decoding circuit performs the second decoding operation on the first data based on the first decoding mode, the decoding circuit adjusts a first critical value corresponding to the first decoding mode according to a result of the second decoding operation.
24. The memory control circuit unit of claim 23, wherein the operation of the memory management circuit adjusting the first threshold corresponding to the first decoding mode according to the execution result of the second decoding operation comprises:
updating a decoding success rate corresponding to the first decoding mode according to an execution result of the second decoding operation; and
and adjusting the first critical value according to the decoding success rate.
CN202211273740.3A 2022-10-18 2022-10-18 Decoding method, memory storage device and memory control circuit unit Pending CN115547388A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118280423A (en) * 2024-05-30 2024-07-02 苏州元脑智能科技有限公司 Flash memory reading method, device, computer equipment and storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118280423A (en) * 2024-05-30 2024-07-02 苏州元脑智能科技有限公司 Flash memory reading method, device, computer equipment and storage medium

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