CN115332272B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN115332272B CN115332272B CN202211256571.2A CN202211256571A CN115332272B CN 115332272 B CN115332272 B CN 115332272B CN 202211256571 A CN202211256571 A CN 202211256571A CN 115332272 B CN115332272 B CN 115332272B
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- 239000000758 substrate Substances 0.000 title claims abstract description 71
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 24
- 238000005530 etching Methods 0.000 claims description 53
- 238000000034 method Methods 0.000 claims description 12
- 230000005540 biological transmission Effects 0.000 claims description 8
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000002834 transmittance Methods 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 abstract description 8
- 238000010586 diagram Methods 0.000 description 8
- 230000002159 abnormal effect Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
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- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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Abstract
The embodiment of the invention discloses an array substrate, a preparation method thereof and a display panel. The array substrate comprises a substrate; the metal layer is arranged on one side of the substrate; the first insulating layer is arranged on one side, far away from the substrate, of the metal layer and is provided with a first through hole penetrating through the first insulating layer; the second insulating layer is arranged on one side, far away from the metal layer, of the first insulating layer and is provided with a first through hole penetrating through the second insulating layer; the first through hole is communicated with the first via hole, the projection of the first via hole on the substrate completely falls into the projection of the first through hole on the substrate, the side wall of the first through hole is positioned on the same inclined plane, the inclined angle is the same, and therefore the structure of continuity is formed through smooth connection, and the problem of fault staggering is solved.
Description
Technical Field
The invention relates to the field of display panels, in particular to an array substrate, a preparation method of the array substrate and a display panel.
Background
A Thin Film Transistor (TFT) is a core device of a flat panel display, and a bottom gate structure is widely used in a current TFT device. TFT devices of a bottom gate structure are generally classified into a BCE (Back-channel etch) type TFT device and an ESL (Etched-stopper Layer) type device according to a difference in manufacturing processes. The BCE type TFT device has the advantages of few processing steps and no etching damage to the back channel of the semiconductor layer, so that the BCE type TFT device is widely applied.
Please refer to fig. 1, fig. 1 is a schematic structural diagram of an array substrate 100 provided in the prior art, in which the array substrate 100 includes a substrate 10, a metal layer 20, a first insulating layer 30 and a second insulating layer 40, the first insulating layer 30 and the second insulating layer 40 are etched such that the first insulating layer 30 has an initial via 311 penetrating the first insulating layer 30, the second insulating layer 40 has an initial via 411 penetrating the second insulating layer 40, and the initial via 411 is communicated with the initial via 311.
In view of the above, it is necessary to develop a novel array substrate and a method for manufacturing the same, so as to solve the problem of abnormal disconnection occurring in the related art when the metal layer is connected.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method thereof and a display panel, which are used for solving the problem of abnormal disconnection caused by lap joint of metal layers in the prior art.
In order to solve the above technical problem, the embodiment of the present invention discloses the following technical solutions:
in one aspect, the present application provides an array substrate, including: a substrate; the metal layer is arranged on one side of the substrate; the first insulating layer is arranged on one side of the metal layer far away from the substrate and is provided with a first through hole penetrating through the first insulating layer; the second insulating layer is arranged on one side, far away from the metal layer, of the first insulating layer and is provided with a first through hole penetrating through the second insulating layer; the first through hole is communicated with the first via hole, and the projection of the first via hole on the substrate completely falls into the projection of the first through hole on the substrate.
In addition to or in the alternative to one or more features disclosed above, a bottom of the first via coincides with a top of the first via, and a sidewall of the first via is continuously connected with a sidewall of the first via.
In addition to or in lieu of one or more of the features disclosed above, the first insulating layer is a silicon nitride layer and the second insulating layer is a silicon oxide layer.
On the other hand, a preparation method of the array substrate is also provided, and the preparation method comprises the following steps: providing a substrate, and sequentially forming a metal layer, a first insulating layer, a second insulating layer and a patterned mask layer on the substrate, wherein the mask layer comprises a first shading part and a second shading part, the thickness of the first shading part is smaller than that of the second shading part, and a light hole for exposing the second insulating layer is formed in the first shading part; etching the first insulating layer and the second insulating layer for the first time through the mask layer to form an initial through hole at a position of the second insulating layer corresponding to the light hole, and form an initial through hole at a position of the first insulating layer corresponding to the light hole, wherein the initial through hole is communicated with the initial through hole; and removing the first shading part, and carrying out second etching on the first insulating layer and the second insulating layer through the mask layer so as to etch and form the initial through hole into a first through hole and etch and form the initial through hole into a first through hole, wherein the projection of the first through hole on the substrate completely falls into the projection of the first through hole on the substrate.
In addition to or in lieu of one or more of the features disclosed above, the step of sequentially forming a metal layer, a first insulating layer, a second insulating layer, and a patterned masking layer on the substrate comprises: sequentially forming a metal layer, a first insulating layer, a second insulating layer and a mask layer on the substrate; providing a halftone mask, wherein the halftone mask is provided with a light transmission area, a first light shielding area and a second light shielding area, and the light transmittances of the first light shielding area and the second light shielding area are different; and exposing and developing the mask layer through the halftone mask plate to form the light transmission holes at positions corresponding to the light transmission regions, form the first light shielding portions at positions corresponding to the first light shielding regions, and form the second light shielding portions at positions corresponding to the second light shielding regions.
In addition to or in lieu of one or more of the features disclosed above, the thickness of the first shade ranges from 0.3um to 1um and the width of the first shade ranges from 0.3um to 0.6um.
In addition to or instead of one or more of the features disclosed above, the thickness of the second light-shielding portion ranges from 0.6um to 2um, and the width of the second light-shielding portion ranges from 0.6um to 1.2um.
In addition to or in lieu of one or more of the features disclosed above, in the step of first etching the first and second insulating layers through the mask layer, an etching rate of the second insulating layer is less than an etching rate of the first insulating layer, a bottom aperture of the initial via is less than a top aperture of the initial via, and a projection of the initial via on the substrate falls entirely within the projection of the initial via on the substrate; the inner side wall of the initial through hole and the inner side wall of the initial through hole are staggered in a fault mode.
In addition to or in lieu of one or more of the features disclosed above, a dry etch is employed in the step of first etching the first and second insulating layers.
In addition to or in lieu of one or more of the features disclosed above, the step of first etching the first and second insulating layers wherein the second insulating layer is not etched in a vertical direction but is etched only in a horizontal direction.
In addition to one or more features disclosed above, or in the alternative, in the step of removing the first light shielding portion, the first light shielding portion and at least a part of the second light shielding portion are removed by an ashing process.
In addition to or in lieu of one or more of the features disclosed above, in the step of etching the first insulating layer and the second insulating layer a second time through the mask layer, an etching rate of the second insulating layer is greater than an etching rate of the first insulating layer, a bottom aperture of the first via is greater than a top aperture of the first via, and a projection of the first via on the substrate falls entirely within the projection of the first via on the substrate.
In addition or alternatively to one or more of the features disclosed above, after the step of etching the first insulating layer and the second insulating layer a second time, further comprising: the mask layer is removed.
In addition to or in lieu of one or more of the features disclosed above, a dry etch is employed in the step of second etching the first and second insulating layers.
In addition to or in lieu of one or more of the features disclosed above, in the step of etching the first and second insulating layers a second time, the second insulating layer has an etch rate greater than an etch rate of the first insulating layer.
In addition to or in lieu of one or more of the features disclosed above, in the step of second etching the first insulating layer and the second insulating layer, the second insulating layer is etched in a vertical direction and etched in a horizontal direction, the first insulating layer is etched only in the horizontal direction, and an etching rate in the vertical direction is greater than an etching rate in the horizontal direction.
Because the dry-etched ions bombard the film layer under the guidance of the vertical electric field to cause physical etching, and cause the vertical direction to have physical etching under the chemical etching in the horizontal direction besides the chemical etching in the horizontal direction, the etching rate in the vertical direction is far greater than the etching rate in the horizontal direction, the etching rate in the vertical direction can be greater than 3 times the etching rate in the horizontal direction, and the second insulating layer of the first light shielding part has the photoresist for blocking during the first etching, so the etching in the vertical direction is not performed, and only the etching in the horizontal direction is performed. And the photoresist of the first shading part is removed during the second etching, and the second insulating layer exposed outside is subjected to etching in the vertical and horizontal directions, so that the etching rate of the second insulating layer is higher than that of the first insulating layer, and the side wall of the first through hole is continuously connected with the side wall of the first through hole.
The first insulating layer and the second insulating layer are etched twice, so that the projection of the first through hole on the substrate completely falls into the projection of the first through hole on the substrate, the problem of abnormal disconnection caused by the overlapping of subsequent metal layers is avoided, and the stability of the device is improved; and the process is simple and the operability is high.
In another aspect, a display panel is also provided, which includes the array substrate related to the present invention.
One of the above technical solutions has the following advantages or beneficial effects: the lateral wall of first through-hole and the lateral wall of first via hole are located same inclined plane, and inclination is the same to the structure of formation continuity is connected in the same direction as smooth, has solved the staggered problem of fault.
Drawings
The technical solution and other advantages of the present invention will become apparent from the following detailed description of specific embodiments of the present invention, which is to be read in connection with the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate provided in the prior art;
fig. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic structural diagram of step 1 of the preparation method according to the embodiment of the present invention;
FIG. 5 is a schematic structural diagram of step 2 of the preparation method according to the embodiment of the present invention;
FIG. 6 is a schematic structural diagram of step 3 of the preparation method according to the embodiment of the present invention;
fig. 7 is a schematic structural diagram of step 4 in the preparation method according to the embodiment of the present invention.
Reference numerals:
an array substrate-100; a substrate-10;
a metal layer-20;
a first insulating layer-30; a second insulating layer-40;
mask layer-50; a second light-shielding portion-51;
a first light shielding portion-52; a light hole-53;
initial via-411; an initial via-311;
a first through-hole-41; a first via-31.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
Referring to fig. 2, fig. 2 is a schematic structural diagram of an array substrate 100 according to an embodiment of the present invention, the array substrate 100 includes a substrate 10, a metal layer 20, a first insulating layer 30, and a second insulating layer 40.
The metal layer 20 is provided on one side of the substrate 10. The first insulating layer 30 is disposed on a side of the metal layer 20 away from the substrate 10, the first insulating layer 30 is a silicon nitride layer, and the first insulating layer 30 has a first via hole 31 penetrating through the first insulating layer 30. The second insulating layer 40 is disposed on a side of the first insulating layer 30 away from the metal layer 20, the second insulating layer 40 is a silicon oxide layer, and the second insulating layer 40 has a first through hole 41 penetrating through the second insulating layer 40.
The first through hole 41 communicates with the first via hole 31, and a sidewall of the first through hole 41 is continuously connected to a sidewall of the first via hole 31. The bottom of the first through hole 41 coincides with the top of the first via 31, and the projection of the first via 31 on the substrate 10 falls completely within the projection of the first through hole 41 on the substrate 10. The side wall of the first through hole 41 and the side wall of the first via hole 31 are positioned on the same inclined plane, and the inclined angles are the same, so that a continuous structure is formed by smooth connection, and the problem of fault staggering is solved.
The embodiment of the invention further provides a display panel, which comprises the array substrate 100.
Referring to fig. 3, fig. 3 is a flowchart illustrating a method for manufacturing an array substrate 100 according to an embodiment of the present invention, where the method includes steps 1-4.
Step 1: providing a substrate 10, and sequentially forming a metal layer 20, a first insulating layer 30, a second insulating layer 40 and a patterned mask layer 50 on the substrate 10; the mask layer 50 includes a first light-shielding portion 52 and a second light-shielding portion 51, the first light-shielding portion 52 has a thickness smaller than that of the second light-shielding portion 51, and a light-transmitting hole 53 exposing the second insulating layer 40 is formed on the first light-shielding portion 52.
Referring to FIG. 4, the thickness of the first shading portion 52 ranges from 0.3um to 1um. Preferably, the width of the first shading portion 52 is in the range of 0.3um to 0.6um.
The thickness of the second light-shielding portion 51 is in a range of 0.6um to 2um. Preferably, the width of the second light-shielding portion 51 is in the range of 0.6um to 1.2um.
The specific steps of step 1 include:
sequentially forming a metal layer 20, a first insulating layer 30, a second insulating layer 40 and a mask layer 50 on a substrate 10;
providing a halftone mask, wherein the halftone mask is provided with a light transmission area, a first shading area and a second shading area, and the light transmission rates of the first shading area and the second shading area are different; and
the mask layer 50 is exposed and developed by a halftone mask to form light-transmitting holes 53 at positions corresponding to the light-transmitting regions, first light-shielding portions 52 at positions corresponding to the first light-shielding regions, and second light-shielding portions 51 at positions corresponding to the second light-shielding regions.
Step 2: performing a first etching of the first and second insulating layers 30 and 40 through the mask layer 50; so that an initial through hole 411 is formed at a position of the second insulating layer 40 corresponding to the light-transmitting hole 53, an initial via hole 311 is formed at a position of the first insulating layer 30 corresponding to the light-transmitting hole 53, and the initial through hole 411 is communicated with the initial via hole 311.
Referring to fig. 5, the first etching is dry etching.
In the first etching, the second insulating layer 40 of the first light shielding portion 52 has a photoresist barrier, so there is no etching in the vertical direction, but only etching in the horizontal direction, because the first insulating layer 30 uses silicon nitride, the silicon nitride reacts more violently with ions, and the silicon nitride film is also loose, so the etching rate of the first insulating layer 30 is greater than that of the second insulating layer 40.
The etching rate of the second insulating layer 40 is smaller than that of the first insulating layer 30, the bottom aperture of the initial via 411 is smaller than the top aperture of the initial via 311, and the projection of the initial via 411 on the substrate 10 completely falls into the projection of the initial via 311 on the substrate 10; the inner sidewall of the initial through hole 411 and the inner sidewall of the initial via hole 311 are staggered.
And step 3: the first light shielding portion 52 is removed, and the first insulating layer 30 and the second insulating layer 40 are subjected to second etching through the mask layer 50 to etch and form the initial through hole 411 into a first through hole 41 and the initial via hole 311 into a first via hole 31, wherein a projection of the first via hole 31 on the substrate 10 completely falls within a projection of the first through hole 41 on the substrate 10.
Referring to fig. 6, the first light-shielding portion 52 and at least a part of the second light-shielding portion 51 are removed by an ashing process.
The second etching adopts dry etching.
The initial through hole 411 is enlarged to form a first through hole 41, the initial through hole 311 is enlarged or unchanged to form a first through hole 31, the bottom of the first through hole 41 coincides with the top of the first through hole 31, and the projection of the first through hole 31 on the substrate 10 completely falls into the projection of the first through hole 41 on the substrate 10.
The etching rate of the second insulating layer 40 is greater than that of the first insulating layer 30, and the bottom aperture of the first via hole 41 is greater than the top aperture of the first via hole 31.
The second insulating layer 40 is etched in a vertical direction and etched in a horizontal direction, and the first insulating layer 30 is etched only in the horizontal direction, with the etching rate in the vertical direction being greater than that in the horizontal direction.
Because the dry etching ions bombard the film layer under the guidance of the vertical electric field to cause physical etching, and cause the vertical physical etching in addition to the horizontal chemical etching, the vertical etching rate is much greater than the horizontal etching rate, and the vertical etching rate can be greater than 3 times the horizontal etching rate. The photoresist of the first light-shielding portion 52 is removed during the second etching, and the exposed second insulating layer 40 is subjected to etching in the vertical and horizontal directions, so that the etching rate of the second insulating layer 40 is greater than that of the first insulating layer 30, so that the sidewall of the first through hole 41 is continuously connected with the sidewall of the first via hole 31.
And 4, step 4: the mask layer 50 is removed.
Referring to fig. 7, the sidewall of the first through hole 41 and the sidewall of the first via hole 31 are located on the same inclined plane, and the inclined angles are the same, so that a continuous structure is formed by smooth connection, and the problem of fault staggering is solved.
By etching the first insulating layer 30 and the second insulating layer 40 twice, the projection of the first via hole 31 on the substrate completely falls into the projection of the first through hole 41 on the substrate, so that the problem of abnormal disconnection caused by the overlapping of subsequent metal layers is avoided, and the stability of the device is improved; and the process is simple and the operability is high.
The array substrate, the manufacturing method thereof, and the display panel provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by applying specific examples, and the description of the embodiments is only used to help understanding the technical solutions and the core ideas of the present invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (4)
1. The preparation method of the array substrate is characterized by comprising the following steps:
providing a substrate, and sequentially forming a metal layer, a first insulating layer, a second insulating layer and a patterned mask layer on the substrate, wherein the first insulating layer is a silicon nitride layer, and the second insulating layer is a silicon oxide layer; the mask layer comprises a first shading part and a second shading part, the thickness of the first shading part is smaller than that of the second shading part, and a light hole for exposing the second insulating layer is formed in the first shading part;
performing first dry etching on the first insulating layer and the second insulating layer through the mask layer to form an initial through hole at a position of the second insulating layer corresponding to the light hole, and form an initial via hole at a position of the first insulating layer corresponding to the light hole, wherein the initial through hole is communicated with the initial via hole, the etching rate of the second insulating layer is less than that of the first insulating layer, the bottom aperture of the initial through hole is less than the top aperture of the initial via hole, and the projection of the initial through hole on the substrate completely falls into the projection of the initial via hole on the substrate; and
removing the first light shielding part, and performing second dry etching on the first insulating layer and the second insulating layer through the mask layer to etch and form the initial through hole into a first through hole and etch and form the initial through hole into a first through hole, wherein the etching rate of the second insulating layer is greater than that of the first insulating layer, the bottom aperture of the first through hole is greater than that of the top aperture of the first through hole, and the projection of the first through hole on the substrate completely falls into the projection of the first through hole on the substrate;
the side wall of the first through hole and the side wall of the first via hole are positioned on the same inclined plane, and the inclined angles are the same.
2. The method of claim 1, wherein the sequentially forming a metal layer, a first insulating layer, a second insulating layer, and a patterned mask layer on the substrate comprises:
sequentially forming a metal layer, a first insulating layer, a second insulating layer and a mask layer on the substrate;
providing a halftone mask, wherein the halftone mask is provided with a light transmission area, a first light shielding area and a second light shielding area, and the light transmittances of the first light shielding area and the second light shielding area are different; and
and exposing and developing the mask layer through the halftone mask plate to form the light transmission holes at positions corresponding to the light transmission areas, form the first light shielding parts at positions corresponding to the first light shielding areas, and form the second light shielding parts at positions corresponding to the second light shielding areas.
3. The method for manufacturing an array substrate according to claim 1, wherein in the step of removing the first light-shielding portion, the first light-shielding portion and at least a part of the second light-shielding portion are removed by an ashing process.
4. The method for preparing an array substrate according to claim 1, further comprising, after the step of etching the first insulating layer and the second insulating layer for the second time: the mask layer is removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211256571.2A CN115332272B (en) | 2022-10-14 | 2022-10-14 | Array substrate, preparation method thereof and display panel |
Applications Claiming Priority (1)
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