CN114743976A

CN114743976A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN114743976A
Application number: CN202210507404.4A
Authority: CN
Inventors: 王春明; 王绍迪
Original assignee: Beijing Witinmem Technology Co ltd
Current assignee: Beijing Witinmem Technology Co ltd
Priority date: 2022-05-10
Filing date: 2022-05-10
Publication date: 2022-07-12
Also published as: WO2023216368A1

Abstract

A semiconductor device and a method of manufacturing the same are provided. The manufacturing method comprises the following steps: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form a gate stack; removing portions of the oxide layer over the first and second regions of the substrate; forming a first selective gate oxide structure and a second selective gate oxide structure on a first region and a second region of a substrate, respectively, and forming a tunneling oxide structure on both sides of a gate stack, respectively; forming a selection grid on one side of the tunneling oxide structure opposite to the grid stacked body; etching the gate stack to form a first opening; forming a source region in a portion of the substrate located below the first opening; and forming a drain region in the substrate on a side of the select gate opposite the first opening.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

In electronic devices, reading and storing of data by means of a memory is required. Thus, as the demand for electronic devices continues to grow, the demand for memory technology is also increasing.

Flash memory is an electrically erasable and reprogrammable electrically non-volatile computer storage medium that retains on-chip information even after power is turned off. The flash memory is convenient to use, has the characteristics of reading and writing flexibility and high access speed, and can not lose information after power failure, so that the flash memory technology is developed very rapidly.

Flash memory includes an addressable array of memory cells, where each memory cell includes a floating gate transistor for storing corresponding information. Accordingly, it is desirable to improve methods of manufacturing flash memories (and in particular memory cells in flash memories).

Disclosure of Invention

According to some embodiments of the present disclosure, there is provided a method of manufacturing a semiconductor device, including: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form a gate stack comprised of the hard mask layer, the control gate layer, the dielectric layer and remaining portions of the floating gate layer; removing portions of the oxide layer over a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack; forming a first selection grid oxide structure and a second selection grid oxide structure on a first area and a second area of the substrate respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on two sides of the grid stacked body respectively; forming a first select gate on a side of the first tunnel oxide structure opposite the gate stack and a second select gate on a side of the second tunnel oxide structure opposite the gate stack; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remaining portion of the floating gate layer; forming a source region in a portion of the substrate located below the first opening; and forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite the first opening.

According to some embodiments of the present disclosure, a semiconductor device is provided, which is manufactured by the method as described in the present disclosure.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is a schematic flow diagram of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

2A-2H are schematic cross-sectional views of steps of methods of fabricating semiconductor devices according to some embodiments of the present disclosure;

figures 3A-3O are schematic cross-sectional views of steps of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

4A-4B are schematic cross-sectional views of steps of methods of fabricating semiconductor devices according to some embodiments of the present disclosure;

fig. 5 is a schematic cross-sectional view of a step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 6 is a schematic cross-sectional view of a step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure;

fig. 7 is a cross-sectional structural schematic of a semiconductor device according to some embodiments of the present disclosure;

FIG. 8 is a circuit schematic of a memory cell array according to some embodiments of the present disclosure;

figures 9A-9B are top plan views of memory cell arrays according to some embodiments of the present disclosure.

Detailed Description

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

Spatially relative terms such as "below …," "below …," "lower," "below …," "above …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "under" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below …" and "below …" may encompass both an orientation above … and below …. Terms such as "before …" or "before …" and "after …" or "next" may similarly be used, for example, to indicate the order in which light passes through the elements. The devices may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" refers to a alone, B alone, or both a and B.

It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to" or "adjacent to" another element or layer, it can be directly on, connected to, coupled to or adjacent to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," "directly coupled to," or "directly adjacent to" another element or layer, there are no intervening elements or layers present. However, neither "on … nor" directly on … "should be construed as requiring that one layer completely cover an underlying layer in any event.

Embodiments of the present disclosure are described herein with reference to schematic illustrations (and intermediate structures) of idealized embodiments of the present disclosure. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the present disclosure should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present disclosure.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "substrate" may refer to a substrate of a diced wafer, or may refer to a substrate of an unslit wafer. Similarly, the terms chip and die may be used interchangeably unless such an interchange would cause a conflict.

Common types of flash memory cells in the prior art include stacked gate memory cells and split gate memory cells. Compared with a stacked gate memory unit, the split gate memory unit has the technical advantages of low power consumption, high injection efficiency and the like. For a flash memory having split gate memory cells, the present disclosure provides a method of manufacturing a semiconductor device, comprising: sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate; etching the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer to form a gate stack comprised of the hard mask layer, the control gate layer, the dielectric layer and remaining portions of the floating gate layer; removing portions of the oxide layer over a first region and a second region of the substrate, wherein the first region and the second region are located on both sides of the gate stack; forming a first selection grid oxide structure and a second selection grid oxide structure on a first area and a second area of the substrate respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on two sides of the grid stacked body respectively; forming a first select gate on a side of the first tunnel oxide structure opposite the gate stack and a second select gate on a side of the second tunnel oxide structure opposite the gate stack; etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remaining portion of the floating gate layer; forming a source region in a portion of the substrate located below the first opening; and forming a first drain region in the substrate on a side of the first select gate opposite the first opening, and forming a second drain region in the substrate on a side of the second select gate opposite the first opening.

Fig. 1 is a schematic flow diagram of a method 100 of fabricating a semiconductor device, according to some embodiments of the present disclosure.

At step S101, an oxide layer, a floating gate layer, a dielectric layer, a control gate layer, and a hard mask layer are sequentially formed on a substrate.

According to some embodiments, the method of manufacturing 100 further comprises: shallow trench isolation is formed in the substrate in advance before an oxide layer is formed on the substrate. According to some embodiments, the manufacturing method 100 further comprises: a memory cell well (memory cell well) is previously implanted in the substrate before forming an oxide layer on the substrate.

According to some embodiments, the process of forming the shallow trench isolation may include, but is not limited to, the steps of: forming a liner oxide, depositing silicon nitride, exposing an active area, etching a shallow insulation trench, filling the shallow insulation trench, flattening the shallow insulation trench, and removing the silicon nitride.

According to some embodiments, step S101 comprises: forming an oxide layer on a substrate; forming a floating gate layer on the oxide layer; forming a dielectric layer on the floating gate layer; forming a control gate layer on the dielectric layer; a hard mask layer is formed on the control gate layer.

According to some embodiments, growing an oxide layer on an upper surface of a substrate; depositing floating gate polysilicon on the upper surface of the oxide layer, and planarizing the floating gate polysilicon to form a floating gate layer; depositing a dielectric material (e.g., an ONO (oxide-nitride-oxide) material) on an upper surface of the floating gate polysilicon to form a dielectric layer; depositing a control gate polysilicon on an upper surface of the dielectric layer to form a control gate layer; a hard mask material (e.g., a silicon nitride material) is deposited on the control gate layer to form a hard mask layer.

Fig. 2A shows a cross-sectional view of an exemplary structure formed after step S101. As shown in fig. 2A, the semiconductor structure 200 includes, in order from bottom to top: substrate 210, oxide layer 220, floating gate layer 230, dielectric layer 240, control gate layer 250, and hard mask layer 260.

At step S102, the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer are etched to form a gate stack comprised of the hard mask layer, the control gate layer, the dielectric layer, and remaining portions of the floating gate layer.

According to some embodiments, first, a photolithography process is performed on an upper surface of the hard mask layer to form a photoresist pattern; etching the hard mask layer, the control gate layer and the dielectric layer by using the formed photoresist pattern as a mask; next, the floating gate layer is etched continuously.

In accordance with some embodiments, after etching the hard mask layer, the control gate layer, and the dielectric layer, control gate spacers are formed on both sides of the remaining portions of the hard mask layer, the control gate layer, and the dielectric layer, e.g., a control gate oxide (e.g., silicon oxide) is deposited on both sides of the hard mask layer, the control gate layer, and the remaining portions of the dielectric layer, and the deposited control gate oxide is etched to form the control gate spacers.

Fig. 2B shows a cross-sectional view of an exemplary structure formed after steps S101 to S102. As shown in fig. 2B, the semiconductor structure 200 includes, from bottom to top: substrate 210, oxide layer 220, and gate stack 270, wherein gate stack 270 includes, from bottom to top, floating gate layer 230, dielectric layer 240, control gate layer 250, and the remaining portions of hard mask layer 260.

At step S103, portions of the oxide layer over first and second regions of the substrate are removed, wherein the first and second regions are located on both sides of the gate stack.

According to some embodiments, portions of the oxide layer over the first and second regions of the substrate are removed by cleaning, photolithography, and etching steps, and a substrate oxide structure is formed at the gate stack.

Fig. 2C shows a cross-sectional view of an exemplary structure formed after steps S101 to S103. As shown in fig. 2C, the semiconductor structure 200 includes, from bottom to top: substrate 210, substrate oxide structure 221, and gate stack 270, wherein gate stack 270 includes, from bottom to top, floating gate layer 230, dielectric layer 240, control gate layer 250, and the remaining portions of hard mask layer 260.

At step S104, a first select gate oxide structure and a second select gate oxide structure are formed on the first region and the second region of the substrate, respectively, and a first tunnel oxide structure and a second tunnel oxide structure are formed on both sides of the gate stack, respectively.

According to some embodiments, forming the first and second select gate oxide structures on the first and second regions of the substrate, respectively, and forming the first and second tunnel oxide structures on both sides of the gate stack, respectively, comprises: depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack to form first and second select gate oxide structures; and removing portions of the first and second gate oxide films on the upper surface of the gate stack to form first and second tunneling oxide structures.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further comprises, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack: depositing a first gate oxide film on the first region, the second region and the high voltage pipe region of the substrate, and on the side and upper surfaces of the gate stack; and removing portions of the first gate oxide film on the first region, the second region, the upper surface, and the side surfaces of the gate stack of the substrate, and depositing a second gate oxide film on the first region and the second region of the substrate, and on the side surfaces and the upper surface of the gate stack includes: a second gate oxide film is deposited on the first, second and high voltage tube regions of the substrate, and on the sides and upper surface of the gate stack. In embodiments as described in the present disclosure, a high voltage pipe oxide structure of a different thickness than the select gate oxide structure is formed on the high voltage pipe region by two oxide film depositions and excess oxide is removed during the two depositions to facilitate subsequent formation of a corresponding high voltage logic device (e.g., 11V powered high voltage device) on the high voltage pipe region.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further comprises, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack: depositing a first gate oxide film on the first and second regions of the substrate and on the side and upper surfaces of the gate stack; and removing portions of the first gate oxide film on the first and second regions of the substrate, the upper surface of the gate stack, and removing a portion of the first gate oxide film on the side surfaces of the gate stack. According to some embodiments, a portion of the first gate oxide film on the sidewalls of the gate stack is retained by etching (e.g., dry etching and wet etching) the first gate oxide film. According to some embodiments, after etching the first gate oxide film, a high temperature rapid thermal process is performed to enhance the quality of the oxide on the sidewalls.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further comprises, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack: depositing a first gate oxide film on the first and second regions of the substrate and on the side and upper surfaces of the gate stack; removing portions of the first gate oxide film on the first and second regions of the substrate, the upper surface and the side surfaces of the gate stack; and forming sidewall oxide structures on the sides of the gate stack. According to some embodiments, the sidewall oxide structure is formed on the sides of the gate stack by means of poly-silicon oxidation.

According to the embodiments described above, the select gate oxide structure may be made to be different in thickness from the tunnel oxide structure by leaving or additionally forming an oxide structure on the sides of the gate stack before depositing the second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack, e.g., a thicker tunnel oxide structure may be advantageous for floating gate data storage and a thinner select gate oxide structure may be advantageous for improving memory device performance (e.g., providing a larger read current).

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further comprises, prior to removing the portion of the first gate oxide film over the first and second regions of the substrate and over the upper surface of the gate stack: a select gate channel ion (e.g., boron or BF2) implant is performed in the first and second regions of the substrate.

According to some embodiments, performing a select gate channel ion implant in the first and second regions of the substrate comprises: carrying out selective grid channel photoetching to form a photoresist pattern so as to protect the region which does not need to be subjected to ion implantation; with the formed photoresist pattern as a mask, select gate channel ion implantation is performed.

According to some embodiments, the method of fabricating a semiconductor device according to the present disclosure further comprises, after depositing a second gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on the side and upper surfaces of the gate stack: performing logic well injection in the substrate; forming a logic IO gate oxide structure on a substrate; and forming a logic core gate oxide structure on the substrate.

Fig. 2D shows a cross-sectional view of an exemplary structure formed after steps S101 to S104. As shown in fig. 2D, the semiconductor structure 200 includes, in addition to the substrate 210, the substrate oxide structure 221, and the gate stack 270, a first select gate oxide structure 222a on a first region on the left side of the gate stack 270, a first tunnel oxide structure 271a on the left side of the gate stack 270, a second select gate oxide structure 222b on a second region on the right side of the gate stack 270, and a second tunnel oxide structure 271b on the right side of the gate stack 270. It should be understood that although the first select gate oxide structure 222a and the first tunnel oxide structure 271a are shown as two separate portions and the second select gate oxide structure 222b and the second tunnel oxide structure 271b are shown as two separate portions, the first select gate oxide structure 222a and the first tunnel oxide structure 271a may actually be a continuous oxide but with different thicknesses and the second select gate oxide structure 222b and the second tunnel oxide structure 271b may actually be a continuous oxide but with different thicknesses, e.g., formed by the two oxide film deposition steps described above.

At step S105, a first select gate is formed on a side of the first tunnel oxide structure opposite the gate stack, and a second select gate is formed on a side of the second tunnel oxide structure opposite the gate stack.

According to some embodiments, forming the first select gate on a side of the first tunnel oxide structure opposite the gate stack and forming the second select gate on a side of the second tunnel oxide structure opposite the gate stack comprises: depositing select gate polysilicon on the first and second select gate oxide structures and on the gate stack; and removing portions of the deposited select gate polysilicon to form a first select gate and a second select gate.

According to some embodiments, the deposited select gate polysilicon has the same coverage on the surfaces of the first and second select gate oxide structures and the gate stack such that the deposited select gate polysilicon appears "raised" in shape. For example, as described in detail below with reference to fig. 3I.

According to some embodiments, removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate comprises: carrying out planarization treatment on the deposited selection grid polysilicon; etching the selection grid polysilicon after the planarization treatment to form a first polysilicon structure and a second polysilicon structure which are respectively positioned on a first area and a second area of the substrate; and etching the first polysilicon structure and the second polysilicon structure to form a first select gate and a second select gate, respectively.

In accordance with some embodiments, the deposited select gate polysilicon is subjected to a planarization process to remove the select gate polysilicon deposited over the gate stack. In accordance with some embodiments, during the planarization process of the deposited select gate polysilicon, the oxide deposited over the gate stack in the previous step may also be removed.

According to some embodiments, etching the planarized select gate polysilicon to form first and second polysilicon structures on first and second regions of the substrate, respectively, includes: shoulders of the select gate polysilicon in the shape of "L" on both sides of the gate stack are etched to form first and second polysilicon structures in the shape of rectangles on the first and second regions of the substrate, respectively, for subsequent etching using the photoresist or hard mask spacers as a mask to form the first and second select gates. For example, as described in detail below with reference to fig. 3J.

According to some embodiments, etching the first and second polysilicon structures to form the first and second select gates, respectively, includes: carrying out first photoetching treatment on the first polycrystalline silicon structure and the second polycrystalline silicon structure; etching the first polysilicon structure and the second polysilicon structure with the photoresist pattern formed by the first photolithography process as a mask to form a first select gate and a second select gate, respectively; and removing the photoresist pattern formed by the first photolithography process. For example, as described in detail below with reference to fig. 3K-3L.

According to some embodiments, etching the first and second polysilicon structures to form the first and second select gates, respectively, includes: forming first and second hard mask spacers on either side of the gate stack, respectively, wherein the first hard mask spacers are located on the first polysilicon structures and the second hard mask spacers are located on the second polysilicon structures; and etching the first and second polysilicon structures using the first and second hard mask spacers as a mask to form first and second select gates, respectively. For example, as described in detail below with reference to fig. 4A-4B.

According to some embodiments, removing portions of the deposited select gate polysilicon to form the first and second select gates comprises: the deposited select gate polysilicon is self-aligned etched to form first and second select gates, respectively. For example, as described in detail below with reference to fig. 5.

According to some embodiments, the method of manufacturing a semiconductor device according to the present disclosure further comprises: depositing logic gate polysilicon on the logic gate region of the substrate while depositing select gate polysilicon on the first and second select gate oxide structures and on the gate stack; and removing portions of the logic gate polysilicon to form the logic gate while removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate.

According to further embodiments, logic gate polysilicon is deposited on the logic gate region of the substrate while depositing select gate polysilicon on the first and second select gate oxide structures and on the gate stack; and, in a different processing step than the removal of the deposited portion of the select gate polysilicon, a portion of the logic gate polysilicon is removed to form the logic gate.

Fig. 2E shows a cross-sectional view of an exemplary structure formed after steps S101 to S105. As shown in fig. 2E, the semiconductor structure 200 includes, in addition to the substrate 210, the substrate oxide structure 221, the gate stack 270, the first select gate oxide structure 222a, the first tunnel oxide structure 271a, the second select gate oxide structure 222b, and the second tunnel oxide structure 271b, a first select gate 280a on a side of the first tunnel oxide structure 271a opposite to the gate stack 270, and a second select gate 280b on a side of the second tunnel oxide structure 271b opposite to the gate stack 270.

At step S106, the gate stack is etched to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remaining portion of the floating gate layer.

According to some embodiments, etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and the remaining portion of the floating gate layer comprises: performing source electrode photoetching to form a photoresist pattern; the gate stack is etched using the formed photoresist pattern as a mask to form a first opening.

Fig. 2F shows a cross-sectional view of an exemplary structure formed after steps S101 to S106. As shown in fig. 2F, compared to fig. 2E, the first opening 272 penetrates the hard mask layer, the control gate layer, the dielectric layer and the remaining portions of the floating gate layer, wherein the remaining portions of the hard mask layer, the control gate layer, the dielectric layer and the floating gate layer include gate structures of memory cells respectively belonging to two sides, i.e., a gate structure composed of the first floating gate 230a, the first dielectric structure 240a, the first control gate 250a and the first hard mask 260a on the left side and a gate structure composed of the second floating gate 230b, the second dielectric structure 240b, the second control gate 250b and the second hard mask 260b on the right side.

At step S107, a source region is formed in a portion of the substrate located below the first opening.

According to some embodiments, the source region is formed by source ion implantation (e.g., arsenic and phosphorous) to form a graded junction in the substrate, i.e., in the source region, the source ion doping concentration is gradually decreased in a direction from the substrate oxide structure to the substrate to improve the pressure-bearing capability of the semiconductor device. In the embodiment as disclosed in the present disclosure, since the gate structure and the oxide structure of the memory cells on both sides are formed first and then the source region implantation is performed, the influence on the performance of the source region due to the thermal deposition step for forming the gate structure and the oxide structure is avoided.

Fig. 2G shows a cross-sectional view of an exemplary structure formed after steps S101-S107. As shown in fig. 2G, the semiconductor device 200 includes a source region 212 in the substrate 210 below the first opening 272, as compared to fig. 2F.

At step S108, a first drain region is formed in the substrate on the side of the first select gate opposite the first opening, and a second drain region is formed in the substrate on the side of the second select gate opposite the first opening.

According to some embodiments, forming the first drain region in the substrate at a side of the first select gate opposite the first opening, and forming the second drain region in the substrate at a side of the second select gate opposite the first opening includes: performing lightly doped drain implantation in the substrate at the side of the first select gate opposite to the first opening and the substrate at the side of the second select gate opposite to the first opening to form a first lightly doped drain region at the side of the first select gate and a second lightly doped drain region at the side of the second select gate; forming a first drain spacer on a side of the first select gate opposite the first opening, and forming a second drain spacer on a side of the second select gate opposite the first opening; forming a first source spacer on a side of the first selection gate facing the first opening, and forming a second source spacer on a side of the second selection gate facing the first opening; and performing a heavily doped drain implant in the substrate at a side of the first drain spacer opposite the first opening and in the substrate at a side of the second drain spacer opposite the first opening to form a first heavily doped drain region at a side of the first drain spacer and a second heavily doped drain region at a side of the second drain spacer.

Fig. 2H shows a cross-sectional view of an exemplary structure formed after steps S101 to S108. As shown in fig. 2H, compared to fig. 2G, the semiconductor device 200 includes a first drain region 211a formed in the substrate 210 at a side of the first select gate 280a opposite to the first opening 272 and a second drain region 211b formed in the substrate 210 at a side of the second select gate 280b opposite to the first opening 272.

According to some embodiments, the method of manufacturing a semiconductor device according to the present disclosure further comprises: a silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

In a conventional method for manufacturing a semiconductor device, an opening between two adjacent memory cells and a source region under the opening are formed, and then a select gate is formed at one side of each memory cell. In the method for manufacturing a semiconductor device according to the present disclosure, since the select gates on both sides of the gate stack are formed first, and then the opening passing through the gate stack and the source region located below the opening are formed, there is no deposition of an excessive select gate material in the opening as described above with reference to the conventional manufacturing method, and thus, steps for removing the excessive select gate material are reduced, and the production cost is reduced; and, avoid depositing the conductive polycrystalline silicon and using the way such as dry etching to remove the polycrystalline silicon deposited in more ditch groove areas, reduce the technological risk that increases and the etched wafer surface produces the probability of the defect in the course of etching, raise the chip yield.

In addition, in the conventional method for manufacturing a semiconductor device, since the source region under the opening between two adjacent memory cells is formed first and then deposited to form the remaining structure of the memory cell, the deposition process performed after the formation of the source region will affect the performance of the source region (e.g., further enlarge the source region), so that the process for forming the source region is more demanding (i.e., the desired performance can be maintained after the subsequent heat treatment of multiple subsequent process steps (e.g., deposition)). In the method for manufacturing the semiconductor device according to the present disclosure, since each deposition process is performed before the source region is formed, the formed source region is prevented from being affected by the subsequent deposition process, thereby reducing the process requirements for the source region.

Fig. 3A-3O are schematic cross-sectional views of steps of methods of fabricating a semiconductor device 300, according to some embodiments of the present disclosure.

According to some embodiments, as shown in fig. 3A, similar to that described with reference to fig. 2A, the semiconductor structure 300 comprises, in order from bottom to top: substrate 210, oxide layer 220, floating gate layer 230, dielectric layer 240, control gate layer 250, and hard mask layer 260.

According to some embodiments, as shown in fig. 3B, a photoresist is coated on an upper surface of the hard mask layer 260, a photolithography process is performed to form a photoresist pattern 290, and the hard mask layer 260, the control gate layer 250, and the dielectric layer 240 are etched with the photoresist pattern 290 as a mask.

According to some embodiments, as shown in fig. 3C, the photoresist pattern shown in fig. 3B is removed, first and second control gate spacers 273a and 273B are formed on both sides of the remaining portions of the hard mask layer 260, the control gate layer 250, and the dielectric layer 240, e.g., a control gate oxide is deposited, and the deposited control gate oxide is etched to form the control gate spacers.

According to some embodiments, floating gate layer 230 is etched to form a gate stack including floating gate layer 230, dielectric layer 240, control gate layer 250, and hard mask layer 260, as shown in fig. 3D.

According to some embodiments, as shown in fig. 3E, portions of the oxide layer in the first and second regions of the substrate 210 (i.e., the regions on which the select gates are to be formed), as well as the high voltage tube regions, are removed (e.g., by cleaning, photolithography, and etching processes, etc.) to form a substrate oxide structure 221.

According to some embodiments, as shown in fig. 3F, a first gate oxide film 291 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210, and on the high voltage pipe region and on the upper surface of the hard mask layer 280.

According to some embodiments, as shown in fig. 3G, performing a select gate channel ion implantation in the first and second regions of the substrate 210 comprises: carrying out selective grid channel photoetching to form a photoresist pattern so as to protect the region which does not need to be subjected to ion implantation; performing select gate channel ion implantation with the formed photoresist pattern as a mask; next, portions of the first gate oxide film 291 on the first and second regions, and the sidewalls and upper surface of the gate stack are removed. It should be understood that although not shown, a portion of the first gate oxide film 291 on the high voltage region of the substrate 210 is left for subsequent formation of a corresponding oxide structure of the high voltage region.

According to some embodiments, as shown in fig. 3H, a second gate oxide film 292 covering the semiconductor device 300 is formed on the first and second regions of the substrate 210, and on the high voltage pipe region and on the upper surface of the hard mask layer 280. Although not shown in fig. 3H, logic well implants may be performed in substrate 210, logic IO gate oxide structures formed on substrate 210, and logic core gate oxide structures formed on substrate 210, according to some embodiments.

According to some embodiments, as shown in fig. 3I, a select gate silicide 280 is deposited on the second gate oxide film 292, wherein the select gate silicide 280 has a substantially uniform coverage. Logic gate polysilicon may be deposited for subsequent formation of logic gates, along with select gate suicide 280 in fig. 3I, according to some embodiments.

According to some embodiments, as shown in fig. 3J, the semiconductor structure 300 is planarized and polysilicon etched to remove portions of the select gate silicide 280 to form a first polysilicon structure 281a on the first region and a second polysilicon structure 281b on the second region, and to remove portions of the first gate oxide film 291 and the second gate oxide film 292 on the hard mask layer 260.

According to some embodiments, as shown in fig. 3K, the first poly structure 281a and the second poly structure 281b are subjected to a photolithography process; the first and

second polysilicon structures

281a and 281b are etched using the photoresist pattern 293 formed by the photolithography process as a mask to form the first and second

select gates

280a and 280b, respectively. According to some embodiments, a logic gate may be formed along with the steps illustrated in fig. 3K.

According to some embodiments, as shown in fig. 3L, a photolithography process (e.g., corresponding to

photoresist patterns

294a and 294b as shown in fig. 3L) and a corresponding etch of the source region are performed to form a first opening 272, and a source ion implantation is performed in a portion of the substrate 210 below the first opening 272 to form the source region 212. According to some embodiments, the source ion implantation may be an N-type ion implantation. According to further embodiments, the source ion implantation may include a suitably augmented P-type ion implantation in addition to the N-type ion implantation to adjust the floating gate channel threshold voltage.

According to some embodiments, as shown in fig. 3M, a Lightly Doped Drain (LDD) implant lithography (e.g., corresponding to the photoresist pattern 295 shown in fig. 3M) is performed and a lightly doped drain implant (e.g., arsenic) is performed in the substrate 210 at a side of the first select gate 280a opposite the first opening 272 and in the substrate 210 at a side of the second select gate 280b opposite the first opening 272 to form a first lightly doped drain region 2111a at a side of the first select gate 280a and a second lightly doped drain region 2111b at a side of the second select gate 280 b. According to some embodiments, after performing the lightly doped drain implant, related processes for forming the logic IO/core device may be performed. According to some embodiments, the photoresist pattern 295 may be removed after performing the lightly doped drain implant.

According to some embodiments, as shown in fig. 3N, first, a first drain spacer 273a is formed at a side of the first select gate 280a opposite to the first opening 272, and a second drain spacer 273b is formed at a side of the second select gate 280b opposite to the first opening 272, a first source spacer 274a is formed at a side of the first select gate 280a facing the first opening 272, and a second source spacer 274b is formed at a side of the second select gate 280b facing the first opening 272; next, heavily doped drain implant lithography (e.g., corresponding to the photoresist pattern 296 illustrated in fig. 3N) is performed and a heavily doped drain implant is performed in the substrate 210 at a side of the first drain spacer 273a opposite the first opening 272 and in the substrate 210 at a side of the second drain spacer 273b opposite the first opening 272 to form a first heavily doped drain region 2112a at a side of the first drain spacer 273a and a second heavily doped drain region 2112b at a side of the second drain spacer 273 b. According to some embodiments, a baseline logic process may be performed after the heavily doped drain implant is performed.

According to some embodiments, a silicide structure is formed on the first select gate, the first drain region, the source region, the second select gate, and the second drain region. As shown in fig. 3O, silicide structures 223a-223e are formed on the first select gate 280a, the first heavily doped drain region 2112a, the source region 223c, the second select gate 280b, and the second heavily doped drain region 2112 b. In accordance with some embodiments, as shown in fig. 3O, portions of the oxide layer 220 between the first source spacer 274a and the second source spacer 274b, and over the first lightly doped drain region 2111a, the first heavily doped drain region 2112a, the second lightly doped drain region 2111b, and the second heavily doped drain region 2112b are removed, and a silicide structure 223c is formed on the substrate 210 exposed by the removal of the oxide layer 220.

According to some embodiments, in the semiconductor structure as shown in fig. 3O, since the gate stack is etched separately on the source side, an asymmetric control gate spacer may be formed only on one side of the control gate (i.e., the control gate spacer is not required to be formed on the source side), increasing the coupling capacitance ratio of the control gate to the floating gate, thereby increasing the efficiency of electron injection at the time of writing operation, or decreasing the voltage value of the control gate while maintaining the same efficiency, to reduce the requirement for a high voltage tube.

Fig. 4A-4B are schematic cross-sectional views of steps of methods of fabricating a semiconductor device 400, according to some embodiments of the present disclosure.

According to some embodiments, after forming the first polysilicon structure 281a located on the first region and the second polysilicon structure 281b located on the second region as shown in fig. 3J, first and second

hard mask spacers

282a and 282b are formed on both sides of the semiconductor device 200, respectively, as shown in fig. 4A, wherein the first hard mask spacer 282a is located on the first polysilicon structure 281a and the second hard mask spacer 282b is located on the second polysilicon structure 281b, for example, by depositing a hard mask material and etching the hard mask material to form the first and second

hard mask spacers

282a and 282 b.

In accordance with some embodiments, as shown in fig. 4B, the first and second polysilicon structures 281a, 281B are etched, using the first and second hardmask spacers 282a, 282B as a mask, to form first and second select gates 280a, 280B, respectively.

According to some embodiments, after forming the semiconductor structure 400 as shown in fig. 4B, process steps as described above with reference to fig. 3L-3O may be performed to form a flash memory semiconductor device.

Fig. 5 is a schematic cross-sectional view of a step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming the first poly structure 281a on the first region and the second poly structure 281b on the second region as shown in fig. 3I, the deposited select gate poly is self-aligned etched to form the first select gate 280a and the second select gate 280b, respectively, as shown in fig. 5.

According to some embodiments, after forming the semiconductor structure 500 as shown in fig. 5, process steps as described above with reference to fig. 3L-3O may be performed to form a flash memory semiconductor device.

Fig. 6 is a schematic cross-sectional view of a step of a method of fabricating a semiconductor device according to some embodiments of the present disclosure.

According to some embodiments, after forming the first gate oxide film 291 covering the semiconductor device 300 as shown in fig. 3F, as shown in fig. 6, a select gate channel ion implantation is performed in the first and second regions of the substrate 210, including: carrying out selective grid channel photoetching to form a photoresist pattern so as to protect the region which does not need to be subjected to ion implantation; performing select gate channel ion implantation with the formed photoresist pattern as a mask; next, portions of the first gate oxide film 291 on the first and second regions and the upper surface of the gate stack are removed, and a portion of the first gate oxide film 291 on the side surface of the gate stack is removed to form

sidewall oxide structures

291a and 291b on both sides of the gate spacer. According to some embodiments, a portion of the first gate oxide film 291 on the sidewalls of the gate stack is retained by etching (e.g., dry etching and wet etching) the first gate oxide film 291. According to other embodiments, instead of partially removing the first gate oxide film 291 on the side of the gate stack, the first gate oxide film 291 on the side of the gate stack is completely removed and then a thickness of oxide is formed on the floating gate sidewalls by, for example, poly-silicon oxidation.

In accordance with some embodiments, after forming the semiconductor structure 600 as shown in fig. 6, process steps as described above with reference to fig. 3H-3O may be performed to form a flash memory semiconductor device.

There is also provided, as an embodiment of the present disclosure, a semiconductor device manufactured by the method of manufacturing a semiconductor device as described in the present disclosure.

Fig. 7 is a cross-sectional structural schematic diagram of a semiconductor device 700, according to some embodiments of the present disclosure.

According to some embodiments, the semiconductor device 700 includes a substrate 210, a substrate oxide structure 221 formed over the substrate 210, gate stacks 270a and 270b located on the substrate oxide structure 221, the first select gate 280a, the second select gate 280b, a first drain region 211a, a second drain region 211b, and a source region 212 located in the substrate 210, wherein the first gate stack 270a includes a first floating gate 230a, a first dielectric structure 240a, a first control gate 250a, and a first hard mask 260a, and the second gate stack 270b includes a second floating gate 230b, a second dielectric structure 240b, a second control gate 250b, and a second hard mask 260 b.

According to some embodiments, the semiconductor device 700 further includes a substrate gate oxide structure 221 located below the first and second gate stacks 270a, 270b, a first tunnel oxide structure 271a located between the first select gate 280a and the first gate stack 270a, a second tunnel oxide structure 271b located between the second select gate 280b and the second gate stack 270b, a first select gate oxide structure 222a located below the first select gate 280a, and a second select gate oxide structure 222b located below the second select gate 280 b.

According to some embodiments, the semiconductor device 700 includes two memory cells sharing the source region 212. According to some embodiments, the semiconductor device 700 includes a first program channel 213a, a second program channel 213b, a first erase channel 214a corresponding to the memory cells on the left side, and a second program channel 213c, a second program channel 213d, a second erase channel 214b corresponding to the memory cells on the right side. According to some embodiments, the first program channel 213a extends from the first drain region 211a to an edge portion of the first floating gate 230a facing the first select gate 280a, the second program channel 213b extends from the first drain region 211a to the source region 212, the first erase channel 214a extends from the first floating gate 230a to the first select gate 280a, the third program channel 213b extends from the second drain region 211b to an edge portion of the second floating gate 230b facing the second select gate 280b, the fourth program channel 213b extends from the second drain region 211b to the source region 212, and the second erase channel 214b extends from the second floating gate 230b to the second select gate 280 b. Wherein the processes of the program operation, the erase operation, and the read operation are similar for the memory cells on the left side and the memory cells on the right side. Hereinafter, the program operation, the erase operation, and the read operation will be described by taking the memory cell on the left side as an example.

According to some embodiments, when a program operation is performed, a positive voltage (e.g., 1.0-1.6V) higher than the threshold voltage is applied to the first select gate 280a, and a positive voltage (e.g., 4.5-7V) is applied to the source terminal (i.e., the source region 212) to provide a strong lateral electric field, and a negative current (e.g., 1 μ a) is injected into the first drain region 211a, while a portion of the hot electrons are injected into the first floating gate 230a through the first program channel 211a and a portion of the hot electrons migrate to the source terminal through the second program channel 211b due to electron source side injection effect.

According to some embodiments, when performing the erase operation, a higher positive voltage (e.g., 7-11V) is applied to the first select gate 280a, a higher negative voltage (e.g., -7V-11V) is applied to the first control gate 250a to form a voltage difference between the first select gate 280a and the first floating gate 230a, and the first drain region 211a and the source region 212 are both set to 0V, at which time electrons are pulled away from the first floating gate 230a by the voltage difference between the first select gate 280a and the first floating gate 230a due to FN (Fowler-Nordheim) tunneling effect.

According to some embodiments, when a read operation is performed, the source region 212 is set to 0V by applying a positive voltage (e.g., 1.8V) to the first select gate 280a, a positive voltage (e.g., 1.8V) to the first control gate 250a, and a lower positive voltage (e.g., 0.6V) to the first drain region 211a, and the state of the memory cell is determined by the magnitude of the current between the source terminal and the drain terminal.

Fig. 8 is a circuit schematic of a memory cell array 800 according to some embodiments of the present disclosure. It should be understood that the numbers of memory cells, word lines, bit lines, source lines, and erase lines in fig. 8 are merely illustrative, and any of the above numbers may be adjusted to achieve a larger or smaller scale memory cell array according to practical application requirements.

As shown in fig. 8, the memory cell array 800 includes a plurality of memory cells (e.g., memory cell 810 shown in fig. 8). According to some embodiments, each memory cell includes a select transistor and a floating transistor connected in series, e.g., memory cell 810 in fig. 8 includes a select transistor 811 and a floating gate transistor 812, where a fixed address memory cell may be selected for operation by the select transistor 811, while the floating gate transistor 812 may store information.

According to some embodiments, each row of memory cells corresponds to one word line, e.g., in fig. 8, the memory cells of the upper row correspond to word line WLn-1, the memory cells of the lower row correspond to word line WLn, and each word line is connected to the gate of the select transistor in the corresponding memory cell. According to some embodiments, the memory cells of each column correspond to one bit line, e.g., in fig. 8, the memory cells of the left column correspond to bit line BLn-1, the memory cells of the middle column correspond to bit line BLn, the memory cells of the right column correspond to bit line BLn +1, and each bit line is connected to the drain of the select transistor in the corresponding memory cell. According to some embodiments, the memory cells of two adjacent rows correspond to one source line, for example, in fig. 8, the memory cells of two upper and lower rows each correspond to a source line SL, and each source line is connected to the source of the floating gate transistor in the corresponding memory cell. According to some embodiments, the source lines of all memory cells in each sector in the memory are electrically connected together. According to some embodiments, in the memory cell array 800, each row of memory cells corresponds to one control line, e.g., in fig. 8, the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each control line is connected to the control gate of the floating transistor in the corresponding memory cell;

according to some embodiments, the drain of the select transistor in the memory cell corresponds to the first drain region 211a in the semiconductor device 700 shown in fig. 7, for example, the gate of the select transistor in the memory cell corresponds to the first select gate 280a in the semiconductor device 700 shown in fig. 7, the floating gate of the floating transistor in the memory cell corresponds to the first floating gate 230a in the semiconductor device 700 shown in fig. 7, the control gate of the floating transistor in the memory cell corresponds to the first control gate 230a in the semiconductor device 700 shown in fig. 7, and the source of the floating transistor in the memory cell corresponds to the source region 212 in the semiconductor device 700 shown in fig. 7.

Figures 9A-9B are top plan views of memory cell arrays according to some embodiments of the present disclosure. As shown in FIG. 9A, the memory cell array 900 includes a plurality of bit lines BLn-1, BLn, and BLn +1, a plurality of word lines WLn-1 and WLn, a plurality of floating gates FG1-FG6, and source lines SL.

According to some embodiments, the memory cells of each column correspond to the same bit line, e.g., as shown in FIG. 9A, the two memory cells of the left column both correspond to bit line BLn-1. It should be understood that although not shown, the bit line structures of the memory cells of the same column are electrically connected.

According to some embodiments, each row of memory cells corresponds to the same word line, e.g., as shown in FIG. 9A, the three memory cells of the upper row all correspond to word line WLn 1. According to some embodiments, each word line extends through multiple memory cells in the same row, as shown in FIG. 9A.

According to some embodiments, each row of memory cells corresponds to one control line, e.g., in fig. 9A, the upper row of memory cells corresponds to control line CGn-1, the lower row of memory cells corresponds to control line CGn, and each control line is connected to a floating gate in the corresponding memory cell.

According to some embodiments, the memory cells of adjacent rows correspond to the same source line, for example, as shown in fig. 9A, six memory cells in the upper and lower two rows each correspond to a source line SL. According to some embodiments, as shown in fig. 9A, a source line SL extends in the substrate through the memory cells of adjacent rows, wherein the source line communicates the source regions in the plurality of bit lines.

The memory cell array 900 shown in fig. 9B differs from the memory cell array 900 shown in fig. 9A in that: instead of the source line SL extending through a plurality of bit lines in the substrate, a corresponding tungsten plug (e.g., a corresponding tungsten plug Wn-1 of the bit line BLn-1) is disposed on each bit line, and the respective tungsten plugs are connected by a metal line to communicate with the source regions in the plurality of bit lines.

Some exemplary aspects of the disclosure are described below.

Aspect 1 is a method of manufacturing a semiconductor device, including:

sequentially forming an oxide layer, a floating gate layer, a dielectric layer, a control gate layer and a hard mask layer on a substrate;

etching the hard mask layer, the control gate layer, the dielectric layer, and the floating gate layer to form a gate stack comprised of the hard mask layer, the control gate layer, the dielectric layer, and remaining portions of the floating gate layer;

removing portions of the oxide layer over first and second regions of the substrate, wherein the first and second regions are located on both sides of the gate stack;

forming a first select gate oxide structure and a second select gate oxide structure on the first region and the second region of the substrate, respectively, and forming a first tunneling oxide structure and a second tunneling oxide structure on both sides of the gate stack, respectively;

forming a first select gate on a side of the first tunneling oxide structure opposite the gate stack and a second select gate on a side of the second tunneling oxide structure opposite the gate stack;

etching the gate stack to form a first opening through the hard mask layer, the control gate layer, the dielectric layer, and a remaining portion of the floating gate layer;

forming a source region in a portion of the substrate located below the first opening; and

a first drain region is formed in the substrate on a side of the first select gate opposite the first opening, and a second drain region is formed in the substrate on a side of the second select gate opposite the first opening.

Aspect 2 the method of aspect 1, wherein the forming first and second select gate oxide structures on the first and second regions of the substrate, respectively, and forming first and second tunnel oxide structures on both sides of the gate stack, respectively, comprises:

depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack to form the first and second select gate oxide structures; and

removing portions of the first and second gate oxide films on an upper surface of the gate stack to form the first and second tunneling oxide structures.

Aspect 3. the method of aspect 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate, and on the sides and upper surface of the gate stack:

depositing a first gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack; and

removing portions of the first gate oxide film on the first and second regions of the substrate, an upper surface of the gate stack, and a portion of the first gate oxide film on a side of the gate stack.

Aspect 4. the method of aspect 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate, and on the sides and upper surface of the gate stack:

depositing a first gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack;

removing portions of the first gate oxide film on the first and second regions of the substrate, an upper surface and sides of the gate stack; and

sidewall oxide structures are formed on sides of the gate stack.

Aspect 5 the method of aspect 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surface of the gate stack:

depositing a first gate oxide film on the first region, the second region and the high voltage tube region of the substrate, and on a side surface and an upper surface of the gate stack; and

removing portions of the first gate oxide film on the first region, the second region, the upper surface and sides of the gate stack of the substrate, and the depositing a second gate oxide film on the first region and the second region of the substrate, and the sides and upper surface of the gate stack comprises:

depositing a second gate oxide film on the first, second and high voltage tube regions of the substrate, and on side and upper surfaces of the gate stack.

Aspect 6 the method of aspect 5, further comprising, prior to the removing the portions of the first gate oxide film on the first and second regions of the substrate and on the upper surface of the gate stack:

performing a select gate channel ion implant in the first region and the second region of the substrate.

Aspect 7. the method of aspect 5, further comprising, after depositing a second gate oxide film on the first, second, and high-voltage tube regions of the substrate, and on the sides and upper surface of the gate stack:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate; and

a logic core gate oxide structure is formed on the substrate.

Aspect 8. the method of any of aspects 1-7, wherein the forming a first select gate on a side of the first tunneling oxide structure opposite the gate stack and forming a second select gate on a side of the second tunneling oxide structure opposite the gate stack comprises:

depositing select gate polysilicon on the first and second select gate oxide structures and on the gate stack; and

removing portions of the deposited select gate polysilicon to form the first select gate and the second select gate.

Aspect 9. the method of aspect 8, wherein the removing the deposited portion of the select gate polysilicon to form the first and second select gates comprises:

carrying out planarization treatment on the deposited selection grid polysilicon;

etching the selection grid polysilicon subjected to the planarization treatment to form a first polysilicon structure and a second polysilicon structure which are respectively positioned on a first area and a second area of the substrate; and

etching the first and second polysilicon structures to form the first and second select gates, respectively.

Aspect 10 the method of aspect 9, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

carrying out first photoetching treatment on the first polycrystalline silicon structure and the second polycrystalline silicon structure;

etching the first and second polysilicon structures using the photoresist pattern formed by the first photolithography process as a mask to form the first and second select gates, respectively; and

and removing the photoresist pattern formed by the first photoetching treatment.

Aspect 11 the method of aspect 9, wherein the etching the first and second polysilicon structures to form the first and second select gates, respectively, comprises:

forming first and second hardmask spacers on either side of the gate stack, respectively, wherein the first hardmask spacers are located on the first polysilicon structures and the second hardmask spacers are located on the second polysilicon structures; and

etching the first and second polysilicon structures using the first and second hard mask spacers as a mask to form the first and second select gates, respectively.

The method of aspect 8, wherein the removing the deposited portion of the select gate polysilicon to form the first and second select gates comprises:

self-aligned etching the deposited select gate polysilicon to form the first and second select gates, respectively.

Aspect 13 the method of aspect 8, further comprising:

depositing logic gate polysilicon on a logic gate region of the substrate while depositing the select gate polysilicon on the first and second select gate oxide structures and on the gate stack; and

removing portions of the logic gate polysilicon to form the logic gate while the removing of the deposited portions of the select gate polysilicon to form the first select gate and the second select gate.

Aspect 14 the method of any of aspects 1-7, wherein the forming a first drain region in the substrate on a side of the first select gate opposite the first opening and forming a second drain region in the substrate on a side of the second select gate opposite the first opening comprises:

performing lightly doped drain implantation in the substrate at the side of the first select gate opposite to the first opening and the substrate at the side of the second select gate opposite to the first opening to form a first lightly doped drain region at the side of the first select gate and a second lightly doped drain region at the side of the second select gate;

forming a first drain spacer at a side of the first select gate opposite the first opening, and forming a second drain spacer at a side of the second select gate opposite the first opening;

forming a first source spacer at a side of the first select gate facing the first opening, and forming a second source spacer at a side of the second select gate facing the first opening; and

performing a heavily doped drain implant in the substrate on a side of the first drain spacer opposite the first opening and in the substrate on a side of the second drain spacer opposite the first opening to form a first heavily doped drain region on a side of the first drain spacer and a second heavily doped drain region on a side of the second drain spacer.

Aspect 15 the method of any of aspects 1-7, further comprising:

forming a silicide structure on the first select gate, the first drain region, the source region, the second select gate, and the second drain region.

Aspect 16. a semiconductor device fabricated by the method according to any one of aspects 1-15.

While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed, the indefinite article "a" or "an" does not exclude a plurality, and the term "a plurality" means two or more. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

1. A method of manufacturing a semiconductor device, comprising:

2. The method of claim 1, wherein the forming first and second select gate oxide structures on the first and second regions of the substrate, respectively, and forming first and second tunnel oxide structures on both sides of the gate stack, respectively, comprises:

3. The method of claim 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack:

4. The method of claim 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack:

a sidewall oxide structure is formed on a side of the gate stack.

5. The method of claim 2, further comprising, prior to depositing a second gate oxide film on the first and second regions of the substrate and on the sides and upper surfaces of the gate stack:

6. The method of claim 5, further comprising, prior to said removing portions of said first gate oxide film over said first and second regions of said substrate and over an upper surface of said gate stack:

7. The method of claim 5, further comprising, after depositing a second gate oxide film on the first, second, and high-voltage tube regions of the substrate, and on side and upper surfaces of the gate stack:

performing logic well implantation in the substrate;

forming a logic IO gate oxide structure on the substrate; and

a logic core gate oxide structure is formed on the substrate.

8. The method of any of claims 1-7, wherein the forming a first select gate on a side of the first tunneling oxide structure opposite the gate stack and forming a second select gate on a side of the second tunneling oxide structure opposite the gate stack comprises:

9. The method of claim 8, wherein the removing the deposited portion of the select gate polysilicon to form the first and second select gates comprises:

10. A semiconductor device manufactured by the method according to any one of claims 1 to 9.