CN114678267A - Method for doping ions into semiconductor grid and application thereof - Google Patents

Method for doping ions into semiconductor grid and application thereof Download PDF

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Publication number
CN114678267A
CN114678267A CN202011549390.XA CN202011549390A CN114678267A CN 114678267 A CN114678267 A CN 114678267A CN 202011549390 A CN202011549390 A CN 202011549390A CN 114678267 A CN114678267 A CN 114678267A
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China
Prior art keywords
ion implantation
ion
grid
ions
semiconductor
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CN202011549390.XA
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Chinese (zh)
Inventor
李龙范
刘金彪
杨涛
唐波
贺晓彬
李俊峰
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Priority to CN202011549390.XA priority Critical patent/CN114678267A/en
Publication of CN114678267A publication Critical patent/CN114678267A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention relates to a method for doping ions into a semiconductor grid and application thereof. A method of doping ions into a semiconductor gate, comprising: carrying out plasma doping ion implantation on the semiconductor grid to form an ion-doped semiconductor grid; and then implanting ions into the ion-doped semiconductor grid in situ by taking the co-gas as a gas source. The invention reserves the ion amount doped in the grid to a greater extent, avoids resource waste caused by secondary ion doping, and does not need to add extra equipment such as a high-current ion implanter and the like.

Description

Method for doping ions into semiconductor grid and application thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a method for doping ions into a semiconductor grid and application thereof.
Background
The polysilicon film used as the semiconductor gate is usually deposited without doping, and then needs to be implanted with phosphorus ions, boron ions and other ions to change the resistance or other electrical characteristics of the polysilicon film. It is also necessary to cover the gate electrode with photoresist after ion implantation for subsequent processing steps (e.g., fabrication of ion implantation windows, further ion fabrication, or deposition of other films) that must be followed by removal of the photoresist. In the above process, limited by the decrease of the ion implantation amount with the increase of the implantation depth, the ion concentration of the surface of the polysilicon thin film is high, and the surface with the high ion concentration is more or less removed when the photoresist layer is removed later, thereby resulting in the ion doping insufficiency of the polysilicon.
In order to solve the above problems, in the prior art, ions are usually implanted again after the photoresist is removed to compensate for the ions removed by the photoresist removal, and a high-current ion implanter is required to be used for secondary ion implantation, which inevitably causes resource waste, prolongs the process time, and adds additional equipment.
Disclosure of Invention
The invention mainly aims to provide a method for doping ions into a semiconductor grid, which reserves the ion amount doped in the grid to the greatest extent, avoids resource waste caused by secondary ion doping and does not need to add extra equipment such as a high-current ion implanter and the like.
In order to achieve the above purpose, the invention provides the following technical scheme:
a method of doping ions to a semiconductor gate, comprising:
carrying out plasma doping ion implantation on the semiconductor grid to form an ion-doped semiconductor grid;
and then implanting ions into the ion-doped semiconductor grid in situ by taking the co-gas as a gas source.
According to the method, after plasma doping, the co-gas is added for in-situ ion implantation, and high-concentration ions accumulated on the surface of the grid can be pushed into the deeper grid, so that the amount of doped ions carried away when photoresist is removed is reduced, and the amount of the doped ions in the grid is reserved to a greater extent. In addition, since the ion implantation equipment for doping ions is adopted for implanting the co-gas and is carried out in situ, equipment does not need to be added, so that the production cost is reduced, and the production efficiency is improved.
The companion gas refers to any ionic precursor suitable for implantation into a semiconductor gate without causing destructive effects.
The above method is applicable to any situation where it is desirable to maximize the retention of the ion concentration on the surface of a gate, such as P-type ion implantation or N-type ion implantation of a semiconductor gate in a typical semiconductor device, which is generally applicable to the fabrication of transistors, memories (DRAM, SRAM, etc.), integrated circuit devices (including integrated circuits of different scales), and the like.
Compared with the prior art, the invention achieves the following technical effects:
(1) the ion amount doped on the surface of the grid is reserved to a greater extent;
(2) no additional equipment is required;
(3) the time of the process flow is shortened;
(4) the process cost is reduced.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 shows the variation of the doping ion concentration in the gate with the depth of the gate obtained by different processes.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
In order to maximally preserve the amount of doped ions on the surface of the gate, the present invention provides an improved method, which introduces a combination of plasma doped ion implantation (PLAD IMP) and co-gas ion implantation into the manufacturing process of the semiconductor device, as follows.
Firstly, carrying out plasma doping ion implantation on the semiconductor grid to form an ion-doped semiconductor grid;
and then implanting ions into the ion-doped semiconductor grid in situ by taking the co-gas as a gas source.
According to the method, ion implantation of in-situ co-generation gas is added after the PLAD IMP process, and high-concentration ions accumulated on the surface of the grid are pushed into the deeper grid, so that the amount of doped ions carried away when photoresist is removed is reduced, and the amount of the doped ions in the grid is reserved to the greatest extent.
In addition, since the ion implantation equipment for doping ions is adopted for implanting the co-gas and is carried out in situ, equipment does not need to be added, so that the production cost is reduced, and the production efficiency is improved.
In some embodiments, the ion type of the PLAD IMP doping is arbitrary, depending on the doping purpose, which typically improves surface conductivity or forms PN junctions, and the corresponding ion type includes, but is not limited to, at least one of boron, phosphorous, arsenic, carbon, nitrogen, oxygen, fluorine, silicon, sulfur, hydrogen, helium, germanium, aluminum.
Diffusion sources that may be used to incorporate the ions include, but are not limited to, BF3、B2H6、GeH4、GeF4、He、H2、N2、CH4、CF4、PH3、AsH3、O2、SiH4、SiF4、SF6And at least one of Al.
The source of the co-gas may be the same or different from the source of the dopant ions, including but not limited to, GeH, and4、GeF4、He、H2、N2、CH4、CF4、、O2、SiH4、SiF4、SF6at least one of (1).
In some embodiments, the semiconductor gate is a polysilicon gate, and may be replaced by other good electrical alloys.
In some embodiments, the dose of the co-carrier gas during the implantation is less than or equal to the dose of the plasma doping ion implantation, and the energy is greater than 0.5 KeV.
In some embodiments, the process parameters of the plasma doping ion implantation are: BF (BF) generator3,3.0KeV,2.0E16ions/cm2And the concentration of the polycrystalline dopant after annealing is more than 1E20/cm3
In some embodiments, the process parameters for implanting ions into the ion-doped semiconductor gate in situ are: BF (BF) generator3,3.0KeV,2.0E16ions/cm2The process pressure is 1 mtorr-10 torr, and the substrate temperature is-100 ℃ to 450 ℃.
Since the semiconductor material needs to be doped to obtain good electrical characteristics when used as a gate, the above embodiments of the present invention are mainly used in the following processes: p-type ion implantation or N-type ion implantation of a semiconductor gate in a semiconductor device. Accordingly, devices fabricated using these processes include, but are not limited to, transistors, memories, integrated circuit devices, and the like.
The invention also takes a P-type doped field effect transistor (MOS) grid as an example, and compares the distribution of doped ions in the polysilicon grid obtained by different processes, as follows.
Comparative example: with B2H6As a gas source, PLAD IMP was performed, process parameters: 3.0KeV, 2.0E16ions/cm2
The invention comprises the following steps:
first step, with B2H6As a gas source, PLAD IMP was performed, process parameters: 2.5KV, 3.5E16/cm2
Second, in situ with Ge F4Ion implantation is carried out for the co-gas, and the process parameters are as follows: the energy is 0.5-15 KeV, and the dosage is 1E 14-5E 16.
The distributions of dopant ions in the gate obtained by the comparative example and the various co-gases of the present invention (the present invention considers the improvement under different implanted Ge energies) are shown in fig. 1, and the results show that: the gradient of the concentration of the doped B ions in the comparative example is larger along with the increase of the depth of the grid electrode, so that the total doping amount of the accumulated B ions is smaller; after the ion implantation of the co-gas of the invention, the total doping amount of the B ions in the grid electrode is increased, which shows that the invention can reserve the ion doping amount in the grid electrode to the maximum extent. As can also be clearly seen from fig. 1: the higher the energy, the greater the bombardment of the substrate, and the higher the residual dose of B. In addition, the effect is better when the atomic weight is larger, for example, the effect of Ge is better than that of other atoms, and the gas used may be GeH4Or GeF4
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A method of doping ions into a semiconductor gate, comprising:
carrying out plasma doping ion implantation on the semiconductor grid to form an ion-doped semiconductor grid;
and then implanting ions into the ion-doped semiconductor grid in situ by taking the co-gas as a gas source.
2. The method of claim 1, wherein the plasma doping ion implantation is performed with at least one of boron, phosphorus, arsenic, carbon, nitrogen, oxygen, fluorine, silicon, sulfur, hydrogen, helium, germanium, and aluminum.
3. The method of claim 1, wherein the co-partner gas is GeH4、GeF4、He、H2、N2、CH4、CF4、O2、SiH4、SiF4、SF6At least one of (1).
4. The method according to any of claims 1-3, wherein the diffusion source used for plasma doping ion implantation is BF3、B2H6、GeH4、GeF4、He、H2、N2、CH4、CF4、PH3、AsH3、O2、SiH4、SiF4、SF6And at least one of Al.
5. The method of claim 1, wherein the semiconductor gate is a polysilicon gate.
6. The method of claim 1, wherein the co-carrier gas is implanted at a dose less than or equal to the dose of the plasma dopant ion implantation and at an energy greater than 0.5 KeV.
7. The method of claim 1, wherein the plasma doping ion implantation process parameters are: BF (BF) generator3,3.0KeV,2.0E16ions/cm2And the concentration of the polycrystalline dopant after annealing is more than 1E20/cm3
8. The method according to any one of claims 1, 6 and 7, wherein the process parameters for implanting ions into the ion-doped semiconductor gate in situ are as follows: BF3,3.0KeV,2.0E16ions/cm2The process pressure is 1 mtorr-10 torr, and the substrate temperature is-100 ℃ to 450 ℃.
9. The method of any one of claims 1-8 used for P-type ion implantation or N-type ion implantation of a semiconductor gate in a semiconductor device.
10. Use of the method of any of claims 1-8 for the fabrication of transistors, memories, integrated circuit devices.
CN202011549390.XA 2020-12-24 2020-12-24 Method for doping ions into semiconductor grid and application thereof Pending CN114678267A (en)

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Application Number Priority Date Filing Date Title
CN202011549390.XA CN114678267A (en) 2020-12-24 2020-12-24 Method for doping ions into semiconductor grid and application thereof

Publications (1)

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CN114678267A true CN114678267A (en) 2022-06-28

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