CN114546029B - Control chip, MCU chip, MPU chip and DSP chip - Google Patents
Control chip, MCU chip, MPU chip and DSP chip Download PDFInfo
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- CN114546029B CN114546029B CN202210171495.9A CN202210171495A CN114546029B CN 114546029 B CN114546029 B CN 114546029B CN 202210171495 A CN202210171495 A CN 202210171495A CN 114546029 B CN114546029 B CN 114546029B
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Abstract
The application discloses a control chip, an MCU chip, an MPU chip and a DSP chip, wherein the control chip comprises a processor, a timer and a GPIO interface, the timer comprises a filter, and the filter comprises an input interface for receiving edge signals; the processor is used for presetting the output jump and the interrupt signal generated by the filter after N events, and is also used for executing interrupt processing after receiving the interrupt signal so as to enable the output signal of the GPIO interface to generate GPIO overturn. The filter of this application can produce interrupt signal based on N incident of border signal, and the treater can produce GPIO upset based on interrupt signal, and then can calculate the sampling of the filter of timer based on the border signal of N incident and the time and the corresponding formula of GPIO upset, makes the timing or the timing of timer more accurate.
Description
Technical Field
The application relates to the technical field of timers, in particular to a control chip, an MCU chip, an MPU chip and a DSP chip.
Background
The timer is an element used for delay and performs the next step after a precise time. The functions of timing, delay waiting, etc. are realized by different programs or circuits.
Generally, the input channel of the timer has a filtering unit (the filtering unit belongs to the internal structure of the timer) respectively located on each input channel and the external trigger input channel for filtering high-frequency interference on the input signal.
In practice, the digital filter is an event counter that records an output transition after N events. Specifically, when the filter continuously samples to N times of effective levels, the effective levels are output; otherwise, when the filter does not continuously sample to N times of effective levels, counting is started from 0 again, and the output always keeps the effective level output last time. For example, if the last output of the filter is high, and N-1 high levels are continuously sampled this time, but the nth level is low, the filter still keeps the high level of the last output, and starts counting again, records 1 low level, and if N-1 sampled after that is also low, then the filter outputs low level, and then a falling edge appears at the filter output. It can be seen that N events refer to the consecutive sampling of N active levels, and that "generating an output transition" refers to outputting the level N consecutive times.
The sampling frequency and the number of samples of the filter can be selected by the user program as desired. However, in actual use, due to the influence of various factors such as environment, the actual sampling rate of the timer filter and the theoretical value of the configuration are not exactly the same, and there may be an error.
Disclosure of Invention
In order to overcome the problems in the prior art, a main object of the present application is to provide a control chip capable of accurately calculating an actual sampling frequency of a timer filter.
In order to achieve the above purpose, the following technical solutions are specifically adopted in the present application:
the application provides a control chip, which comprises a processor, a timer and a GPIO interface, wherein the timer comprises a filter;
the filter comprises an input interface for receiving an edge signal;
the processor is used for presetting the filter to generate output jump after N events and generating an interrupt signal, and is also used for executing interrupt processing after receiving the interrupt signal so as to enable the output signal of the GPIO interface to generate GPIO overturn;
the filter generates a first output jump and generates a first interrupt signal after the input interface receives N1 events of the edge signal, and the processor receives the first interrupt signal to enable the GPIO interface to generate a first GPIO overturn; the filter generates second output jump and generates a second interrupt signal after the input interface receives N2 events of the edge signal, and the processor receives the second interrupt signal to enable the GPIO interface to generate second GPIO overturn;
calculating the sampling rate of a filter of the timer based on the time t1 from the edge signal of N1 event to the first GPIO overturn, the time t2 from the edge signal of N2 event to the second GPIO overturn and the formula f = 1/((t 2-t 1)/(N2-N1)), wherein N1 and N2 are positive integers, and N2 is more than N1.
In some embodiments, the edge signals include a rising edge signal and a falling edge signal. .
In some embodiments, the N events are consecutive samples of the filter to N active levels after the input interface receives an edge signal.
In some embodiments, the GPIO toggling comprises a GPIO signal toggling from a low output to a high output or from a high output to a low output.
In some embodiments, the processor includes a preset program and an interrupt handler, and when executing the preset program, the processor controls the filter to generate an output jump after N events and generate an interrupt signal; and the processor executes the interrupt processing program after receiving the interrupt signal, and controls the output signal of the GPIO interface to generate GPIO overturn.
In some embodiments, the processor further comprises a sampling rate calculation program, the processor, when executing the sampling rate calculation program, timing the time t1 of the edge signal of N1 events to the first GPIO flip and the time t2 of the edge signal of N2 events to the second GPIO flip, and calculating the sampling rate of the filter of the timer according to the formula f = 1/((t 2-t 1)/(N2-N1)).
In some embodiments, the processor is a CPU.
In some embodiments, the input interface of the filter and the GPIO interface are coupled to a signal collector that records the waveforms of the N1 event edge signals, the N2 event edge signals, and the first GPIO flip, the second GPIO flip of the GPIO interface for the input interface of the filter to time t1 for the N1 event edge signals to the first GPIO flip and t2 for the N2 event edge signals to the second GPIO flip.
Correspondingly, the application also discloses an MCU chip which is the control chip in any of the above embodiments.
Correspondingly, the application also discloses an MPU chip, which is the control chip described in any one of the above embodiments.
Correspondingly, the application also discloses a DSP chip which is the control chip in any of the above embodiments.
Compared with the prior art, the control chip comprises a processor, a timer and a GPIO (general purpose input/output) interface, wherein the timer comprises a filter, the filter comprises an input interface, and the input interface is used for receiving edge signals; the processor is used for presetting output jump generated by the filter after N events and generating an interrupt signal, and is also used for executing interrupt processing after receiving the interrupt signal so as to enable the output signal of the GPIO interface to generate GPIO overturn; when the sampling rate of the filter is calculated, the filter generates a first output jump and generates a first interrupt signal after the input interface receives N1 events of the edge signal, and the processor receives the first interrupt signal to enable the GPIO interface to generate a first GPIO overturn; the filter generates second output jump and generates a second interrupt signal after the input interface receives N2 events of the edge signal, the processor receives the second interrupt signal to enable the GPIO interface to generate second GPIO overturn, so that the sampling of the filter of the timer can be calculated based on the time t1 from the edge signal of the N1 event to the first GPIO overturn, the time t2 from the edge signal of the N2 event to the second GPIO overturn and the formula f = 1/((t 2-t 1)/(N2-N1)), and the timing or the timing of the timer is more accurate.
Drawings
Fig. 1 is a flowchart of a method for calculating a sampling rate of a timer filter according to an embodiment of the present application.
Fig. 2 is a waveform diagram of an edge signal input by the embodiment of the present application when the edge signal is a rising edge signal.
Fig. 3 is a waveform diagram of an edge signal input by the embodiment of the present application when the edge signal is a falling edge signal.
Fig. 4 is a block diagram of a control device according to an embodiment of the present application.
Fig. 5 is a block diagram of a control device according to another embodiment of the present application.
Fig. 6 is a block diagram of a control device according to another embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
In the description of the present application, unless explicitly stated or limited otherwise, the terms "first", "second", and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance; the term "plurality" means two or more unless otherwise specified or indicated; the terms "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, integrally connected, or electrically connected; may be directly connected or indirectly connected through an intermediate. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Referring to fig. 1, an embodiment of the present application discloses a method for calculating a sampling rate of a timer filter, the method including:
and S11, the preset timer filter generates output jump after N1 events and generates an interrupt signal when the output jump is generated.
Wherein the preset can be defined by a processor program, the N1 events are continuously sampled to N1 active levels, and N1 is a positive integer. An output transition refers to the level at which this output occurs N1 times in succession.
For example, it may be preset that when the timer filter samples 8 times of active low levels continuously, the timer filter outputs low levels, otherwise, counting from 0 is started, and the output keeps the active level output last time.
And S12, inputting an edge signal into the timer filter, enabling the timer filter to generate a first output jump after N1 events, and generating a first interrupt signal immediately.
The timer filter may be input with edge signals through the signal generator, and the edge signals include a rising edge signal and a falling edge signal. Taking the input signal as the rising edge signal as an example, when the timer filter continuously samples to N1 times of effective high levels, the output jumps from the original low level to the high level, and then generates an interrupt signal. The step of generating the interrupt signal immediately after the level jump is generated can be set by a processor program.
And S13, the processor receives the first interrupt signal and executes interrupt processing after receiving the first interrupt signal to generate first GPIO (general purpose input/output) turnover.
The GPIO overturning means that GPIO signals are changed from low-level output to high-level output or from high-level output to low-level output in a jumping mode.
And S14, counting the time t1 from the edge occurrence of the edge signal to the generation of the first GPIO overturn.
And S15, the preset timer filter generates output jump after N2 events and generates an interrupt signal when the output jump is generated.
Wherein the preset can be defined by a processor program, the N2 events are continuously sampled to N2 active levels, and N2 is a positive integer, and N2 > N1.
For example, it may be preset that when the timer filter samples to 10 active low levels continuously, the timer filter outputs a low level, otherwise, counting from 0 again, the output will keep the active level output last time.
And S16, inputting the edge signal into the timer filter, so that the timer filter generates a second output jump after N2 events, and then generating a second interrupt signal.
The step of inputting the edge signal to the timer filter through the signal generator, and generating the level jump and then generating the interrupt signal can be set by a processor program.
And S17, the processor receives the second interrupt signal and executes interrupt processing after receiving the second interrupt signal to generate second GPIO (general purpose input/output) turnover.
And S18, counting the time t2 from the edge occurrence of the edge signal to the generation of the second GPIO inversion.
Step S19, the actual sampling rate of the timer filter is calculated according to the formula f = 1/((t 2-t 1)/(N2-N1)).
Wherein f is the actual sampling frequency of the timer filter, t1 is the time required from the edge occurrence of the edge signal to the generation of the first GPIO inversion, t2 is the time required from the edge occurrence of the edge signal to the generation of the second GPIO inversion, and the statistics of t1 and t2 can be executed by the signal acquisition device or the processor program.
In an embodiment, taking the example of inputting a rising edge signal to the timer filter, please refer to fig. 2, when the number of high levels continuously sampled by the timer filter does not reach N1 after the rising edge occurs, the timer filter still outputs the original level (low level) at this time; when the number of the high levels continuously sampled by the timer filter reaches N1, the timer filter jumps from the original output low level to the output high level, and at the moment, the timer filter generates an interrupt signal. The time from the rising edge to the generation of the interrupt signal can be referred to as the filtering time t1', and in the time t1', the time t1' cannot be counted because only the waveform at the starting time (the rising edge occurs) can be captured, but the waveform at the end time (the interrupt signal is generated or the filter output jumps) cannot be captured.
The timer filter generates an interrupt signal and outputs the interrupt signal to the processor, and the processor receives the interrupt signal and then executes an interrupt function, so that GPIO (general purpose input/output) overturning is realized. The time from the generation of the interrupt signal to the completion of the GPIO inversion is referred to as an interrupt processing time t1", and in the time t1", the time t1 "cannot be counted because only the waveform at the end point time (GPIO inversion) can be captured, but the waveform at the start point time (generation of the interrupt signal or transition of the filter output) cannot be captured. However, since the waveform of the rising edge and the GPIO inversion can be captured on the waveform diagram, the time t1 required from the rising edge to the GPIO inversion can be obtained statistically, and it is known that t1= t1' + t1".
Similarly, when the number of the high levels continuously sampled by the timer filter does not reach N2 after the rising edge occurs, the timer filter still outputs the original level (low level); when the number of the high levels continuously sampled by the timer filter reaches N2, the timer filter jumps from the original output low level to the output high level, and at the moment, the timer filter generates an interrupt signal. The time from the rising edge to the generation of the interrupt signal can be referred to as the filtering time t2', and in the time t2', the time t2' cannot be counted because only the waveform at the start time (the rising edge occurs) can be captured, but the waveform at the end time (the interrupt signal is generated or the filter output jumps) cannot be captured.
The timer filter generates an interrupt signal and outputs the interrupt signal to the processor, and the processor executes an interrupt function after receiving the interrupt signal, so that GPIO (general purpose input/output) overturning is realized. The time from the generation of the interrupt signal to the completion of the GPIO inversion is referred to as an interrupt processing time t2", and in this time t2", the time of t2 "cannot be obtained uniformly because only the waveform at the end point time (output inversion) can be captured, but the waveform at the start point time (generation of the interrupt signal or transition of the filter output) cannot be captured. However, since the waveform of the rising edge and the GPIO inversion can be captured on the waveform diagram, the time t2 required for timing the GPIO inversion from the rising edge to the GPIO occurrence can be obtained statistically, and it is known that t2= t2' + t2".
Finally, the actual sampling frequency of the timer filter can be calculated by the formula f = 1/((t 2-t 1)/(N2-N1)). Since the interrupt handling time is equal on the same processor, i.e. t1"= t2". Then t2-t1= t2'-t1' indicates the filtering time difference and also the time difference between recording N2 levels and recording N1 levels, so ((t 2-t 1)/(N2-N1)) indicates the time taken to record one level, i.e. 1/((t 2-t 1)/(N2-N1)) indicates the actual sampling frequency of the timer filter.
In another embodiment, taking the falling edge signal input to the timer filter as an example, as shown in fig. 3, when the number of low levels continuously sampled by the timer filter does not reach N1 after the falling edge occurs, the timer filter still outputs the original level (high level) at this time; when the number of the low levels continuously sampled by the timer filter reaches N1, the timer filter jumps from the original output high level to the output low level, and at the moment, the timer filter generates an interrupt signal. The time from the occurrence of the falling edge to the generation of the interrupt signal may be referred to as a filtering time t1', and in the time t1', the time t1' cannot be obtained statistically because only the waveform at the start time (the falling edge arrives) can be captured, but the waveform at the end time (the generation of the interrupt signal or the jump in the output of the filter) cannot be captured.
The timer generates an interrupt signal and outputs the interrupt signal to the processor, and the processor executes an interrupt function after receiving the interrupt signal, so that GPIO (general purpose input/output) overturning is realized. The time from the generation of the interrupt signal to the completion of the GPIO inversion may be referred to as an interrupt processing time t1", and in this time t1", the time of t1 "cannot be counted because only the waveform at the end point time (output inversion) can be captured, but the waveform at the start point time (generation of the interrupt signal or output transition of the filter) cannot be captured. However, the time t1 required from the falling edge to the GPIO inversion can be obtained statistically, and it is known from the above that t1= t1' + t1".
Similarly, when the number of the low levels continuously sampled by the timer filter does not reach N2 after the falling edge occurs, the timer filter still outputs the original level (high level); when the number of the low levels sampled by the timer filter reaches N2, the timer filter jumps from the original output high level to the low level, and at the moment, the timer filter generates an interrupt signal. The time from the occurrence of the falling edge to the generation of the interrupt signal may be referred to as a filtering time t2', and in the time t2', the time t2' cannot be counted because only the waveform at the start time (the falling edge arrives) can be captured, but the waveform at the end time (the generation of the interrupt signal or the jump in the output of the filter) cannot be captured.
The timer filter generates an interrupt signal and outputs the interrupt signal to the processor, and the processor receives the interrupt signal and then executes an interrupt function, so that GPIO (general purpose input/output) overturning is realized. The time from the generation of the interrupt signal to the completion of the GPIO inversion is referred to as an interrupt processing time t2", and in this time t2", the time of t2 "cannot be obtained uniformly because only the waveform at the end point time (output inversion) can be captured, but the waveform at the start point time (generation of the interrupt signal or transition of the filter output) cannot be captured. However, since the waveforms of the falling edge and the GPIO inversion can be captured on the waveform diagram, the time t2 required from the falling edge to the GPIO inversion is counted. It can be statistically found that t2= t2' + t2 "as described above.
Finally, the actual sampling frequency of the timer filter can be calculated by the formula f = 1/((t 2-t 1)/(N2-N1)) because the interrupt handling time is equal on the same processor, i.e. t1"= t2". Then t2-t1= t2'-t1' indicates the filtering time difference and also the time difference between recording N2 levels and recording N1 levels, so ((t 2-t 1)/(N2-N1)) indicates the time taken to record one level, so 1/((t 2-t 1)/(N2-N1)) indicates the actual sampling frequency of the timer filter.
In one embodiment, the present application further discloses a control device, which is shown in fig. 4 and includes a timer filter 200 and a processor 300. The timer filter 200 is configured to receive an edge signal (a rising edge signal or a falling edge signal) from the signal generator 100, and is preset to generate an output transition after N events, and then generate an interrupt signal, where the N events are continuously sampled to N valid levels; the processor 300 includes a timer filter presetting program 301, an interrupt handling program 302, and a sampling rate calculation program 303; the timer filter presetting program 301 is used for presetting the timer filter to generate output jump after N (N1, N2, and) events and then generating an interrupt signal after the output jump; the interrupt handler 302 is configured to execute an interrupt function after receiving the interrupt signal, so as to turn over the GPIO; the sampling rate calculation program 303 is used for calculating the time t (t 1, t2, t) from the edge of the edge signal to the GPIO overturn, and calculating the actual sampling rate of the timer filter by using the formula 1/((t 2-t 1)/(N2-N1)).
Specifically, timer filter 200 is preset by a preset program 301 of processor 300 to generate a first output transition after N1 events, and then generate a first interrupt signal; generating a second output jump after the N2 events, and immediately following the second interrupt signal; wherein, N1 events are continuously sampled to N1 effective levels, N2 events are continuously sampled to N2 effective levels, N1 and N2 are positive integers, and N2 is more than N1. The signal generator 100 inputs edge signals (including a rising edge signal and a falling edge signal) to the timer filter 200; the timer filter 200 generates a first output transition after N1 events, and then generates a first interrupt signal; a second output transition is generated after N2 events, followed by a second interrupt signal. After receiving the first interrupt signal or the second interrupt signal, the processor 300 executes an interrupt handler 302, that is, triggers an interrupt function to correspondingly generate a first GPIO inversion and a second GPIO inversion, respectively; the processor 300 further executes a sampling rate calculation routine 303 to count the time t1 required from the edge occurrence of the edge signal to the generation of the first GPIO flip and the time t2 required from the edge occurrence of the edge signal to the generation of the second GPIO flip, and then calculate the actual sampling rate of the timer filter according to the formula f = 1/((t 2-t 1)/(N2-N1)).
In another embodiment, the present application further discloses a control device, please refer to fig. 5, which includes a timer filter 200, a processor 300, a GPIO interface 400 and a signal collector 500. The timer filter 200 includes an input interface for receiving the edge signal from the signal generator 100 and is preset to generate an output transition after N events, wherein N events are successively sampled to N valid levels. The processor 300 includes a timer filter presetting program 301 and an interrupt handling program 302; the timer filter presetting program 301 is used for presetting the timer filter to generate output jump after N (N1, N2, N) events and then generating an interrupt signal after the output jump; the interrupt handler 302 is configured to execute an interrupt function after receiving the interrupt signal, so as to flip the output signal on the GPIO interface 400. The signal collector 500 is coupled to the timer filter input interface and the GPIO interface 400, and is configured to record waveforms of the edge signal and the GPIO output signal, so as to time t (t 1, t2, t,) required by the edge signal from edge occurrence to GPIO inversion. Finally, the actual sampling rate of the timer filter is calculated according to the formula f = 1/((t 2-t 1)/(N2-N1)).
Specifically, the timer filter 200 is preset by the preset program 301 of the processor to generate a first output transition after N1 events, and then generate a first interrupt signal, and generate a second output transition after N2 events, and then generate a second interrupt signal; wherein, N1 events are continuously sampled to N1 effective levels, N2 events are continuously sampled to N2 effective levels, N1 and N2 are positive integers, and N2 is more than N1. The signal generator 100 inputs interface input edge signals (including a rising edge signal and a falling edge signal) to the timer filter; the timer filter 200 generates a first output transition after N1 events, and then generates a first interrupt signal; a second output transition is generated after N2 events, followed by a second interrupt signal. After receiving the first interrupt signal or the second interrupt signal, the processor 300 executes an interrupt handler 302, that is, triggers an interrupt function to correspondingly generate a first GPIO inversion and a second GPIO inversion, respectively; the signal collector 500 records the waveform of the edge signal on the input interface 201 of the timer filter and the waveform of the output signal on the GPIO interface, and times t1 required from the edge signal edge to the first GPIO overturn and t2 required from the edge signal edge to the second GPIO overturn. And finally, calculating the actual sampling rate of the timer filter according to the formula f = 1/((t 2-t 1)/(N2-N1)).
The processor may be a Central Processing Unit (CPU).
As shown in fig. 6, the timer filter 200, the processor 300, and the GPIO interface 400 may be integrated and packaged on a chip. The chip may be an MCU (Micro Control Unit) chip, an MPU (Micro Processor Unit) chip, or a DSP (Digital Signal Processing) chip.
Wherein, the signal collector 500 can be configured as an oscilloscope.
In the present embodiment, the actual sampling frequency of the timer filter is calculated by the calculator according to the formula f = 1/((t 2-t 1)/(N2-N1)). It will be appreciated that in other embodiments, the actual sampling frequency of the timer filter may also be calculated manually.
The above description is only for the preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application should be covered within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. The control chip is characterized by comprising a processor, a timer and a GPIO interface, wherein the timer comprises a filter;
the filter comprises an input interface for receiving an edge signal;
the processor is used for presetting the filter to generate output jump after N events and generating an interrupt signal, and is also used for executing interrupt processing after receiving the interrupt signal so as to enable the output signal of the GPIO interface to generate GPIO overturn;
the filter generates first output jump and generates a first interrupt signal after the input interface receives N1 events of an edge signal, and the processor receives the first interrupt signal to enable the GPIO interface to generate first GPIO overturn; the filter generates second output jump and generates a second interrupt signal after the input interface receives N2 events of the edge signal, and the processor receives the second interrupt signal to enable the GPIO interface to generate second GPIO overturn;
calculating the sampling rate of a filter of the timer based on the time t1 from the edge signal of N1 events to the first GPIO overturn, the time t2 from the edge signal of N2 events to the second GPIO overturn and a formula f = 1/((t 2-t 1)/(N2-N1)), wherein N1 and N2 are positive integers, and N2 is greater than N1;
the edge signal is a rising edge signal or a falling edge signal;
the N events are consecutive samples of the filter to N active levels after the filter receives an edge signal at the input interface.
2. The control chip of claim 1, wherein the GPIO toggling comprises a GPIO signal toggling from a low output level to a high output level or from a high output level to a low output level.
3. The control chip of claim 1, wherein the processor includes a preset program and an interrupt handler, and when the preset program is executed, the processor controls the filter to generate an output jump and generate an interrupt signal after N events; and the processor executes the interrupt processing program after receiving the interrupt signal, and controls the output signal of the GPIO interface to generate GPIO turnover.
4. The control chip of claim 1, wherein the processor further comprises a sampling rate calculation program, and when executing the sampling rate calculation program, the processor clocks time t1 of the edge signal of N1 events to the first GPIO flip and time t2 of the edge signal of N2 events to the second GPIO flip, and calculates the sampling rate of the filter of the timer according to the formula f = 1/((t 2-t 1)/(N2-N1)).
5. The control chip according to any one of claims 1 to 4, wherein the processor is a CPU.
6. The control chip of claim 1, wherein the input interface of the filter and the GPIO interface are coupled to a signal collector, and the signal collector records the edge signals of N1 events, the edge signals of N2 events, and the waveforms of the first GPIO flip and the second GPIO flip of the GPIO interface of the input interface of the filter to time t1 from the edge signals of N1 events to the first GPIO flip and t2 from the edge signals of N2 events to the second GPIO flip.
7. An MCU chip, characterized in that the MCU chip is the control chip of any one of claims 1 to 6.
8. An MPU chip, wherein the MPU chip is the control chip according to any one of claims 1 to 6.
9. A DSP chip, characterized in that, the DSP chip is the control chip of any one of claims 1 to 6.
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| CN113126530A (en) | 2021-07-16 |
| CN113126530B (en) | 2022-03-18 |
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