CN114528034A

CN114528034A - Loading circuit, method and system

Info

Publication number: CN114528034A
Application number: CN202011210215.8A
Authority: CN
Inventors: 谢建; 吴敬东; 梅优良
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-11-03
Filing date: 2020-11-03
Publication date: 2022-05-24

Abstract

The application provides a loading circuit, a loading method and a loading system, and belongs to the technical field of semiconductors. In the solution provided by the present application, the loading circuit includes a JTAG circuit and a channel selection circuit, the channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect the SPI flash memory. Because each pin of this JTAG circuit can correspond with each pin of this first SPI to be connected, and this JTAG circuit can control this first SPI and third SPI to switch on, consequently realized JTAG interface and SPI's communication. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted. Therefore, the out-of-band upgrading of the firmware stored in the SPI flash memory through the JTAG interface is realized, and the flexibility of firmware upgrading is improved.

Description

Loading circuit, method and system

Technical Field

The present application relates to the field of semiconductor technologies, and in particular, to a loading circuit, a loading method, and a loading system.

Background

The processor board card includes a Printed Circuit Board (PCB), a processor disposed on the PCB, and a Serial Peripheral Interface (SPI) flash memory (flash) connected to the processor. The SPI flash is used for storing firmware, and the processor is used for running the firmware.

In the related art, the firmware in the SPI flash is generally upgraded in an in-band upgrade manner, that is, the processor directly loads data to the SPI flash, thereby upgrading the firmware. However, if the in-band upgrade method is abnormal, the firmware upgrade needs to be performed by using the out-of-band upgrade method. For a processor board card supporting SPI, when out-of-band upgrading is performed, a Baseboard Management Controller (BMC) may be connected to the SPI flash through the SPI of the processor board card, and the BMC loads data to the SPI flash through the SPI, thereby upgrading firmware in the SPI flash.

However, currently, the main processor board cards are all Peripheral Component Interconnect Express (PCIE) boards or open computing project accelerator modules (OAM), and hardware interfaces of the PCIE board cards and the OAM do not include an external SPI, which cannot support out-of-band upgrade through the SPI, and thus the flexibility is poor.

Disclosure of Invention

The application provides a loading circuit, a loading method and a loading system, which can solve the problem of poor flexibility when a processor board card is upgraded out of band.

In one aspect, a loading circuit is provided, the loading circuit comprising: a Joint Test Action Group (JTAG) circuit, a flash memory controller (SFC), and a channel selection circuit; the channel selection circuit is provided with a first SPI, a second SPI and a third SPI, the second SPI is connected with the SFC, and the third SPI is used for connecting an SPI flash memory; the JTAG circuit is used for controlling the first SPI and the third SPI of the channel selection circuit to be conducted, or controlling the second SPI and the third SPI to be conducted; a Test Clock (TCK) pin of the JTAG circuit is connected to a Serial Clock (SCLK) pin in the first SPI, a Test Data Input (TDI) pin of the JTAG circuit is connected to a Master Output Slave Input (MOSI) pin in the first SPI, a Test Data Output (TDO) pin of the JTAG circuit is connected to a Master Input Slave Output (MISO) pin in the first SPI, and a Test Access Port (TAP) controller of the JTAG circuit is connected to a Chip Select (CS) pin in the first SPI; wherein a level of a target CS signal supplied to the CS pin jumps from an inactive level to an active level after the TAP controller is in a Data Register (DR) state.

The application provides a passageway selection circuit among loading circuit has first SPI, second SPI and third SPI, and this third SPI is used for connecting SPI flash memory. Because each pin of the JTAG circuit in the loading circuit can be correspondingly connected with each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to be conducted, the communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted. Therefore, the out-of-band upgrading of the firmware stored in the SPI flash memory through the JTAG interface is realized, and the flexibility of firmware upgrading is improved.

Optionally, the JTAG circuit is configured to control the first SPI and the third SPI to be turned on according to a received load instruction.

Wherein, the load instruction can be issued by the controller. When the JTAG circuit controls the first SPI and the third SPI to be conducted, the SPI flash memory and the loading circuit are gated, and at the moment, the controller can carry out-of-band upgrading on the firmware stored in the SPI flash memory through the loading circuit.

Optionally, if the load instruction is a parallel load instruction, the JTAG circuit is further configured to communicate the TDI pin with the TDO pin according to the load instruction.

The TDI pin is communicated with the TDO pin, so that the loading circuit can transparently transmit the TDI signal to the next loading circuit connected in series while loading data to the SPI flash memory, and the SPI flash memory connected with a plurality of loading circuits connected in series can be loaded in parallel.

Optionally, at a first target jump edge of the TCK pin after the TAP controller is in the DR-shifted state, a level of a target CS signal provided to the CS pin is jumped from an inactive level to an active level; at the first target jump edge of the TCK pin after the TAP controller finishes shifting the DR state, the level of a target CS signal provided for the CS pin is changed from an active level jump to an inactive level; wherein, the target jump edge is a rising edge or a falling edge.

The JTAG circuit can read and write data when the TAP controller is in the stage of shift DR state, and the first SPI can read and write data when the target CS signal is in active level. For a scenario where the controller is connected to only one load circuit, there is no delay in the TDI signal transmitted by the controller to the TDI pin of the load circuit, and there is no delay in the TDO signal transmitted by the TDO pin of the load circuit to the controller. Thus, in this scenario, the loading circuit may determine the stage in which the target CS signal is at the active level directly with reference to the stage in which the TAP controller is in the shift DR state.

Optionally, the JTAG circuitry is to provide the target CS signal to the CS pin; or, the loading circuit further comprises a timing conversion circuit, and the TAP controller is connected with the CS pin through the timing conversion circuit; the timing conversion circuit is configured to provide the target CS signal to the CS pin according to a state of the TAP controller and a level of the TCK pin.

In the scheme provided by the application, the target CS signal can be provided by a JTAG circuit and also can be provided by a time sequence conversion circuit, so that the flexibility of providing the target CS signal for the CS pin is effectively improved.

Optionally, the loading circuit may further include a timing conversion circuit, and the TAP controller is connected to the CS pin through the timing conversion circuit; the JTAG circuit is used for providing an initial CS signal to the time sequence conversion circuit, wherein, at a first target jump edge of the TCK pin after the TAP controller is in a shift DR state, the level of the initial CS signal is adjusted from an invalid level to an valid level, at a first target jump edge of the TCK pin after the TAP controller finishes the shift DR state, the level of the initial CS signal is adjusted from the valid level to the invalid level, and the target jump edge is a rising edge or a falling edge; the time sequence conversion circuit is used for carrying out time sequence conversion on the initial CS signal to obtain a target CS signal and providing the target CS signal for the CS pin; wherein, the time when the level of the target CS signal jumps from the invalid level to the valid level is delayed by n clock cycles relative to the time when the level of the initial CS signal jumps from the invalid level to the valid level; and/or the time when the level of the target CS signal jumps from the active level to the inactive level is m clock cycles ahead of the time when the level of the initial CS signal jumps from the active level to the inactive level; n and m are both positive integers.

For a scenario where the load circuit is preceded by n other load circuits in series, there may be a delay in the TDI signal that the controller transmits to the TDI pin of the load circuit. For a scenario where m other load circuits are connected in series after the load circuit, there is a delay in the TDO signal transmitted from the TDO pin of the load circuit to the controller. Therefore, in the solution provided in this application, the timing conversion circuit may delay a skip edge of the initial CS signal by n clock cycles and/or advance by m clock cycles, so as to enable synchronization between the data signal and the control signal received by the first SPI.

Optionally, the loading circuit further includes a first configuration register connected to the timing conversion circuit, and a first value used for indicating n is configured in the first configuration register; the time sequence conversion circuit is used for delaying the time when the initial CS signal jumps from the invalid level to the valid level by n clock cycles according to the first numerical value.

The first value may be configured by the controller, that is, the controller may configure the first configuration register in the loading circuit to be loaded according to a position of the loading circuit to be loaded in the multiple loading circuits connected in series.

Optionally, the first configuration register is further configured with a second value for indicating a duration of the target CS signal at the active level; the time sequence conversion circuit is used for advancing the time when the initial CS signal jumps from the active level to the inactive level by m clock cycles according to the second value.

The second value may also be configured by the controller, that is, the controller may configure the first configuration register in the loading circuit to be loaded according to the position of the loading circuit to be loaded in the multiple loading circuits connected in series.

Optionally, the TDI pin is connected to the MOSI pin in the first SPI through the timing conversion circuit; the timing conversion circuit is further used for delaying the TDI signal provided by the TDI pin by i clock cycles and providing the delayed TDI signal to the MOSI pin, wherein i is a positive integer not larger than n.

In the scheme provided by the application, the controller can load x loading circuits connected in series in parallel, wherein x is an integer not greater than n + 1. In this scenario, the x-i th load circuit may delay the TDI signal provided by its TDI pin by i clock cycles before providing it to the MOSI pin, so that the x load circuits may load data to the SPI flash memory at the same time. Wherein i is a positive integer less than x.

Optionally, the loading circuit further includes a second configuration register connected to the timing conversion circuit, and a third value used for indicating the i is configured in the second configuration register; the timing conversion circuit is used for delaying the TDI signal provided by the TDI pin by i clock cycles and providing the delayed TDI signal to the MOSI pin according to the third value.

The third value may also be configured by the controller, that is, the controller may configure the second configuration register in the load circuit to be loaded according to the position of the load circuit to be loaded in the plurality of load circuits connected in series and the number of load circuits loaded in parallel.

In another aspect, a loading method is provided, which is applied to the loading circuit provided in the above aspect; the method comprises the following steps: conducting a first SPI and a third SPI of a channel selection circuit in the loading circuit; the level of a target CS signal supplied to the CS pin is adjusted from an inactive level to an active level after the TAP controller is in a shifted DR state in the loading circuit.

Optionally, turning on the first SPI and the third SPI of the channel selection circuit in the loading circuit includes: and conducting the first SPI and the third SPI of the channel selection circuit in the loading circuit according to the received loading instruction.

Optionally, the load instruction is a parallel load instruction; the method further comprises the following steps: and communicating the TDI pin and the TDO pin of the JTAG circuit in the loading circuit according to the loading instruction.

Optionally, after the TAP controller in the loading circuit is in the DR shifting state, adjusting the level of the target CS signal provided to the CS pin from an inactive level to an active level includes: in the loading circuit, the level of a target CS signal provided to a CS pin is adjusted from an invalid level to an effective level at a first target jump edge of a TCK pin after a TAP controller is in a DR shifting state; the method further comprises the following steps: adjusting the level of a target CS signal provided to the CS pin from an active level to an inactive level at a first target jump edge of the TCK pin after the TAP controller finishes shifting the DR state; wherein, the target jump edge is a rising edge or a falling edge.

Optionally, after the TAP controller in the loading circuit is in the DR shifting state, adjusting the level of the target CS signal provided to the CS pin from an inactive level to an active level includes: adjusting the level of a target CS signal provided to the CS pin from an invalid level to an effective level at an nth target jump edge of the TCK pin after the TAP controller is in a DR shifting state in the loading circuit; and/or, the method further comprises: in the loading circuit, the TAP controller finishes shifting the mth target jump edge of the TCK pin before the DR state, and the level of a target CS signal provided for the CS pin is changed from an active level jump to an inactive level; the target jump edge is a rising edge or a falling edge, and both n and m are positive integers.

Optionally, the method further comprises: and delaying a TDI signal provided by a TDI pin of a JTAG circuit in the loading circuit for i clock cycles and providing the delayed TDI signal to a MOSI pin of the first SPI, wherein i is a positive integer not greater than n.

The beneficial effects of the loading method provided by the above aspect can be described with reference to the effects of the loading circuit provided by the above aspect.

In yet another aspect, a loading system is provided, the loading system comprising: the device comprises a controller, x first loading circuits and x serial peripheral interface SPI flash memories, wherein x is a positive integer; wherein each of the first loading circuits is the loading circuit according to any one of claims 1 to 10; the controller is connected with the JTAG circuit in each first loading circuit through a JTAG interface, and each SPI flash memory is connected with a third SPI of a channel selection circuit in the first loading circuit; the controller is used for sending a loading instruction and data to the JTAG circuit, wherein the loading instruction is used for instructing the JTAG circuit to conduct the first SPI and the third SPI of the channel selection circuit and loading the data to the SPI flash memory.

In the loading system that this application provided, because each pin of JTAG circuit can correspond with each pin of first SPI and be connected among the loading circuit, and this JTAG circuit can control this first SPI and third SPI and switch on, consequently realized JTAG interface and SPI's communication. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted. Therefore, the out-of-band upgrading of the firmware stored in the SPI flash memory through the JTAG interface is realized, and the flexibility of firmware upgrading is improved.

Optionally, the system further includes: n second loading circuits connected in series between the TDI pin of the JTAG interface of the controller and the first loading circuit, wherein n is a positive integer; the controller is further configured to send a first configuration instruction to the first loading circuit, the first configuration instruction being configured to indicate that a first value indicating the n is configured in a first configuration register of the first loading circuit.

For a scenario where the first load circuit is preceded by n other load circuits in series, there may be a delay in the TDI signal that the controller transmits to the TDI pin of a load circuit. Therefore, in the solution provided in this application, the controller may further configure a first value indicating the n in the first configuration register of the first loading circuit, and the timing conversion circuit may delay the edge of the initial CS signal by n clock cycles according to the first value, so as to enable synchronization between the data signal and the control signal received by the first SPI.

Optionally, the x is 1; the system further comprises: m third loading circuits connected in series between the first loading circuit and the TDO pin of the JTAG interface of the controller, wherein m is a positive integer; the controller is further configured to determine, according to the number m of the third loading circuits, a duration that the target CS signal is at an active level, and send a second configuration instruction to the first loading circuit, where the second configuration instruction is further configured to indicate that a second value indicating the duration that the target CS signal is at the active level is configured in the first configuration register; the target CS signal is a signal received by a CS pin of the first SPI in the first loading circuit.

For a scenario where m other load circuits are connected in series after the load circuit, there is a delay in the TDO signal transmitted from the TDO pin of the load circuit to the controller. Therefore, in the solution provided in this application, the controller may further configure the first configuration register of the first loading circuit according to the number m of the third loading circuits. The timing conversion circuit can lead the jump edge of the initial CS signal to be m clock cycles ahead according to the configuration in the first configuration register, so that the data signal and the control signal received by the first SPI can be synchronous.

Optionally, x is greater than 1, and the x first loading circuits are connected in series; the system further comprises: n-x +1 second loading circuits connected in series between the TDI pin of the JTAG interface of the controller and the x first loading circuits, wherein n is a positive integer, and x is an integer not greater than n + 1; the controller is used for carrying out parallel loading on the SPI flash memories connected with the x first loading circuits, the loading instruction is a parallel loading instruction, and the loading instruction is also used for indicating the 1 st to the x-1 st first loading circuits in the x first loading circuits to communicate the TDI pin and the TDO pin of the JTAG circuit; the controller is further configured to send a first configuration instruction to each of the first load circuits, and send a third configuration instruction to the 1 st to x-1 st of the first load circuits, where the first configuration instruction is used to indicate that a first value indicating n is configured in the first configuration register of the first load circuit, and the third configuration instruction sent to the x-i th of the first load circuits is used to indicate that a third value indicating i is configured in the second configuration register of the x-i th of the first load circuits, and i is a positive integer smaller than x.

The controller can send parallel loading instructions to x first loading circuits which are connected in series, and the 1 st to the x-1 st first loading circuits can communicate the TDI pin and the TDO pin of the JTAG circuit according to the parallel loading instructions, so that the controller can load data to the SPI flash memory which is connected with the x first loading circuits in parallel and perform out-of-band upgrading on firmware stored in the SPI flash memory in parallel, and the time consumed by firmware upgrading is effectively reduced; the controller can send the first numerical value for indicating n to the 1 st to the x-1 st first loading circuits, so even if other loading circuits are connected in series before the x first loading circuits, the controller can still correctly load the SPI flash memories connected with the x first loading circuits in parallel; and the controller can send a third numerical value for indicating i to the x-i first loading circuit, so that the x-i first loading circuit can delay the TDI signal by i clock cycles and provide the delayed TDI signal to the MOSI pin, and the controller can load the SPI flash memory connected with the x first loading circuits at the same time, thereby simplifying the control complexity.

In summary, the present application provides a loading circuit, method and system. In the scheme that this application provided, the passageway selection circuit in the load circuit has first SPI, second SPI and third SPI, and this third SPI is used for connecting SPI flash memory. Because each pin of the JTAG circuit in the loading circuit can be correspondingly connected with each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to be conducted, the communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted. Therefore, the out-of-band upgrading of the firmware stored in the SPI flash memory through the JTAG interface is realized, and the flexibility of firmware upgrading is improved.

Drawings

Fig. 1 is a schematic structural diagram of a loading system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a loading circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of JTAG interface timing and SPI timing provided by an embodiment of the present application;

FIG. 4 is a schematic diagram of a state machine of a TAP controller provided in an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another loading circuit provided in an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another loading circuit provided in an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another loading circuit provided in an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another loading system provided in an embodiment of the present application;

FIG. 9 is a schematic diagram of another JTAG interface timing and SPI timing provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of another loading system provided in the embodiments of the present application;

FIG. 11 is a schematic diagram of a JTAG interface timing sequence and an SPI timing sequence provided by an embodiment of the present application;

FIG. 12 is a schematic diagram of a JTAG interface timing sequence and an SPI timing sequence provided by an embodiment of the present application;

fig. 13 is a flowchart of a loading method provided in an embodiment of the present application;

FIG. 14 is a schematic structural diagram of another loading system provided in an embodiment of the present application;

FIG. 15 is a schematic structural diagram of another loading system provided in an embodiment of the present application;

fig. 16 is a schematic structural diagram of another loading system according to an embodiment of the present application.

Detailed Description

The loading circuit, method and system provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

In the related art, when firmware of a processor board card supporting SPI is upgraded in an out-of-band upgrade manner, an SPI of a BMC needs to be connected to an SPI flash memory in the processor board card through a Multiplexer (MUX). The MUX needs to be additionally arranged on the processor board card, so that the size and the cost of the processor board card are large. The multiplexer may also be referred to as a channel selection circuit, among others.

And because the processor board card mainly upgrades the firmware in an in-band upgrading mode, the out-of-band upgrading mode is considered to be used when the in-band upgrading fails. Therefore, the out-of-band upgrade mode is used less frequently, and the overhead of additionally arranging the MUX on the processor board card for the out-of-band upgrade is large.

Fig. 1 is a schematic structural diagram of a loading system according to an embodiment of the present application. As shown in fig. 1, the loading system may include: controller 01, x first load circuits 02 and x SPI flash 03. Wherein x is a positive integer, and the x first loading circuits 02 are connected with the x SPI flash memories 03 in a one-to-one correspondence manner. For example, fig. 1 schematically shows a first load circuit 02 and an SPI flash memory 03 (i.e., x ═ 1). It should be understood that if x is greater than 1, the x first loading circuits 02 may be connected in series.

As shown in fig. 1, the controller 01 may be connected to each first load circuit 02 through a JTAG interface, and is configured to send a load instruction and data to be loaded to each first load circuit 02. Each first loading circuit 02 is connected with a corresponding SPI flash memory 03 through the SPI, and each first loading circuit 02 can load data sent by the controller 01 to the SPI flash memory 03 connected thereto through the SPI under the instruction of the loading instruction, thereby upgrading the firmware stored in the SPI flash memory.

Fig. 2 is a schematic structural diagram of a loading circuit according to an embodiment of the present disclosure. The loading circuit may be applied to the system as shown in fig. 1, i.e. the loading circuit may be the first loading circuit 02 in fig. 1. The following description will be given taking the loading circuit as the first loading circuit 02 as an example. As shown in fig. 2, the first loading circuit 02 may include: JTAG circuitry 021, SFC022, and channel select circuitry 023. The channel selection circuit 023 has a first SPI, a second SPI, and a third SPI, the second SPI being connected with the SFC022, the third SPI being used to connect the SPI flash 03.

The JTAG circuit 021 is configured to control the first SPI of the channel selection circuit 023 to be conducted with the third SPI, or control the second SPI to be conducted with the third SPI. For example, the JTAG circuit 021 may be coupled to a control interface of the channel selection circuit 023 and may send instructions to the control interface. The channel selection circuit 023 may switch on the first SPI and the third SPI, or switch on the second SPI and the third SPI according to the instruction. When the first SPI and the third SPI are turned on, the JTAG circuit 021 may communicate with the SPI flash memory 03, for example, data may be loaded to the SPI flash memory 03. When the second SPI is turned on with the third SPI, the SFC022 may control the SPI flash memory 03.

As can be seen with reference to fig. 1 and 2, the JTAG interface of the JTAG circuit 021 may include a TCK pin, a TDI pin, a TDO pin, a Test Mode Selection (TMS) pin, and a test reset input (TRST) pin. Each SPI may include an SCLK pin, a MOSI pin, a MISO pin, and a CS pin.

Wherein, the JTAG circuit 021 is compatible with an Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard, a TCK pin of the JTAG circuit 021 is connected to an SCLK pin of the first SPI, a TDI pin of the JTAG circuit 021 is connected to a MOSI pin of the first SPI, a TDO pin of the JTAG circuit 021 is connected to a MISO pin of the first SPI, and a TAP controller 021a of the JTAG circuit 021 is connected to a CS pin of the first SPI. After the TAP controller 021a is in the shift DR state, the level of the target CS signal supplied to the CS pin jumps from an inactive level to an active level.

Fig. 3 is a timing diagram of pins in a JTAG interface and SPI provided by an embodiment of the present application. Referring to fig. 3, it can be seen that the timing of the TCK pin of the JTAG interface is the same as the timing of the SCLK pin in the first SPI, the timing of the TDI pin of the JTAG interface is the same as the timing of the MOSI pin in the first SPI, and the timing of the TDO pin of the JTAG interface is the same as the timing of the MISO pin in the first SPI. Therefore, the TCK pin of the JTAG interface may be directly connected to the SCLK pin in the first SPI, so that the TCK signal transmitted by the TCK pin serves as the SCLK signal of the first SPI. And, the TDI pin of the JTAG interface may be directly connected to the MOSI pin in the first SPI, so that the TDI signal transmitted by the TDI pin may be used as the MOSI signal of the first SPI. And, the TDO pin of the JTAG interface may be directly connected to the MISO pin in the first SPI, so that the TDO signal transmitted by the TDO pin may be used as the MISO signal of the first SPI.

Since in the JTAG protocol, referring to fig. 3, the JTAG circuit 021 is able to acquire a TDI signal (i.e., write data) transmitted by the TDI pin and transmit a TDO signal (i.e., read data) to the TDO pin while the TAP controller 021a is in the shift DR state. The above timing characteristics are respectively the same as those of the data writing timing and the data reading timing of the SPI. Accordingly, a target CS signal transmitted to the CS pin of the first SPI may be generated based on the shifted DR state of the TAP controller 021 a.

The active level of the target CS signal received by the CS pin in the first SPI may be low, and the inactive level may be high, for example, the CS signal may be denoted as CS #, # denotes that the signal is active low. The first SPI may read write data, i.e., write data through the MOSI pin, and read data out through the MISO when the target CS signal is at an active level.

Fig. 4 is a schematic diagram of a state machine of a TAP controller according to an embodiment of the present disclosure. As shown in fig. 4, the TAP controller 021a has 16 synchronization states: test logic/reset (test-logic/reset), run test/idle (run-test/idle), select-DR-scan (select-DR-scan), capture DR (capture-DR), shift DR (shift-DR), exit 1DR (exit1-DR), pause DR (pause-DR), exit 2DR (exit2-DR), update DR (update-DR), select IR scan (select-IR-scan), capture IR (capture-IR), shift IR (shift-IR), exit 1IR (exit1-IR), pause IR (pause-IR), exit 2IR (exit2-IR), and update IR (update-IR). Wherein the synchronization state of the TAP controller 021a can be changed under the control of the TMS signal. In the state machine shown in fig. 4, TMS ═ 1 indicates that the TMS signal is high, and TMS ═ 0 indicates that the TMS signal is low. Since the timing of the read/write data of the JTAG circuit 021 depends on the shifted DR state of the TAP controller 021a, the JTAG circuit 021 can read/write data as long as the synchronization state of the TAP controller 021a passes through the shifted DR state. Referring to fig. 4, it can be seen that the path for the synchronization state of the TAP controller 021a to transition to the shift DR state is not unique.

Based on the pin connection mode, the conversion from the time sequence of the JTAG circuit to the time sequence of the SPI can be realized, namely, the communication between the JTAG interface and the SPI can be realized. Because most PCIE board cards support the JTAG interface, the controller can upgrade the SPI flash memory on the PCIE board cards out of band through the JTAG interface.

In summary, the embodiment of the present application provides a loading circuit, which includes a JTAG circuit and a channel selection circuit, where the channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect an SPI flash memory. Because each pin of the JTAG circuit can be correspondingly connected with each pin of the first SPI, and the JTAG circuit can control the first SPI and the third SPI to be conducted, the communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted, thereby realizing the out-of-band upgrade of the firmware stored in the SPI flash memory.

Optionally, the JTAG circuit 021 may be configured to control the first SPI and the third SPI to be turned on according to a received load instruction. The load instruction may be issued by the controller 01 in the loading system. The controller 01 can issue a load instruction to the JTAG circuit 021 in the first load circuit 02 through the JTAG interface when the firmware in the SPI flash 03 connected to the first load circuit 02 needs to be upgraded in an out-of-band upgrade manner.

Fig. 5 is a schematic diagram of another loading circuit according to an embodiment of the present disclosure, and as shown in fig. 5, the JTAG circuit 021 of the first loading circuit 02 may further include an Instruction Register (IR) 021b and an instruction decoder 021 c. The IR 021b is connected to the TDI pin, and may be configured to receive a load instruction, and control the channel selection circuit 023 to conduct the first SPI and the third SPI according to the load instruction. The command decoder 021c may be configured to decode the command received by the IR 021b, and send a control signal to the channel selection circuit 023 so as to control the channel selection circuit 023 to conduct the first SPI and the third SPI. It should be appreciated that JTAG circuit 021 in the first load circuit 02 may also include a Data Register (DR) 021d, and the IR 021b may configure DR 021d according to the received load instruction. The channel selection circuit 023 can further conduct the first SPI and the third SPI based on the configuration in DR 021 d. It should also be understood that the IR 021b can also generate a control signal through logic circuitry (e.g., and gate and or gate, etc.) in conjunction with the internal state of the JTAG circuit 021, thereby controlling the channel select circuit 023 to turn on the first SPI with the third SPI.

Referring to fig. 5, it can also be seen that the JTAG circuit 021 may further include two MUXs through which the IR 021b, the instruction decoder 021c, the bypass register 021d1, the identification code register 021d2, and the MISO pin in the first SPI may be connected with the TDO pin.

As an alternative implementation, the loading system may include more than 1 first loading circuits 02, that is, x may be more than 1. In this scenario, the controller 01 may load the x first loading circuits 02 in parallel. Accordingly, the load instruction issued by the controller 01 to the JTAG circuit 021 in the x-1 first load circuits 02 may be a parallel load instruction. The JTAG circuit 021 receiving the parallel load instruction may be further configured to communicate the TDI pin with the TDO pin according to the parallel load instruction, so that the TDI signal received through the TDI pin may be directly transmitted to the next first load circuit 02 through the TDO pin. The TDI signal may include instructions sent by the controller and data to be loaded.

For example, as shown in fig. 5 and 6, the DR 021d may include a bypass register 021d1 and an identification code register 021d2 connected to the TDI pin and the TDO pin, respectively. The identification code register 021d2 is used to store the identification code of the first loading circuit 02, which is used to uniquely identify the first loading circuit 02. The bypass register 021d1 is used for responding to the parallel loading instruction and communicating the TDI pin with the TDO pin after the IR 021b receives the parallel loading instruction, so that the TDI signal is transmitted through while the data is loaded to the SPI flash memory. The bold black line in fig. 6 indicates a transmission path of the TDI signal in the first loading circuit 02.

As another alternative implementation, as shown in fig. 1, only one first loading circuit 02 may be included in the loading system, i.e., x ═ 1. In this scenario, the TDI pin of the first loading circuit 02 is directly connected to the TDI pin of the JTAG interface of the controller 01, and the TDO pin is directly connected to the TDO pin of the JTAG interface of the controller 01, so that there is no delay in the TDI signal transmitted from the controller 01 to the TDI pin of the first loading circuit 02, and there is no delay in the TDO signal transmitted from the TDO pin of the first loading circuit 02 to the controller 01. Therefore, the phase in which the target CS signal is at the active level can be determined directly with reference to the phase in which the TAP controller 021a is in the shift DR state.

Accordingly, as shown in fig. 3, at the first target jump edge of the TCK pin after the TAP controller 021a is in the DR-shifted state, the level of the target CS signal supplied to the CS pin jumps from an inactive level to an active level. At the first target jump edge of the TCK pin after the TAP controller 021a finishes the DR state, the level of the target CS signal supplied to the CS pin jumps from an active level to an inactive level. Wherein, the target jump edge is a rising edge or a falling edge.

Also, referring to FIG. 7, it can be seen that in this scenario, bypass register 021d1 does not communicate the TDI pin with the TDO pin. The bold line in fig. 7 indicates the transmission path of data in the first loading circuit 02, and as can be seen from fig. 7, the data to be loaded sent from the TDI pin of the JTAG circuit 021 is transmitted to the MOSI _1 pin of the first SPI through the timing conversion circuit 024. Since the MOSI _1 pin is gated to the MOSI _3 pin, the data to be loaded can be transmitted to the SPI flash 03. The data read out by the SPI flash 03 is transmitted from the MISO _3 pin to the MISO _1 pin of the first SPI through the channel selection circuit 023, and then transmitted to the TDO pin of the JTAG circuit 021 through the MUX inside the JTAG circuit 021. The above process completes the writing of the data to be loaded and the reading of the data in the SPI flash 03.

For example, assuming that the active level is low in the timing sequence of each pin shown in fig. 3, the target hop edge may be a falling edge. Referring to fig. 3, at the first falling edge of the TCK pin after the TAP controller 021a is in the DR-shifted state, the target CS signal provided to the CS pin by the TAP controller 021a jumps from a high level to a low level. At the first falling edge of the TCK pin after the TAP controller 021a finishes the DR state, the level of the target CS signal supplied to the CS pin by the TAP controller 021a jumps from low level to high level.

In the embodiment of the present application, the target CS signal may be provided to the CS pin by JTAG circuit 021. That is, the JTAG circuit 021 may supply a target CS signal to the CS pin according to the state of the TAP controller 021a and the level of the TCK pin.

Alternatively, as shown in fig. 5 to 7, the first loading circuit 02 may further include a timing conversion circuit 024, the TAP controller 021a is connected to the CS pin through the timing conversion circuit 024, and the target CS signal may be provided to the CS pin by the timing conversion circuit 024. That is, the timing conversion circuit 024 may provide the target CS signal to the CS pin according to the state of the TAP controller 021a and the level of the TCK pin.

For example, the timing conversion circuit 024 may adjust the level of the target CS signal provided to the CS pin from a high level to a low level at the first falling edge of the TCK pin after the TAP controller 021a is in the shift DR state. At the first falling edge of the TCK pin after the TAP controller 021a finishes the DR state, the level of the target CS signal supplied to the CS pin is adjusted from low level to high level.

Fig. 8 is a schematic structural diagram of another loading system according to an embodiment of the present application. As shown in fig. 8, the loading system may further include: n second load circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the TDI pin of the first load circuit 02, and/or m third load circuits 05 connected in series between the TDO pin of the first load circuit 02 and the TDO pin of the JTAG interface of the controller 01. Each second loading circuit 04 is correspondingly connected with one SPI flash memory 03, each third loading circuit 05 is correspondingly connected with one SPI flash memory 03, and n and m are positive integers. For example, in the system shown in fig. 8, both n and m are integers greater than 1.

The JTAG circuit 021 of the first loading circuit 02 may be used to provide an initial CS signal to the timing conversion circuit 024. Referring to fig. 9, at the first target jump edge of the TCK pin after the TAP controller 021a is in the DR-shifted state, the level of the initial CS signal is adjusted from an inactive level to an active level, and at the first target jump edge of the TCK pin after the TAP controller 021a finishes the DR-shifted state, the level of the initial CS signal is adjusted from an active level to an inactive level, and the target jump edge is a rising edge or a falling edge.

The timing conversion circuit 024 is configured to perform timing conversion on the initial CS signal to obtain a target CS signal, and provide the target CS signal to the CS pin. The timing conversion circuit 024 may implement timing conversion of the initial CS signal by a logic circuit such as a counter or a state machine.

In a scenario where n second load circuits 04 are connected in series between the controller 01 and the TDI pin of the first load circuit 02, a time when the level of the target CS signal received by the CS pin of the first SPI in the load circuit 02 jumps from an inactive level to an active level may be delayed by n clock cycles with respect to a time when the initial CS signal jumps from an inactive level to an active level.

N second loading circuits 04 are connected in series between the TDI pin of the first loading circuit 02 and the TDI pin of the JTAG interface of the controller 01, wherein each second loading circuit 04 can enter a bypass state under the instruction of the controller 01 to pass through the TDI signal sent by the controller 01. Moreover, the time duration required for each second loading circuit 04 to pass through the TDI signal is one clock cycle, so that the TDI signal sent by the controller 01 needs to pass through n clock cycles before being transmitted to the first loading circuit 02. Accordingly, the timing conversion circuit 021 in the first loading circuit 02 may delay the time at which the level of the initial CS signal jumps from the inactive level to the active level by n clock cycles and supply the delayed signal to the CS pin.

Alternatively, referring to fig. 6 and 7, the first loading circuit 02 may further include a first configuration register 025 connected to the timing conversion circuit 024, and the first configuration register 025 may have a first value indicating the n configured therein. Wherein, as shown in fig. 6 and 7, the first configuration register 025 can be a register in DR 021d of JTAG circuit 021. Also, the first value may be configured by the controller 01. Alternatively, the first configuration register 025 may be a register separate from the JTAG circuit 021, for example, the first configuration register 025 may interface with an inter-integrated circuit (I2C), and the first value may be configured through the I2C interface.

The timing conversion circuit 024 is configured to delay a time at which the initial CS signal jumps from an inactive level to an active level by n clock cycles according to the first value.

For a scenario where m third loading circuits 05 are connected in series between the TDO pin of the first loading circuit 02 and the controller 01, the time when the level of the target CS signal received by the CS pin of the first SPI in the loading circuit 02 jumps from the active level to the inactive level may be advanced by m clock cycles relative to the time when the initial CS signal jumps from the active level to the inactive level.

Since m third loading circuits 05 are connected in series between the TDO pin of the first loading circuit 02 and the TDO pin of the JTAG interface of the controller 01, each third loading circuit 05 can enter a bypass state under the instruction of the controller 01, and pass through the TDO signal sent by the first loading circuit 02. Moreover, the time duration required for each third loading circuit 05 to transparently transmit the TDO signal is one clock cycle, so that the TDO signal transmitted by the TDO pin of the first loading circuit 02 needs to be transmitted to the controller 01 after m clock cycles. Accordingly, the timing conversion circuit 021 in the first loading circuit 02 may advance the time at which the level of the initial CS signal changes from the active level to the inactive level by m clock cycles before supplying the signal to the CS pin.

Optionally, the first configuration register 025 may be configured with a second value indicating a duration of time that the target CS signal is at an active level. The timing conversion circuit 024 is configured to advance a time at which the initial CS signal jumps from an active level to an inactive level by m clock cycles according to the second value.

Wherein the second value may be configured by the controller 01. Also, since the JTAG circuit 021 can write or read data when the CS signal is at the active level, the duration in which the target CS signal is at the active level can be determined by the controller according to the length of the data to be loaded and the data to be read.

Fig. 10 is a schematic structural diagram of another loading system provided in the embodiment of the present application. As shown in fig. 10, the loading system may include: x first loading circuits 02 in series. And, the loading system may further include: n-x +1 second load circuits 04 connected in series between the TDI pin of the JTAG interface of the controller 01 and the x first load circuits 02, and/or m third load circuits 05 connected in series between the x first load circuits 02 and the TDO pin of the JTAG interface of the controller 01. Wherein x is an integer greater than 1 and less than n +1, and n and m are both positive integers.

If the loading system includes m third loading circuits 05, since data does not need to be read when the SPI flash memory is loaded, it is not necessary to consider a time delay caused by the m third loading circuits 05 transmitting through the TDO signal.

In this scenario, as an alternative implementation manner, the number of clock cycles delayed by the timing conversion circuit 024 in each of the x first loading circuits 02 at the time when the initial CS signal jumps from the inactive level to the active level may be equal to the number of loading circuits before the first loading circuit 02. The number of clock cycles by which the timing conversion circuit 024 in each first loading circuit 02 advances the timing at which the initial CS signal jumps from the active level to the inactive level may be equal to the number of first loading circuits after the first loading circuit 02.

For example, since n-x +1 second loading circuits 04 are connected in series between the 1 st first loading circuit 02 and the controller 01, x-1 first loading circuits 02 are connected in series after the 1 st first loading circuit 02. Therefore, referring to fig. 11, the timing conversion circuit 024 in the 1 st first load circuit 02 delays the timing at which the target chip select signal supplied to the CS pin in the first SPI jumps from high to low by n-x +1 clock cycles with respect to the timing at which the initial CS signal jumps from high to low. The timing of the target chip select signal provided by the timing converter 024 to the CS pin in the first SPI that jumps from low to high is advanced by x-1 clock cycles relative to the time of the initial CS signal that jumps from low to high.

Since the xth first loading circuit 02 includes before: x-1 first load circuits 01 and n-x +1 second load circuits 04, i.e. the x-th first load circuit 02 includes n load circuits before it, and the x-th first load circuit 02 is not connected with other first load circuits after it. Therefore, referring to fig. 11, the timing conversion circuit 024 in the xth first load circuit 02 delays the timing at which the target chip select signal supplied to the CS pin in the first SPI jumps from high to low by n clock cycles with respect to the timing at which the initial CS signal jumps from high to low. In addition, the timing at which the target chip select signal provided to the CS pin in the first SPI jumps from low to high does not need to be earlier than the timing at which the initial CS signal jumps from low to high.

In this scenario, as another optional implementation manner, the timing conversion circuit 024 in each of the x first loading circuits 02 may delay the initial chip select signal by n clock cycles and send the delayed initial chip select signal to the CS pin. Also, the number of clock cycles by which the timing conversion circuit 024 in each first loading circuit 02 advances the timing at which the initial CS signal jumps from the active level to the inactive level may be equal to 0, that is, there is no need to advance the timing at which the initial CS signal jumps from the active level to the inactive level.

Moreover, the timing conversion circuit 024 in the x-th first loading circuit 02 of the x first loading circuits 02 may be further configured to delay the TDI signal provided by the TDI pin by i clock cycles and provide the delayed TDI signal to the MOSI pin. Wherein i is a positive integer less than x. And the timing conversion circuit 024 in the xth first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, the x first load circuits 02 can be made to load data to the SPI flash memory 03 at the same time.

For example, referring to fig. 12, the timing conversion circuit 024 in the 1 st first load circuit 02 and the timing conversion circuit 024 in the xth first load circuit 02 delay the timing at which the target chip select signal supplied to the CS pin in the first SPI jumps from high to low by n clock cycles with respect to the timing at which the initial CS signal jumps from high to low. Also, for the 1 st first loading circuit 02, the timing conversion circuit 024 thereof may convert the TDI pin: the TDI signal received by TDI _1 is delayed by x-1 clock cycles and then provided to MOSI _1 of the first SPI. For the xth first loading circuit 02, the timing conversion circuit 024 does not need to delay the TDI signal provided by the TDI pin.

Optionally, as shown in fig. 6 and fig. 7, in the x first loading circuits 02, the x-i th first loading circuit 02 may further include: and a second configuration register 026 coupled to the timing conversion circuit 024, the second configuration register 026 having a third value indicative of the i. Wherein, as shown in fig. 6 and 7, the second configuration register 026 can be a register in DR 021d of JTAG circuit 021. Also, the second value may be configured by the controller 01. Alternatively, the second configuration register 026 can be a register separate from JTAG circuitry 021, e.g., the second configuration register 026 can interface with I2C and the first value can be configured via the I2C interface.

The timing conversion circuit 024 in the x-i-th first loading circuit 02 may be configured to delay the TDI signal provided by the TDI pin by i clock cycles and provide the delayed TDI signal to the MOSI pin according to the third value.

In summary, the embodiment of the present application provides a loading circuit, which includes a JTAG circuit and a channel selection circuit, where the channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect an SPI flash memory. Because each pin of this JTAG circuit can correspond with each pin of this first SPI to be connected, and this JTAG circuit can control this first SPI and third SPI to switch on, consequently realized JTAG interface and SPI's communication. Correspondingly, the controller can be connected with the JTAG circuit in the loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted, thereby realizing the out-of-band upgrade of the firmware stored in the SPI flash memory.

Also, for a scenario where the loading circuit is one of a plurality of loading circuits connected in series in the loading system, the timing conversion circuit in the loading circuit may jump the level of the target CS signal provided to the CS pin from an inactive level to an active level, delay and/or advance by several clock cycles. Therefore, the controller can load the SPI flash memory connected with any one of the plurality of loading circuits connected in series, and the loading flexibility is effectively improved.

And the TDI pin and the TDO pin can be communicated after the loading circuit receives the parallel loading instruction, so that the TDI signal can be transmitted while data are loaded to the SPI flash memory, the controller can be ensured to load a plurality of loading circuits connected in series in parallel, and the loading efficiency is improved. In addition, the time sequence conversion circuit in the loading circuit can delay the TDI signal provided by the TDI pin by i clock cycles and provide the delayed TDI signal to the MOSI pin, so that a plurality of loading circuits can load data to the SPI flash memory at the same time in the parallel loading process.

The embodiment of the present application further provides a loading method, which may be applied to the loading circuit provided in the foregoing embodiment, for example, the method may be applied to the first loading circuit 02 shown in fig. 2 and any one of fig. 5 to 7. The following description will be given taking an example in which the loading method is applied to the first loading circuit 02. As shown in fig. 13, the method may include:

and step 101, receiving a loading instruction sent by a controller.

In this embodiment of the application, when the firmware stored in the SPI flash memory needs to be upgraded in an out-of-band upgrade manner, the controller may issue a load instruction to the first load circuit connected to the SPI flash memory.

And 102, conducting a first SPI and a third SPI of a channel selection circuit in the first loading circuit according to the loading instruction.

The JTAG circuit in the loading circuit can respond to a loading instruction issued by the controller, and the control channel selection circuit conducts the first SPI and the third SPI.

Step 103, after the TAP controller in the first loading circuit is in the DR shifting state, the level of the target CS signal provided to the CS pin of the first SPI is adjusted from the inactive level to the active level.

In an embodiment of the present application, the target CS signal may be provided by JTAG circuitry in the load circuitry. Alternatively, a timing conversion circuit may be included in the loading circuit, and the target CS signal may be provided by the timing conversion circuit.

As an alternative implementation, referring to fig. 1 or fig. 6, the loading system may include only one first loading circuit 02, and in this implementation, the loading circuit 02 may turn on only the first SPI and the third SPI in response to the load instruction.

As another alternative implementation, referring to fig. 8, the loading system may include x first loading circuits 02, where x is greater than 1. In this implementation, the controller 01 may load the x first load circuits 02 in parallel, i.e., the load instruction is a parallel load instruction. Accordingly, the first load circuit may also communicate the TDI pin with the TDO pin of the JTAG circuit in response to the parallel load instruction. Therefore, the TDI signal can be transparently transmitted to the SPI flash memory when data are loaded, the controller is further ensured to be capable of carrying out parallel loading on a plurality of first loading circuits connected in series, and loading efficiency is improved.

For the scenario where the loading system includes only one first loading circuit 02, the implementation process of step 103 may include:

in the first loading circuit 02, the level of the target CS signal supplied to the CS pin is adjusted from an inactive level to an active level at the first target jump edge of the TCK pin after the TAP controller 021a is in the DR-shifted state.

Also, referring to fig. 10, the method may further include:

in step 104a, after the TAP controller in the first loading circuit finishes shifting the DR state, the level of the target CS signal provided to the CS pin is adjusted from an active level to an inactive level.

The target skip edge may be a rising edge or a falling edge, the active level of the target CS signal received by the CS pin may be a low level, and the inactive level may be a high level.

For a scenario in which n second loading circuits are connected in series between the controller and the TDI pin of the first loading circuit in the loading system, the implementation process of step 103 may include:

and the n & ltth & gt target jump edge of the TCK pin after the TAP controller is in the DR shifting state in the loading circuit adjusts the level of a target CS signal provided for the CS pin from an invalid level to an valid level.

Because the TDI signal sent by the controller needs to be transmitted to the first loading circuit after n clock cycles, the timing conversion circuit in the first loading circuit can delay the time when the level of the initial CS signal changes from the inactive level to the active level by n clock cycles and provide the delayed signal to the CS pin.

For a scenario in which m third loading circuits are connected in series between the TDO pin of the first loading circuit and the controller in the loading system, referring to fig. 10, the method may further include:

in step 104b, the TAP controller in the loading circuit finishes shifting the mth target jump edge of the TCK pin before the DR state, and the level of the target CS signal supplied to the CS pin is changed from the active level to the inactive level.

Because the TDO signal sent by the TDO pin of the first loading circuit needs to be transmitted to the controller after m clock cycles, the timing conversion circuit in the first loading circuit can advance the time at which the level of the initial CS signal changes from the active level to the inactive level by m clock cycles before being provided to the CS pin. Wherein n and m are both positive integers.

For the scenario that the loading system includes x first load circuits and x is greater than 1, as shown in fig. 10, the method performed by the ith first load circuit of the x first load circuits may further include:

step 105, delaying the TDI signal provided by the TDI pin of the first loading circuit by i clock cycles and providing the delayed TDI signal to the MOSI pin of the first SPI.

Wherein i is a positive integer less than x. When the loading system includes x first loading circuits connected in series, the controller may load the x first loading circuits in parallel. The timing conversion circuit 024 in the x-th first loading circuit 02 and the x-i-th first loading circuit 02 may be further configured to delay the TDI signal provided by the TDI pin by i clock cycles and provide the delayed TDI signal to the MOSI pin. And the timing conversion circuit 024 in the xth first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, the x first load circuits 02 can be made to load data to the SPI flash memory 03 at the same time.

In summary, the embodiments of the present application provide a loading method, which can be applied to the loading circuit provided in the above embodiments. The loading circuit includes JTAG circuitry and a channel selection circuit having a first SPI, a second SPI, and a third SPI for connecting to the SPI flash. Because each pin of the JTAG circuit can be correspondingly connected to each pin of the first SPI, and the load circuit can receive a load instruction issued by the controller, and switch on the first SPI and the third SPI according to the load instruction, communication between the JTAG interface and the SPI is realized. Correspondingly, the controller can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted, and therefore out-of-band upgrading of firmware stored in the SPI flash memory is achieved.

An embodiment of the present application further provides a loading system, and with reference to fig. 1 and fig. 14, the loading system may include: the controller 01, x first loading circuits 02 and x SPI flash memories 03, where x is a positive integer. Each of the first loading circuits 02 may be the loading circuit provided in the above embodiments. For example, fig. 1 schematically illustrates a first loading circuit 02 and an SPI flash memory 03 (i.e., x ═ 1), and it is understood that if x is greater than 1, the x first loading circuits 02 may be connected in series.

The controller 01 can be connected to the JTAG circuit 021 in each of the first loading circuits 02 through the JTAG interface, and each of the SPI flash memories 03 is connected to the third SPI of the channel selection circuit 023 in the first loading circuit 02.

As can be seen with reference to fig. 14, the first loading circuit 02 may include: JTAG circuitry 021, SFC022, and channel select circuitry 023. The JTAG interface of the controller 01 may include: a TRST pin, a TCK pin, a TMS pin, a TDI pin, and a TDO pin. The controller 01 is connected to a JTAG circuit 021 in the first loading circuit 02 through the above-mentioned pin of the JTAG interface, and the SPI flash memory 03 is connected to a third SPI of the channel selection circuit 023 in the first loading circuit 02.

The controller 01 is configured to send a load instruction and data to the JTAG circuit 021, where the load instruction is used to instruct the JTAG circuit 021 to turn on the first SPI and the third SPI of the channel selection circuit 023, and load the data to the SPI flash memory 03. Wherein, the controller 01 may be a BMC or a JTAG emulator.

With continued reference to fig. 14, the controller 01 may send a TDI signal to the JTAG circuit 021 in the first load circuit 02 through the TDI pin of the JTAG interface. The TDI signal may contain a load instruction or data.

In this embodiment, the controller 01 may be configured with loading software, and the loading software may be a Serial Vector Format (SVF) file parser. When the SPI flash 03 needs to be loaded, the controller 01 may first parse and execute the SVF file through the loading software. The SVF file may be obtained by converting a target binary file that needs to be loaded into the SPI flash memory 03. The process of loading the SPI flash 03 connected to the first loading circuit 02 by the controller 01 may include the following steps:

1. the controller 01 resets the first loading circuit 02. For example, the controller 01 may adjust the level of the TRST signal sent to the first loading circuit 02 to an inactive level. If the controller 01 is connected to a plurality of load circuits connected in series including the first load circuit 02, the controller 01 needs to reset all of the plurality of load circuits connected in series. Wherein the plurality of serially connected load circuits may be referred to as a JTAG chain.

2. The controller 01 issues a configuration instruction to the first load circuit 02 through the IR instruction, where the configuration instruction is used to configure the timing parameters. The timing conversion circuit 024 in the first loading circuit 02 may read the timing parameter to effect conversion of the JTAG timing to the SPI timing. For example, as shown in fig. 14, for a scenario where n second loading circuits 04 are connected in series between the TDI pin of the controller 01 and the first loading circuit 02, and/or m third loading circuits 05 may be connected in series between the TDO pin of the first loading circuit 02 and the controller 01, the timing parameter may include a first value indicating the n and a second value indicating the m.

3. The controller 01 issues a load instruction to the first load circuit 02 through the IR instruction, where the load instruction is used to instruct to turn on the first SPI and the third SPI of the channel selection circuit 023.

4. The controller 01 issues data to be loaded to the first loading circuit 02 through a DR instruction so as to load the SPI flash memory 03 connected to the first loading circuit 02.

The above flow can be described by the following pseudo flow in SVF format:

the detailed syntax of the SVF file may refer to serial vector format specification (serial vector format specification). Since a certain time is required for the erasing process of the SPI flash memory 03, it can be seen with reference to the above-described dummy flow that the first loading circuit 02 needs to wait for k ms in response to the wait instruction after executing the erase instruction. The k may be a positive number, and the value of k may be set according to a duration required to empty the storage space of the SPI flash memory 03.

Taking the loading system shown in fig. 1 and including only one first loading circuit 02 as an example, a process of loading the SPI flash memory 03 connected to the first loading circuit 02 by the controller 01 will be described. Assume that the length of IR 021a in JTAG circuit 021 is 4 bits (bit), the command length of SPI flash 03 is 8 bits, and the address length of SPI flash 03 is 3 bytes (byte), i.e., 24 bits. If the load instruction is defined as a hexadecimal number: 3, the erase command is defined as a hexadecimal number: c7, programming instructions are defined as hexadecimal numbers: 02. when the controller 01 loads the SPI flash 03 connected to the first loading circuit 02, the executed SVF file may be:

since the SVF file parser provided in the controller 01 reads the instructions in the SVF file from the lower order to the upper order, the instruction values provided in the SVF file are in the reverse order of the upper order and the lower order of the actual instructions. For example, a load instruction is defined as a hexadecimal number: 3 (binary: 0011), since the load instruction is arranged from low bit to high bit in the following order: 1100 (denoted c in the 16 th notation), the instruction value of the load instruction in the SVF file is c. The erase command is defined as a hexadecimal number: c7 (binary expression: 11000111), since the sequence of the erasure instruction from low bit to high bit is: 11100011 (denoted by 16 as: e3), so the instruction value of the erase instruction in the SVF file is e 3.

Executing a programming instruction to write data to be loaded to the 0 address: ff5a, since the program instruction is defined as a hexadecimal number: 02 (binary represented by 00000010), which is arranged from lower to higher in the order: 01000000 (40 in 16), so for writing data to be loaded: the last two bits of the TDI signal "5 aff 00000040" of ff5a are 40. Since the address length of the SPI flash 03 is 3 bytes (24 bits), 0000000 in the middle of the TDI signal "5 af 00000040" indicates a 0 address having a length of 3 bytes. Also since the data ff5a to be loaded are binary represented as: 1111111101011010, the low order to the high order is: 0101101011111111 (i.e., hexadecimal number: 5 af), so the first four bits of the TDI signal "5 af 00000040" are 5 af.

It should be understood that the SVF file is described by taking a loading system (i.e., x is 1) including only one first loading circuit 02 as an example, and thus the controller 01 does not need to issue a configuration instruction to the first loading circuit 02 to configure the timing parameters.

Optionally, for a scenario where the loading system includes only one first loading circuit 02, as shown in fig. 14, the loading system may further include: and n second loading circuits 04 which are connected between the TDI pin of the JTAG interface of the controller 01 and the first loading circuit 02 in series, wherein n is a positive integer. The controller 01 may be further configured to send a first configuration instruction to the first load circuit 02, where the first configuration instruction is used to indicate that a first value indicating the n is configured in the first configuration register 025 of the first load circuit 02.

Referring to fig. 9, the timing conversion circuit 024 in the first loading circuit 02 may determine the value of n according to the first numerical value, and delay a timing at which the target chip select signal supplied to the CS pin in the first SPI jumps from high to low by n clock cycles with respect to a timing at which the initial CS signal jumps from high to low.

Optionally, for a scenario where the loading system includes only one first loading circuit 02, as shown in fig. 14, the loading system may further include: m third loading circuits 05 connected in series between the TDO pin of the first loading circuit 02 and the controller 01, where m is a positive integer. The controller 01 is further configured to determine a duration of the target CS signal being at the active level according to the number m of the third loading circuits 04, and send a second configuration instruction to the first loading circuit 02, where the second configuration instruction is further configured to indicate that a second value indicating the duration of the target CS signal being at the active level is configured in the first configuration register 025.

Referring to fig. 9, the timing conversion circuit 024 in the first loading circuit 02 may determine the value of m according to the second value, and advance the timing at which the target chip select signal supplied to the CS pin in the first SPI jumps from low to high by m clock cycles with respect to the timing at which the initial CS signal jumps from low to high.

In the above scenario, when the controller 01 loads the SPI flash memory 03 to which the first load circuit 02 is connected, the n second load circuits 04 and the m third load circuits 05 may be adjusted to be in the bypass state, as shown in fig. 15, where the n second load circuits 04 correspond to n bypass registers and the m third load circuits 05 correspond to m bypass registers. The n bypass registers only pass through the TDI signal sent by the controller 01, and the m bypass registers only pass through the TDO signal sent by the first loading circuit 02, wherein each bypass register passes through the TDI or TDO signal taking 1 clock cycle. It should be understood that the first loading circuit 02 may also load data to be loaded transmitted by the TDI signal, the loading time is j clock cycles, and the value of j is determined by the length of the data to be loaded.

Since the TDI signal sent by the controller 01 needs to reach the first load circuit 02 through n clock cycles, the TDO signal sent by the first load circuit 02 needs to reach the controller 01 through m clock cycles, and the first load circuit 02, each second load circuit 04, and each third load circuit 05 are all state-switched under the same TCK signal and TMS signal sent by the controller 01, the data signals (including the TDI signal and the TDO signal) are not synchronized with the control signals (including the TCK signal and the TMS signal).

In this embodiment, the controller 01 may send a first configuration instruction and a second configuration instruction to the first loading circuit 02 to configure the timing parameter (including the first value and the second value) in the first configuration register of the first loading circuit 02. The timing conversion circuit 024 in the first loading circuit 02 may adjust the timing of the initial CS signal by reading the timing parameter to obtain a target CS signal, thereby synchronizing the data signal with the control signal.

Hereinafter, a process of loading the SPI flash memory 03 connected to the first load circuit 02 by the controller 01 will be described by taking a loading system in which 2 second load circuits 04 are connected in series between the TDI pin of the controller 01 and the first load circuit 02 and 2 third load circuits 05 are connected in series between the TDO pin of the first load circuit 02 and the controller 01 as an example, that is, taking n ═ m ═ 2 as an example. It is assumed that the IR in each load circuit is 4 bits long, the command length of the SPI flash 03 is 8 bits, and the address length of the SPI flash 03 is 3 bytes (i.e., 24 bits). If the strobe instruction is defined as a hexadecimal number: 2, the first configuration instruction is defined as a hexadecimal number: 02, the load instruction is defined as a hexadecimal number: 3, the bypass instruction is defined as a hexadecimal number: f, the erase command is defined as a hexadecimal number: c7, the programming instruction is defined as a hexadecimal number 02. When the controller 01 loads the SPI flash 03 connected to the first loading circuit 02, the executed SVF file may be:

since the loading system includes 5 loading circuits in total, the controller 01 can adjust each of the 2 second loading circuits 04 and the 2 third loading circuits 05 except for the first loading circuit 02 to the bypass state. Since the 5 load circuits are connected in series, the controller 01 issues a load instruction to the first load circuit 02: 3, issuing a bypass instruction to the 2 second load circuits 04 and the 2 third load circuits 05: f, therefore, the command issued by the controller 01 may be: ffcff.

Upon issuing a first configuration instruction to the first configuration register 025 in the first load circuit 02: when 02, the instruction value in the SVF file is 100 hexadecimal number, the length of the instruction value is 10bit, and the binary expression is as follows: 0100000000. since the first load circuit 02 is preceded by 2 second load circuits 04, for the first configuration register 025 in the first load circuit 02, it actually reads the instruction with the upper 8 bits of 0100000000: 01000000. the SVF file parser reads the instructions in the SVF file from the low order to the high order, and 01000000 reads from the low order to the high order as follows: 00000010 (i.e., hexadecimal number: 02).

Similarly, the controller 01 issues an erase command to the SPI flash 03 connected to the first load circuit 02: at C7, the instruction value of the scrub instruction in the SVF file is hexadecimal number: 38c, the instruction value length is 10 bits, and the binary expression is: 1110001100. since the first load circuit 02 is preceded by 2 second load circuits 04, the SPI flash 03 to which the first load circuit 02 is connected actually reads the instruction value of 1110001100 with the upper 8 bits: 11100011. the SVF file parser reads the instructions in the SVF file from the lower bits to the upper bits, and the 11100011 reads the instructions from the lower bits to the upper bits as follows: 11000111 (i.e. hexadecimal number: C7).

The TDI signal for writing the data ff5a to be loaded to the SPI flash 03 is represented as: 16bfc00000100, 50 bits in length, binary represented as: 01011010111111110000000000000000000000000100000000. because there are 2 second loading circuits 04 before the first loading circuit 02, the TDI signal needs to be delayed by 2 clock cycles, and therefore the lowest 2 bits of the TDI signal are: 00. also because the programming instructions are defined as hexadecimal numbers: 02 (binary represented by 00000010), which is arranged from lower to higher in the order: 01000000, so the TDI signal from low to high 3 to 10 bits is: 01000000. since the address length of the SPI flash memory 03 is 3 bytes (24 bits), the "000000000000000000000000" of the TDI signal from 11 bits to 34 bits from low to high indicates a 0 address having a length of 3 bytes. Also since the data ff5a to be loaded are binary represented as: 1111111101011010, the low order to the high order is: 0101101011111111, the 16 bits at the highest bit of the TDI signal are: 0101101011111111.

alternatively, the loading system may include a plurality of first loading circuits 02 in series (i.e., x is greater than 1). Referring to fig. 10, the loading system may further include: and the n-x +1 second loading circuits 04 are connected between the TDI pin of the JTAG interface of the controller 01 and the x first loading circuits 02 in series, wherein n is a positive integer, and x is an integer not greater than n + 1.

If the data to be loaded in the SPI flash memories 03 connected to the x first load circuits 02 are the same, the controller 01 may load the SPI flash memories 03 connected to the x first load circuits 02 in parallel, thereby improving the loading efficiency.

The loading of the SPI flash 03 may comprise 3 steps: 1. erasing; 2. programming; 3. and (6) checking. In which both erasing and programming are unidirectional operations and there is no need to read the data returned by the SPI flash 03. Since these two steps are time-consuming, the two steps of erasing and programming can be performed in parallel, so that the time taken to load the SPI flash memory 03 can be saved.

For example, assume that the erase step takes 3 minutes, the program step takes 1 minute, and the verify step takes 1 minute. If the loading system includes 8 first loading circuits 02 (i.e., x is 8), the time taken to serially load the SPI flash memory 03 connected to each first loading circuit 02 is: (3+1+1) × 8 ═ 40 minutes. If the SPI flash memories 03 connected to the 8 first loading circuits 02 are loaded in parallel, the time taken is: 3+1+1 × 8 ═ 12 minutes. It can be seen that the loading time is reduced by 70%, and the loading efficiency is greatly improved.

When performing parallel loading, the controller 01 may send a parallel loading instruction to the x first loading circuits 02 respectively, where the parallel loading instruction is used to instruct the 1 st to x-1 st first loading circuits 02 of the x first loading circuits 02 to communicate the TDI pin and the TDO pin of the JTAG circuit 021 thereof. Referring to fig. 6, the bypass register 021d1 in the first load circuit 02 may communicate the TDI pin and the TDO pin of the JTAG circuit 021 in response to the parallel load instruction, so as to implement transparent transmission of the TDI signal.

Referring to the bold black line in fig. 6, the transmission path of the data to be loaded sent by the controller 01 in each of the 1 st to x-1 st first loading circuits 02 includes two:

route 1: TDI pin → bypass register 021d1 → TDO pin;

route 2: TDI pin → timing conversion circuit 024 → channel selection circuit 023 → SPI flash memory 03.

The path 1 is capable of transmitting data to be loaded to the next first loading circuit 02. The above path 2 can realize writing of data to the SPI flash memory 03.

As shown in fig. 16, in the scenario of parallel loading, the 1 st to x-1 st first loading circuits 02 in the loading system may all transmit data to be loaded, which is sent by the controller 01, through the bypass register, and each time the data is transmitted through takes 1 clock cycle. Moreover, each of the x first loading circuits 02 may load data to be loaded, where a loading time duration is j clock cycles, and a value of the j is determined by a length of the data to be loaded.

It is understood that, in the embodiment of the present application, the xth first load circuit 02 may also communicate the TDI pin of the JTAG circuit 021 with the TDO pin in response to the parallel load instruction, so as to implement transparent transmission of the TDI signal.

The loading system comprises: the scenario that x first loading circuits 02 are connected in series, and n-x +1 second loading circuits 04 are connected in series between the TDI pin of the controller 01 and the x first loading circuits 02, the process of the controller 01 loading the x first loading circuits 02 in parallel can be described by the following pseudo flow in SVF format:

"valid data" refers to a data stream formed by combining programming instructions and data to be loaded, and "M + N" represents the length of the data stream. Where M represents the length of the data to be loaded, and may be, for example: 2048, mixing the two solutions; n represents the length of the programming instruction.

Taking as an example that the loading system includes 3 first loading circuits 02 connected in series, and 1 second loading circuit 04 is connected in series between the TDI pin of the JTAG interface of the controller 01 and the 3 first loading circuits 02, and 1 third loading circuit 05 is connected in series between the TDI pin of the first loading circuit 02 and the controller 01, that is, x is equal to n is equal to 3, and m is equal to 1, a process of the controller 01 loading the SPI flash memories 03 connected to the 3 first loading circuits 02 in parallel will be described. Assuming that the IR in each loading circuit is 4 bits long, the first configuration register 025 is 8 bits long, the address length of the SPI flash 03 is 3 bytes (i.e., 24 bits), and the command length of the SPI flash 03 is 8 bits. If the strobe instruction is defined as a hexadecimal number: 2, the first configuration instruction is defined as a hexadecimal number 02, the parallel load instruction is defined as a hexadecimal number 4, the bypass instruction is defined as a hexadecimal number f, the erase instruction is defined as a hexadecimal number C7, and the program instruction is defined as a hexadecimal number 02. When the controller 01 loads the SPI flash 03 connected to the first loading circuit 02, the executed SVF file may be:

wherein, the parallel load instruction is defined as hexadecimal number: 4 (binary: 0100), since the parallel load instruction is arranged from low to high bits in the order: 0010 (2 is denoted in the 16 th notation), so the load instruction in the SVF file may be f222f, and the controller 01 may issue a parallel load instruction 4 to the 3 first load circuits 02 based on the SVF file.

After issuing a first configuration instruction to a first configuration register in the 3 first loading circuits 02: when 02, 0808080, the instruction value is configured in the SVF file as hexadecimal number, the instruction value length is 25 bits, and the binary expression is as follows: 0100000001000000010000000. since the 3 first load circuits 02 are preceded by 1 second load circuit 04, for the first configuration register 025 in the 3 first load circuits 02, it actually reads an instruction with a high 24bit of 0100000001000000010000000: 010000000100000001000000. the SVF file parser reads the instructions in the SVF file from the lower bits to the upper bits, and 010000000100000001000000 reads from the lower bits to the upper bits as follows: 000000100000001000000010 (i.e., hexadecimal number: 020202), so that it is possible to issue the first configuration instructions to all the first configuration registers in the 3 first loading circuits 02: 02.

similarly, the controller 01 issues an erase command to the SPI flash 03 connected to the first load circuit 02: at C7, the instruction value of the scrub instruction in the SVF file is hexadecimal number: 1c7c7c6, instruction value length 25bit, binary representation: 1110001111100011111000110. since the 3 first load circuits 02 are preceded by 1 second load circuit 04, for the SPI flash 03 to which the 3 first load circuits 02 are connected, the actual read instruction value is high 24bit of 1110001111100011111000110: 111000111110001111100011. the SVF file parser reads the instructions in the SVF file from the lower bits to the upper bits, and 111000111110001111100011 reads from the lower bits to the upper bits as follows: 110001111100011111000111 (i.e., hexadecimal number: c7c7c7), so that it is possible to issue the erase command c7 to all the 3 SPI flash memories 03 to which the first load circuit 02 is connected.

The TDI signal for writing the data ff5a to be loaded to the SPI flash 03 is represented as: 0b5fe00000040, length 49bit, binary representation: 0101101011111111000000000000000000000000010000000. because the first load circuit 02 is preceded by 1 second load circuit 04, the TDI signal needs to be delayed by 1 clock cycle, and therefore the lowest 1bit of the TDI signal is: 0. also because the programming instructions are defined as hexadecimal numbers: 02 (binary represented by 00000010), which is arranged from lower to higher in the order: 01000000, so the lower 2 to 9 bits of the TDI signal are: 01000000. since the address length of the SPI flash memory 03 is 3 bytes (24 bits), the "000000000000000000000000" indicating 10 bits to 33 bits from low to high of the TDI signal indicates a 0 address having a length of 3 bytes. Also since the data ff5a to be loaded are binary represented as: 1111111101011010, the low order to the high order is: 0101101011111111, the 16 bits at the highest bit of the TDI signal are: 0101101011111111.

optionally, in the loading system, the controller 01 is further configured to send a first configuration instruction to each of the first loading circuits 02 and send a third configuration instruction to the 1 st to x-1 st of the first loading circuits 02, where the first configuration instruction is used to indicate that a first value indicating the n is configured in the first configuration register 025 of the first loading circuit 02, and the third configuration instruction sent to the x-i th first loading circuit 02 is used to indicate that a third value indicating the i is configured in the second configuration register 026 of the x-i th first loading circuit 02, and the i is a positive integer smaller than x.

The timing conversion circuit 024 in the x-i-th first loading circuit 02 may delay the TDI signal provided by the TDI pin by i clock cycles and provide the delayed TDI signal to the MOSI pin according to the third value. And the timing conversion circuit 024 in the xth first loading circuit 02 does not need to delay the TDI signal provided by the TDI pin. Thus, the x first load circuits 02 can be made to load data to the SPI flash memory 03 at the same time.

In summary, the embodiment of the present application provides a loading system, where a first loading circuit in the loading system includes a JTAG circuit and a channel selection circuit, the channel selection circuit has a first SPI, a second SPI, and a third SPI, and the third SPI is used to connect an SPI flash memory. Because each pin of this JTAG circuit can correspond with each pin of this first SPI to be connected, and this JTAG circuit can control this first SPI and third SPI to switch on, consequently realized JTAG interface and SPI's communication. Correspondingly, the controller can be connected with the JTAG circuit in the first loading circuit through the JTAG interface, and can load data to the SPI flash memory when the first SPI and the third SPI of the channel selection circuit are conducted, thereby realizing the out-of-band upgrade of the firmware stored in the SPI flash memory.

And, for the scenario that the loading system comprises a plurality of loading circuits connected in series, and the controller loads the SPI flash memory to which one of the first loading circuits is connected. The controller may configure the configuration register in the first loading circuit so that the timing conversion circuit of the first loading circuit may jump the level of the target CS signal provided to the CS pin from an inactive level to an active level, delay and/or advance by several clock cycles. Therefore, the controller can load the SPI flash memory connected with the first loading circuit in the plurality of loading circuits connected in series, and loading flexibility is effectively improved.

The loading system comprises a plurality of first loading circuits which are connected in series, and the controller loads the SPI flash memories connected with the first loading circuits in parallel. The controller may issue a parallel load instruction to the first load circuit, which in turn may communicate the TDI pin with the TDO pin in response to the parallel load instruction. From this, first load circuit can realize passing through the TDI signal to next first load circuit when to SPI flash memory loading data, and then ensures that the controller can carry out parallel loading to a plurality of first load circuits of establishing ties, has reduced the required time of loading, has promoted loading efficiency.

Based on the above analysis, in the loading system provided by the present application, the controller can directly perform out-of-band upgrade on the SPI flash memory connected to the loading circuit through its JTAG interface. Therefore, the problem that the SPI flash memory cannot be upgraded out of band because an external SPI is not set in a board card (such as a PCIE board card or an OAM module) of the main stream processor can be solved, and the flexibility of firmware upgrading is effectively improved. In addition, the scheme provided by the embodiment of the application can normalize the loading flow of the SPI flash memories connected with the processor board cards of different types, normalize the hardware design of the processor board cards and promote the standardization of the software and hardware design of the processor board cards. In addition, because the channel selection circuit (i.e., the MUX) can be integrated in the loading circuit in the solution provided by the embodiment of the present application, it is not necessary to additionally set the MUX on the processor board card when the SPI flash memory is upgraded out of band, so that the layout space of the processor board card can be saved, and the hardware design cost can be reduced.

Optionally, each loading circuit in the loading system provided in the embodiment of the present application may be an Integrated Circuit (IC), an application-specific integrated circuit (ASIC), or a Programmable Logic Device (PLD). The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.

In a scenario where the loading circuit is an IC (i.e., a chip), the loading circuit may be a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a neural-Network Processing Unit (NPU), an Image Processing Unit (IPU), a Tensor Processing Unit (TPU), or the like.

The above embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, the above-described embodiments may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded or executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains one or more collections of available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium. The semiconductor medium may be a Solid State Drive (SSD).

The terms "first," "second," and the like in this application are used for distinguishing between similar items and items that have substantially the same function or similar functionality, and it should be understood that "first," "second," and "nth" do not have any logical or temporal dependency or limitation on the number or order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first configuration register may be referred to as a second configuration register, and similarly, a second configuration register may be referred to as a first configuration register, without departing from the scope of the various described examples.

The term "at least one" is used herein to mean one or more, and the term "plurality" is used herein to mean two or more, e.g., multiple load circuits refers to two or more load circuits. The terms "system" and "network" are often used interchangeably herein.

The above description is only an alternative embodiment of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, and these modifications or substitutions should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A loading circuit, wherein the loading circuit comprises: joint test action group JTAG circuit, flash memory controller, and channel selection circuit; the channel selection circuit is provided with a first Serial Peripheral Interface (SPI), a second SPI and a third SPI, the second SPI is connected with the flash memory controller, and the third SPI is used for connecting an SPI flash memory;

the JTAG circuit is used for controlling the first SPI and the third SPI of the channel selection circuit to be conducted, or controlling the second SPI and the third SPI to be conducted;

moreover, a test clock pin of the JTAG circuit is connected with a serial clock pin in the first SPI, a test data input pin of the JTAG circuit is connected with a master transmitting and receiving pin and a slave transmitting and receiving pin in the first SPI, a test data output pin of the JTAG circuit is connected with a master transmitting and receiving pin and a slave transmitting and receiving pin in the first SPI, and a test access port controller of the JTAG circuit is connected with a chip selection pin in the first SPI;

and after the test access port controller is in a shift data register state, jumping the level of a target chip selection signal provided to the chip selection pin from an invalid level to an active level.

2. The loading circuit of claim 1, wherein the JTAG circuit is configured to control the first SPI and the third SPI to be turned on according to a received load instruction.

3. The load circuit of claim 2, wherein the load instruction is a parallel load instruction;

and the JTAG circuit is also used for communicating the test data input pin with the test data output pin according to the loading instruction.

4. The loading circuit according to any of claims 1 to 3, wherein the level of the target chip select signal provided to the chip select pin is changed from an inactive level to an active level at a first target jump edge of the test clock pin after the test access port controller is in the shift data register state;

at the first target jump edge of the test clock pin after the test access port controller finishes shifting the state of the data register, the level of a target chip selection signal provided for the chip selection pin is changed from an active level jump to an inactive level;

and the target jump edge is a rising edge or a falling edge.

5. The load circuit of claim 4, wherein the JTAG circuit is configured to provide the target chip select signal to the chip select pin;

alternatively, the loading circuit further comprises: the test access port controller is connected with the chip selection pin through the time sequence conversion circuit; the time sequence conversion circuit is used for providing the target chip selection signal for the chip selection pin according to the state of the test access port controller and the level of the test clock pin.

6. The loading circuit of any of claims 1 to 3, further comprising: the test access port controller is connected with the chip selection pin through the time sequence conversion circuit;

the JTAG circuit is used for providing an initial chip selection signal for the time sequence conversion circuit, wherein, at a first target jump edge of the test clock pin after the test access port controller is in a shift data register state, the level of the initial chip selection signal is adjusted from an invalid level to an active level, at the first target jump edge of the test clock pin after the test access port controller finishes the shift data register state, the level of the initial chip selection signal is adjusted from the active level to the invalid level, and the target jump edge is a rising edge or a falling edge;

the time sequence conversion circuit is used for carrying out time sequence conversion on the initial chip selection signal to obtain a target chip selection signal and providing the target chip selection signal for the chip selection pin;

the time when the level of the target chip selection signal jumps from the invalid level to the valid level is delayed by n clock cycles relative to the time when the level of the initial chip selection signal jumps from the invalid level to the valid level; and/or the time when the level of the target chip selection signal jumps from the active level to the inactive level is m clock cycles ahead of the time when the level of the initial chip selection signal jumps from the active level to the inactive level; and n and m are both positive integers.

7. The loading circuit of claim 6, wherein the loading circuit further comprises: a first configuration register coupled to the timing conversion circuit, the first configuration register having a first value configured therein for indicating the n;

and the time sequence conversion circuit is used for delaying the moment of jumping the initial chip selection signal from the invalid level to the valid level by n clock cycles according to the first numerical value.

8. The loading circuit of claim 7, wherein the first configuration register is further configured with a second value indicating a duration of time that the target chip select signal is at an active level;

and the time sequence conversion circuit is used for advancing the time when the initial chip selection signal is changed from the effective level to the ineffective level by m clock cycles according to the second numerical value.

9. The loading circuit of any of claims 6 to 8, wherein the test data input pin is connected to a master slave receive pin in the first SPI through the timing conversion circuit;

the time sequence conversion circuit is further configured to delay a test data input signal provided by the test data input pin by i clock cycles and provide the delayed test data input signal to the master-slave receiving pin, where i is a positive integer not greater than n.

10. The loading circuit of claim 9, wherein the loading circuit further comprises: a second configuration register coupled to the timing conversion circuit, the second configuration register having a third value configured therein for indicating the i;

and the time sequence conversion circuit is used for delaying the test data input signal provided by the test data input pin by i clock cycles and providing the delayed test data input signal to the master-slave receiving pin according to the third value.

11. A loading method applied to the loading circuit according to any one of claims 1 to 10; the method comprises the following steps:

conducting a first Serial Peripheral Interface (SPI) and a third SPI of a channel selection circuit in the loading circuit;

and after the test access port controller in the loading circuit is in a shift data register state, adjusting the level of a target chip selection signal provided to the chip selection pin from an invalid level to an active level.

12. The method of claim 11, wherein turning on the first SPI and the third SPI of the channel selection circuitry in the loading circuitry comprises:

and conducting the first SPI and the third SPI of the channel selection circuit in the loading circuit according to the received loading instruction.

13. The method of claim 12, wherein the load instruction is a parallel load instruction; the method further comprises the following steps:

and communicating a test data input pin and a test data output pin of a Joint Test Action Group (JTAG) circuit in the loading circuit according to the loading instruction.

14. The method of any of claims 11 to 13, wherein adjusting the level of a target chip select signal provided to the chip select pin from an inactive level to an active level after the test access port controller is in the shifted data register state in the loading circuit comprises:

adjusting the level of a target chip selection signal provided to a chip selection pin from an invalid level to an effective level at a first target jump edge of a test clock pin after a test access port controller in the loading circuit is in a shift data register state;

the method further comprises the following steps:

adjusting the level of a target chip selection signal provided to the chip selection pin from an active level to an inactive level at a first target jump edge of the test clock pin after the test access port controller finishes shifting the state of the data register;

and the target jump edge is a rising edge or a falling edge.

15. The method of any of claims 11 to 13, wherein adjusting the level of a target chip select signal provided to the chip select pin from an inactive level to an active level after the test access port controller is in the shifted data register state in the loading circuit comprises:

adjusting the level of a target chip selection signal provided to the chip selection pin from an invalid level to an effective level at the nth target jump edge of the test clock pin after the test access port controller is in the state of the shift data register in the loading circuit;

and/or, the method further comprises: in the loading circuit, the level of a target chip selection signal provided to the chip selection pin is changed from an effective level to an ineffective level by an mth target jump edge of the test clock pin before the test access port controller finishes shifting the state of the data register;

the target jump edge is a rising edge or a falling edge, and both n and m are positive integers.

16. The method of claim 15, further comprising:

and delaying a test data input signal provided by a test data input pin of a JTAG circuit in the loading circuit by i clock cycles and providing the delayed test data input signal to a master transmitting and slave receiving pin of the first SPI, wherein i is a positive integer not greater than n.

17. A loading system, comprising: the device comprises a controller, x first loading circuits and x Serial Peripheral Interface (SPI) flash memories, wherein x is a positive integer;

wherein each of the first loading circuits is a loading circuit as claimed in any one of claims 1 to 10;

the controller is connected with the JTAG circuit in each first loading circuit through a joint test action group JTAG interface, and each SPI flash memory is connected with a third SPI of a channel selection circuit in one first loading circuit;

the controller is configured to send a load instruction and data to the JTAG circuit, where the load instruction is used to instruct the JTAG circuit to connect the first SPI and the third SPI of the channel selection circuit, and to load the data to the SPI flash memory.

18. The loading system of claim 17, wherein x is 1; the loading system further comprises: n second loading circuits connected in series between a test data input pin of a JTAG interface of the controller and the first loading circuit, wherein n is a positive integer;

the controller is further configured to send a first configuration instruction to the first load circuit, where the first configuration instruction is used to indicate that a first value indicating the n is configured in a first configuration register of the first load circuit.

19. The loading system of claim 17 or 18, wherein x is 1; the loading system further comprises: m third loading circuits connected in series between the first loading circuit and a test data output pin of a JTAG interface of the controller, wherein m is a positive integer;

the controller is further configured to determine, according to the number m of the third loading circuits, a duration that a target chip select signal is at an active level, and send a second configuration instruction to the first loading circuit, where the second configuration instruction is further configured to indicate that a second value indicating the duration that the target chip select signal is at the active level is configured in the first configuration register;

the target chip selection signal is a signal received by a chip selection pin of a first SPI in the first loading circuit.

20. The loading system of claim 17, wherein x is greater than 1, and the x first loading circuits are connected in series; the loading system further comprises: n-x +1 second loading circuits connected in series between a test data input pin of a JTAG interface of the controller and the x first loading circuits, wherein n is a positive integer, and x is an integer not greater than n + 1;

the controller is used for carrying out parallel loading on the SPI flash memories connected with the x first loading circuits, the loading instruction is a parallel loading instruction, and the loading instruction is also used for indicating the 1 st to the x-1 st first loading circuits in the x first loading circuits to communicate the test data input pins and the test data output pins of the JTAG circuits of the x first loading circuits;

the controller is further configured to send a first configuration instruction to each of the first load circuits, and send a third configuration instruction to the 1 st to x-1 st first load circuits, where the first configuration instruction is used to indicate that a first value indicating the n is configured in a first configuration register of the first load circuit, and the third configuration instruction sent to the x-i th first load circuit is used to indicate that a third value indicating the i is configured in a second configuration register of the x-i th first load circuit, and i is a positive integer smaller than x.