CN114461567B - Data processing equipment - Google Patents
Data processing equipment Download PDFInfo
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- CN114461567B CN114461567B CN202210198064.1A CN202210198064A CN114461567B CN 114461567 B CN114461567 B CN 114461567B CN 202210198064 A CN202210198064 A CN 202210198064A CN 114461567 B CN114461567 B CN 114461567B
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- 238000006243 chemical reaction Methods 0.000 claims description 15
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
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- Information Transfer Systems (AREA)
Abstract
In order to save the pin number on a logic processing chip, the application can connect a plurality of parallel-to-serial chips through a first serial port of the logic processing chip and connect a plurality of serial-to-parallel chips through a second serial port, so that input data of a plurality of input interfaces provided by the parallel-to-serial chips can be input into the logic processing chip through the first serial port, and the logic processing chip can output a large amount of data to a designated output interface through the second serial port.
Description
Technical Field
The present invention relates to the field of chips, and in particular, to a data processing apparatus.
Background
In the big data era, there are various data processing devices (such as PLC (Programmable Logic Controller, programmable logic controller) and the like), and many data processing devices currently have a great demand for input interfaces and output interfaces, but the number of input interfaces and output interfaces that can be provided by a logic processing chip (for performing logic processing on data) in the data processing device itself is limited, and how to expand the number of input/output interfaces IO of the data processing device with low cost and small space is a technical problem to be solved.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The application aims to provide the data processing equipment, and the parallel-serial chip and the serial-parallel chip have the characteristics of small volume and low cost, so that the application not only expands the IO number of the data processing equipment, but also saves the cost and controls the volume of the data processing equipment.
To solve the above technical problem, the present invention provides a data processing apparatus, including:
the main control device is used for sending the data to be processed to the logic processing chip;
The logic processing chip is connected with the main control device and is used for providing a plurality of input interfaces and a plurality of output interfaces, carrying out specified logic processing on the data to be processed, then sending the data to be processed to the specified output interface, carrying out specified logic processing on the data received from the input interface, and then sending the data to the specified main control device or the specified output interface;
The parallel-serial conversion chips are connected in series with each other and one end of each parallel-serial conversion chip is connected with a first serial port of the logic processing chip, and are used for converting parallel data input from a plurality of input interfaces provided by the parallel-serial conversion chips into serial data and then transmitting the serial data to the logic processing chip;
And the serial-to-parallel conversion chips are connected in series and one end of each serial-to-parallel conversion chip is connected with the second serial port of the logic processing chip and is used for converting serial data sent by the logic processing chip into parallel data and outputting the parallel data through a plurality of output interfaces provided by the logic processing chip.
Preferably, the data processing apparatus further comprises:
And the level setting circuit is connected with the input interfaces provided by the parallel-serial chip nearest to the logic processing chip and is used for setting the level combination of each connected input interface to be a preset combination so as to determine the total number of the input interfaces provided by the parallel-serial chip and the total number of the output interfaces provided by the serial-parallel chip through the preset combination.
Preferably, the level setting circuit includes a level pull-up circuit and a level pull-down circuit.
Preferably, the master control device is an ARM processor.
Preferably, the logic processing chip is a field programmable gate array FPGA or a complex programmable logic device CPLD.
Preferably, the first serial port and the second serial port are of the same type.
Preferably, the first serial port and the second serial port are serial peripheral interface SPI interfaces.
Preferably, the data processing device is a programmable logic controller PLC.
In order to save the pin number on the logic processing chip, the application can connect a plurality of parallel-to-serial chips through the first serial port of the logic processing chip and connect a plurality of serial-to-parallel chips through the second serial port, so that the input data of a plurality of input interfaces provided by the parallel-to-serial chips can be input into the logic processing chip through the first serial port, and the logic processing chip can output a large amount of data to a designated output interface through the second serial port.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a data processing apparatus according to the present invention;
FIG. 2 is a schematic diagram of another data processing apparatus according to the present invention;
fig. 3 is a schematic diagram of a parallel-serial chip according to the present invention;
fig. 4 is a schematic diagram of a serial-parallel connection chip according to the present invention.
Detailed Description
The core of the application is to provide a data processing device, because the parallel-serial chip and the serial-parallel chip have the characteristics of small volume and low cost, the application not only expands the IO number of the data processing device, but also saves the cost and controls the volume of the data processing device.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a data processing apparatus according to the present invention, where the data processing apparatus includes:
The main control device 1 is used for sending the data to be processed to the logic processing chip 2;
The logic processing chip 2 is connected with the main control device 1 and is used for providing a plurality of input interfaces and a plurality of output interfaces, sending the data to be processed to the designated output interfaces after designated logic processing is carried out on the data received from the input interfaces, and sending the data to the designated main control device 1 or the designated output interfaces after designated logic processing is carried out on the data received from the input interfaces;
A plurality of parallel-serial chips 3 connected in series with each other and having one end connected to the first serial port of the logic processing chip 2, for converting parallel data input from a plurality of input interfaces provided by the parallel-serial chips into serial data and transmitting the serial data to the logic processing chip 2;
And the serial-to-parallel conversion chips 4 are connected in series with each other and one end of each serial-to-parallel conversion chip is connected with the second serial port of the logic processing chip 2, and are used for converting serial data sent by the logic processing chip 2 into parallel data and outputting the parallel data through a plurality of output interfaces provided by the serial-to-parallel conversion chips.
Specifically, considering the technical problems in the background art and considering the limited pin number on the logic processing chip 2, the serial port is used for externally connecting the serial-parallel serial chip 3 and the serial-parallel chip 4, so that a large number of expansion of the IO interfaces can be completed without occupying too many pins of the logic processing chip 2, wherein the data of a plurality of input interfaces provided by the serial-parallel chip 3 are parallel data, namely, the data of each input interface are independent, so that the input interface of the data processing device is expanded, and for the serial-parallel chip 4, the serial data output by the logic processing chip 2 can be received and converted into parallel data and output through a plurality of output interfaces provided by the serial-parallel chip 4, and the data of each output interface are independent, so that the output interface of the data processing device is expanded.
Specifically, the number of the parallel-serial chips 3 and the number of the serial-parallel chips 4 may be set autonomously, for example, 8 or the like are set, which is not limited in this embodiment of the present invention.
It should be noted that, the IO interface provided by the logic processing chip 2 may be a high-speed IO interface, and the IO interfaces provided by the parallel-serial chip 3 and the serial-parallel chip 4 may be low-speed IO interfaces, so that most of interface requirements can be satisfied and the stability is relatively strong.
In order to save the pin number on the logic processing chip, the application can connect a plurality of parallel-to-serial chips through the first serial port of the logic processing chip and connect a plurality of serial-to-parallel chips through the second serial port, so that the input data of a plurality of input interfaces provided by the parallel-to-serial chips can be input into the logic processing chip through the first serial port, and the logic processing chip can output a large amount of data to a designated output interface through the second serial port.
For better illustrating the embodiments of the present invention, please refer to fig. 2 to 4, wherein fig. 2 is a schematic diagram of another data processing apparatus according to the present invention; fig. 3 is a schematic wiring diagram of a parallel-serial chip 3 according to the present invention; fig. 4 is a schematic wiring diagram of a serial-parallel chip 4 according to the present invention, which is based on the above embodiment:
as a preferred embodiment, the data processing apparatus further comprises:
a level setting circuit 5 connected to the input interface provided by the parallel-to-serial chip 3 nearest to the logic processing chip2 for setting the level combinations of the connected respective input interfaces to a preset combination so as to determine the total number of input interfaces provided by the parallel-to-serial chip 3 and the total number of output interfaces provided by the serial-to-parallel chip 4 by the preset combination.
Specifically, in order to facilitate different data processing devices to know the number of IO interfaces expanded by the serial-parallel chip 4 and the parallel-serial chip 3, in the embodiment of the present invention, the level setting circuit 5 may also set the level combination of the input interface provided by the parallel-serial chip 3 nearest to the logic processing chip 2 to be a preset combination, so that the logic processing chip 2 can determine the total number of input interfaces provided by the parallel-serial chip 3 and the total number of output interfaces provided by the serial-parallel chip 4 through the preset combination of the first several bits of the received serial data.
In fig. 3, the definition of each pin is as follows:
CLK: a clock input; CLK INH: a data output enable; SH/LD: a data loading bit; SER: serial input; A-H: parallel input: QH: serial output; ' QH: the serial output is reversed.
In fig. 4, the definition of each pin is as follows:
SRCLK: a clock input; RCLK: a data latch clock; OE: outputting an enable; SRCLR: a reset pin; SER: serial input; QA to QH: parallel output: QH: serial output; ' QH: the serial output is reversed.
As a preferred embodiment, the level setting circuit 5 includes a level pull-up circuit and a level pull-down circuit.
Specifically, the level pull-up circuit and the level pull-down circuit have the advantages of small volume, simple structure, low cost and the like.
Of course, the level setting circuit 5 may be of various types other than the form of the level up-pull circuit and the level down-pull circuit, and the embodiment of the present invention is not limited herein.
As a preferred embodiment, the master device 1 is an ARM processor.
Specifically, the ARM processor has the advantages of high processing capacity, small size, low cost and the like.
Of course, the main control device 1 may be of various types other than an ARM processor, and the embodiments of the present invention are not limited herein.
As a preferred embodiment, the logic processing chip 2 is an FPGA (Field Programmable GATE ARRAY ) or a CPLD (Complex Programmable logic device, complex programmable logic device).
Specifically, the FPGA and the CPLD have the advantages of strong processing capacity, small volume, low cost and the like.
Of course, the logic processing chip 2 may be of other types besides FPGA and CPLD, and the embodiments of the present invention are not limited herein.
As a preferred embodiment, the first serial port and the second serial port are of the same type.
Specifically, the first serial port and the second serial port are set to be of the same type, so that the working efficiency can be improved.
Of course, the first serial port and the second serial port may be set to different types, which is not limited herein.
As a preferred embodiment, the first serial port and the second serial port are SPI (SERIAL PERIPHERAL INTERFACE ) interfaces.
Specifically, the SPI interface has advantages such as transmission speed is fast and stability is strong.
Of course, the first serial port and the second serial port may be other types besides SPI interfaces, such as I2C interfaces, etc., and the embodiments of the present invention are not limited herein.
As a preferred embodiment, the data processing device is a programmable logic controller PLC.
Specifically, the PLC has the advantages of strong data processing capability, long service life and the like.
Of course, the data processing device may be of other types besides a PLC, and embodiments of the present invention are not limited herein.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (2)
1. A data processing apparatus, comprising:
the main control device is used for sending the data to be processed to the logic processing chip;
The logic processing chip is connected with the main control device and is used for providing a plurality of input interfaces and a plurality of output interfaces, carrying out specified logic processing on the data to be processed, then sending the data to be processed to the specified output interface, carrying out specified logic processing on the data received from the input interface, and then sending the data to the specified main control device or the specified output interface;
The parallel-serial conversion chips are connected in series with each other and one end of each parallel-serial conversion chip is connected with a first serial port of the logic processing chip, and are used for converting parallel data input from a plurality of input interfaces provided by the parallel-serial conversion chips into serial data and then transmitting the serial data to the logic processing chip;
the serial-to-parallel conversion chips are connected in series and one end of each serial-to-parallel conversion chip is connected with the second serial port of the logic processing chip, and the serial-to-parallel conversion chips are used for converting serial data sent by the logic processing chip into parallel data and then outputting the parallel data through a plurality of output interfaces provided by the serial-to-parallel conversion chips;
Taking each input interface of each parallel-serial chip as the input interface of the logic processing chip; and each output interface of each serial-parallel chip is used as the output interface of the logic processing chip;
the data processing apparatus further includes:
A level setting circuit connected to the input interfaces provided by the parallel-to-serial chip nearest to the logic processing chip, for setting a level combination of each connected input interface to a preset combination, so as to determine a total number of input interfaces provided by the parallel-to-serial chip and a total number of output interfaces provided by the serial-to-parallel chip through the preset combination;
The first serial port and the second serial port are of the same type;
The level setting circuit comprises a level pull-up circuit and a level pull-down circuit;
the main control device is an ARM processor;
the logic processing chip is a Field Programmable Gate Array (FPGA) or a Complex Programmable Logic Device (CPLD);
the data processing device is a programmable logic controller PLC.
2. The data processing device of claim 1, wherein the first serial port and the second serial port are serial peripheral interface, SPI, interfaces.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210198064.1A CN114461567B (en) | 2022-03-01 | 2022-03-01 | Data processing equipment |
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| CN202210198064.1A CN114461567B (en) | 2022-03-01 | 2022-03-01 | Data processing equipment |
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| CN114461567A CN114461567A (en) | 2022-05-10 |
| CN114461567B true CN114461567B (en) | 2024-10-18 |
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Citations (2)
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| CN204496211U (en) * | 2015-01-23 | 2015-07-22 | 安徽白鹭电子科技有限公司 | A kind of expansion I/O port circuit with standard spi bus interface |
| CN206877319U (en) * | 2017-04-05 | 2018-01-12 | 大族激光科技产业集团股份有限公司 | A kind of operation of serial-port system based on numerical control control |
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| JPH1075183A (en) * | 1996-08-29 | 1998-03-17 | Nippon Telegr & Teleph Corp <Ntt> | Serial/parallel data conversion circuit |
| JP3871813B2 (en) * | 1998-08-10 | 2007-01-24 | 株式会社ルネサステクノロジ | Multi-port memory, data processor and data processing system |
| US8203976B2 (en) * | 2007-01-16 | 2012-06-19 | Ricoh Company, Ltd. | Interface device and image forming apparatus |
| CN202084028U (en) * | 2011-06-03 | 2011-12-21 | 南京理工大学 | Modularized multi-serial port expanding device |
| CN102904787A (en) * | 2011-07-27 | 2013-01-30 | 中兴通讯股份有限公司 | Method and device for bridging local bus and transmitting data |
| CN103561118B (en) * | 2013-10-31 | 2016-08-17 | 中国船舶重工集团公司第七二二研究所 | A kind of interface message processing means |
| CN104794093B (en) * | 2015-03-31 | 2017-06-30 | 南通艾利特自动化有限公司 | A kind of spi bus expanded circuit with ID identification functions |
| CN213581791U (en) * | 2020-10-28 | 2021-06-29 | 北京宏光星宇科技发展有限公司 | Circuit for simulating SPI interface to expand input and output interfaces |
| CN214011973U (en) * | 2021-01-18 | 2021-08-20 | 普联技术有限公司 | Serial port expansion device and computer equipment |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN204496211U (en) * | 2015-01-23 | 2015-07-22 | 安徽白鹭电子科技有限公司 | A kind of expansion I/O port circuit with standard spi bus interface |
| CN206877319U (en) * | 2017-04-05 | 2018-01-12 | 大族激光科技产业集团股份有限公司 | A kind of operation of serial-port system based on numerical control control |
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