CN114170967B - Array substrate, manufacturing method of array substrate and display panel - Google Patents
Array substrate, manufacturing method of array substrate and display panel Download PDFInfo
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- CN114170967B CN114170967B CN202111576893.0A CN202111576893A CN114170967B CN 114170967 B CN114170967 B CN 114170967B CN 202111576893 A CN202111576893 A CN 202111576893A CN 114170967 B CN114170967 B CN 114170967B
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- 229910052733 gallium Inorganic materials 0.000 description 2
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- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Electroluminescent Light Sources (AREA)
- Control Of El Displays (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate, a manufacturing method of the array substrate and a display panel. The array substrate includes: a substrate; the pixel driving circuit is arranged on the substrate and comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a grid electrode leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor. By setting the threshold voltage of the first transistor to be larger than that of the driving transistor, the leakage current of the first transistor in the off state is smaller, so that the leakage current on the gate leakage path of the driving transistor where the first transistor is located can be reduced, the gate potential holding time of the driving transistor is increased, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate and a display panel.
Background
An Active Matrix Organic LIGHT EMITTING Diode (AMOLED) display panel has been widely used in the display field because it is superior to a liquid crystal display panel in terms of display color saturation, power consumption, bending, and the like. In the process of displaying an AMOLED display panel, the pixel driving circuit drives the light emitting device to emit light. In the prior art, the pixel driving circuit includes a driving transistor, and the gate of the driving transistor has a leakage current phenomenon, so that the stability is relatively poor, and the light-emitting brightness of the light-emitting device is unstable, thereby affecting the display image quality of the AMOLED display panel.
Disclosure of Invention
The invention provides an array substrate, a manufacturing method of the array substrate and a display panel, which are used for reducing gate leakage current of a driving transistor, so that display image quality of the display panel is improved.
In a first aspect, an embodiment of the present invention provides an array substrate, including:
A substrate;
The pixel driving circuit is arranged on the substrate and comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a gate leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor.
Optionally, the pixel driving circuit further includes a second transistor, the second transistor being located on a gate leakage path of the driving transistor, a threshold voltage of the second transistor being greater than a threshold voltage of the driving transistor; the second transistor and the first transistor are located on different gate leakage paths of the drive transistor.
Optionally, the pixel driving circuit includes a threshold compensation transistor and an initialization transistor; the grid electrode of the initialization transistor is connected with a first scanning signal input end, the first electrode of the initialization transistor is connected with a reference signal input end, the second electrode of the initialization transistor and the second electrode of the threshold compensation transistor are connected with the grid electrode of the driving transistor, the grid electrode of the threshold compensation transistor is connected with a second scanning signal input end, the first electrode of the threshold compensation transistor is connected with the second electrode of the driving transistor, and the first electrode of the driving transistor is connected with a first voltage input end;
the transistor on the grid leakage path of the driving transistor is a threshold compensation transistor; or the transistor on the gate leakage path of the drive transistor is a gate initialization transistor.
Optionally, the transistor on the gate leakage path of the driving transistor is a double gate transistor.
In a second aspect, an embodiment of the present invention further provides a method for manufacturing an array substrate, including:
Forming a pixel driving circuit on a substrate; the pixel driving circuit comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a grid leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor.
Optionally, forming a pixel driving circuit on the substrate includes:
Forming a semiconductor layer on the substrate;
Patterning the semiconductor layer to form a first channel region and at least one second channel region; wherein the first channel region is used for forming a channel of the driving transistor, and at least one second channel region is used for forming a channel of the first transistor;
Performing ion implantation on the second channel region to enable the ion concentration of the second channel region to be larger than that of the first channel region;
The driving transistor and the first transistor are formed based on the first channel region and the second channel region, respectively.
Optionally, the pixel driving circuit includes a second transistor, the second transistor being located on a gate leakage path of the driving transistor, the semiconductor layer being patterned to form a first channel region and at least one second channel region when the second transistor and the first transistor are located on different gate leakage paths of the driving transistor, including:
patterning the semiconductor layer to form a first channel region and two second channel regions; wherein the first channel region is used for forming a channel of the driving transistor, one of the second channel regions is used for forming a channel of the first transistor, and one of the second channel regions is used for forming a channel of the second transistor;
Forming the driving transistor and the first transistor based on the first channel region and the second channel region, respectively, includes:
The driving transistor, the first transistor, and the second transistor are formed based on the first channel region and the second channel region, respectively.
Optionally, performing ion implantation on the second channel region to make the ion concentration of the second channel region greater than that of the first channel region, including:
And shielding the first channel region, and performing ion implantation on the second channel region.
Optionally, after masking the first channel region and performing ion implantation on the second channel region, the method further includes:
masking the second channel region and performing ion implantation on the first channel region; wherein the ion implantation concentration of the first channel region is smaller than the ion implantation concentration of the second channel region.
In a third aspect, an embodiment of the present invention further provides a display panel, including the array substrate provided in the first aspect.
According to the technical scheme, the threshold voltage of the first transistor is set to be larger than that of the driving transistor, so that the leakage current of the first transistor in the off state is smaller, the leakage current on the gate leakage path of the driving transistor where the first transistor is located can be reduced, the gate potential holding time of the driving transistor is prolonged, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
Drawings
Fig. 1 is a schematic diagram of a pixel driving circuit according to the prior art;
FIG. 2 is a schematic diagram of another pixel driving circuit according to the prior art;
Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
fig. 4 is an electrical schematic diagram of a P-type transistor according to an embodiment of the present invention;
FIG. 5 is a schematic diagram showing a relationship between Flicker of a display panel and a threshold voltage Vth of a first transistor according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention;
fig. 7 is a schematic diagram of a structure of another pixel driving circuit according to an embodiment of the invention;
Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
FIG. 9 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 10 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention;
Fig. 11 is a schematic structural diagram of an array substrate corresponding to step S20 of the method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of an array substrate corresponding to step S21 of the method for manufacturing an array substrate according to the embodiment of the present invention;
Fig. 13 is a schematic structural diagram of an array substrate corresponding to step S22 of the method for manufacturing an array substrate according to the embodiment of the present invention;
FIG. 14 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention;
Fig. 15 is a schematic structural diagram of an array substrate corresponding to step S33 of the method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 16 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of an array substrate corresponding to step S41 of the method for manufacturing an array substrate according to the embodiment of the present invention;
fig. 18 is a schematic structural diagram of an array substrate corresponding to step S42 of the method for manufacturing an array substrate according to an embodiment of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present invention are shown in the drawings.
Fig. 1 is a schematic diagram of a pixel driving circuit according to the prior art. As shown in fig. 1, the pixel driving circuit includes a switching transistor M0, a compensation transistor M1, a light emission control transistor M2, an initialization transistor M3, a driving transistor N0, and a storage capacitor Cs. The initializing transistor M3 has a gate connected to the first Scan line Scan1 to receive the first Scan signal, a source connected to the initializing signal line to receive the initializing signal Vref, and a drain connected to the gate of the driving transistor N0. The gate of the switching transistor M0 and the gate of the compensating transistor M1 are connected to the second Scan line Scan2 to receive the second Scan signal, the source is connected to the data line to receive the data signal Vdata, and the drain is connected to the source of the driving transistor N0. The grid electrode of the driving transistor N0 is electrically connected with one end of the storage capacitor Cs and the source electrode of the compensation transistor M1, the source electrode is connected to the drain electrode of the light-emitting control transistor M2, and the drain electrode is connected to the positive electrode end of the OLED and the drain electrode of the compensation transistor M1; the other ends of the source of the light emission control transistor M2 and the storage capacitor Cs are connected to a first voltage terminal to receive a first voltage Vdd (high voltage), the gate of the light emission control transistor M2 is electrically connected to the third Scan signal line Scan3, and the negative terminal of the OLED is connected to a second voltage terminal to receive a second voltage Vss (low voltage, for example, ground voltage). In the process of operating the pixel driving circuit, the first Scan signal may be applied through the first Scan line Scan1 to turn on the initialization transistor M3, and the initialization signal Vref provided by the initialization signal line may initialize the gate of the driving transistor N0 after passing through the initialization transistor M3. Then, the second Scan signal is applied through the second Scan line Scan2 to turn on the switching transistor M0 and the compensating transistor M1, and at this time, the data signal Vdata supplied from the data driving circuit through the data line charges the storage capacitor Cs through the switching transistor M0 and the compensating transistor M1, thereby storing the difference between the data signal Vdata and the threshold voltage of the driving transistor N0 in the storage capacitor Cs, and when the light emission control transistor M2 is turned on by the third Scan signal applied through the third Scan line Scan3, the driving transistor N0 forms a driving current to drive the OLED to emit light.
In the above operation, when the driving transistor N0 forms a driving current to drive the OLED to emit light, the compensation transistor M1 and the initialization transistor M3 are turned off, so as to avoid the unstable driving current formed by the driving transistor N0 due to the gate leakage current of the driving transistor N0. Due to the limitation of the transistor structure, the compensation transistor M1 and the initialization transistor M3 still have a certain leakage current when turned off, which results in unstable driving current formed by the driving transistor N0, and the brightness of the OLED light emission changes, which affects the display image quality of the display panel. Fig. 2 is a schematic diagram of another pixel driving circuit according to the prior art. As shown in fig. 2, the compensation transistor M1 and the initialization transistor M3 may be further configured as a dual-gate transistor connected in series, and at this time, the gate leakage current of the driving transistor N0 may be partially reduced, and when the pixel driving circuit operates at a low refresh rate, the gate leakage current of the driving transistor N0 is still relatively obvious, which is easy to cause unstable brightness of the OLED light emission. In addition, the compensation transistor M1 and the initialization transistor M3 may be further configured as indium gallium zinc oxide (indium gallium zinc oxide, IGZO) transistors, for reducing the gate leakage current of the driving transistor N0, where the occupied space of the compensation transistor M1 and the initialization transistor M3 is relatively large, so that the occupied space of the pixel driving circuit is relatively large, which is not beneficial to improving the pixel density of the display panel.
Aiming at the technical problems, the embodiment of the invention provides an array substrate. Fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present invention. As shown in fig. 3, the array substrate includes:
A substrate 110;
the pixel driving circuit is disposed on the substrate 110, and the pixel driving circuit includes a driving transistor Tdr and a first transistor T1, wherein the first transistor T1 is located on a gate-drain path of the driving transistor Tdr, and a threshold voltage of the first transistor T1 is greater than a threshold voltage of the driving transistor Tdr.
Specifically, the substrate 110 is used to carry the pixel driving circuit. The substrate 110 may be a flexible substrate or a rigid substrate. Illustratively, the flexible substrate may be a Polyimide (PI) substrate, and the rigid substrate may be a glass substrate. When the array substrate is used for forming a display panel, the display panel comprises a light-emitting unit, and the pixel driving circuit is used for driving the light-emitting unit to emit light. When the pixel driving circuit drives the light emitting unit to emit light, the gate leakage path of the driving transistor Tdr is a path through which leakage current of the gate of the driving transistor Tdr flows when the pixel driving circuit supplies driving current to the light emitting unit. The gate drain path of the driving transistor Tdr may include a plurality of, for example, when the pixel driving circuit includes a gate initializing transistor, the gate drain path of the driving transistor Tdr includes an initializing transistor, and the first transistor T1 may be an initializing transistor. The threshold voltage of the first transistor T1 is greater than the threshold voltage of the driving transistor Tdr, so that the threshold voltage of the first transistor T1 is biased positive with respect to the threshold voltage of the driving transistor Tdr, that is, the threshold voltage of the first transistor T1 is biased positive with respect to the threshold voltages of other transistors in the pixel driving circuit, so that the leakage current of the first transistor T1 when turned off is smaller than the leakage current of other transistors in the pixel driving circuit when turned off. When the first transistor T1 and the driving transistor Tdr are P-type transistors, the threshold voltages of the first transistor T1 and the driving transistor Tdr are smaller than zero. The threshold voltage of the first transistor T1 is greater than the threshold voltage of the driving transistor Tdr, that is, the absolute value of the threshold voltage of the first transistor T1 is smaller than the absolute value of the threshold voltage of the driving transistor Tdr.
The first transistor T1 is exemplified as a P-type transistor. Table 1 shows a relationship between the threshold voltage and the leakage current of the transistor according to the embodiment of the invention, as shown in Table 1, when the threshold voltage Vth of the transistor is biased from-4.52V to-1.30V, the leakage current Ioff of the transistor is reduced from 6.25e-11A to 7.79e-12A, thereby illustrating that the leakage current of the first transistor T1 is reduced when the threshold voltage of the first transistor T1 is biased.
Table 1a table of threshold voltage versus leakage current of transistors
| Threshold voltage Vth (V) | Leakage current Ioff (A) |
| -4.52 | 6.25e-11 |
| -2.89 | 2.13e-11 |
| -1.30 | 7.79e-12 |
Fig. 4 is an electrical schematic diagram of a P-type transistor according to an embodiment of the present invention. Wherein, the abscissa is the gate voltage, the ordinate is the driving current of the transistor, and curve 1, curve 2 and curve 3 correspond to different transistors respectively. As can be seen from fig. 4, when the gate voltage of the transistor is at a low level, each transistor is turned on, and the on current is relatively large. When the gate voltage of the transistor is changed from low level to high level, the transistor is switched from on state to off state, and the voltages corresponding to the transistors of curve 1, curve 2 and curve 3 are different, i.e. the threshold voltages corresponding to the transistors of curve 1, curve 2 and curve 3 are different. As can be seen from the lowest point of the curve, the threshold voltage of the transistor corresponding to the curve 1 is smaller than the threshold voltage of the transistor corresponding to the curve 2, that is, the threshold voltage of the transistor corresponding to the curve 2 is positive with respect to the threshold voltage of the transistor corresponding to the curve 1, and the threshold voltage of the transistor corresponding to the curve 2 is smaller than the threshold voltage of the transistor corresponding to the curve 3, that is, the threshold voltage of the transistor corresponding to the curve 3 is positive with respect to the threshold voltage of the transistor corresponding to the curve 2. Meanwhile, when the gate voltage of the transistor is at a high level and the control transistor is turned off, for example, when the gate voltage of the transistor is 7V, the leakage current of the transistor corresponding to the curve 3 is smaller than the leakage current of the transistor corresponding to the curve 2, and the leakage current of the transistor corresponding to the curve 2 is smaller than the leakage current of the transistor corresponding to the curve 1. From this, it can be seen that when the threshold voltage of the first transistor T1 is deviated from the threshold voltages of the other transistors in the pixel driving circuit, the leakage current of the first transistor T1 when turned off is smaller than the leakage current of the other transistors in the pixel driving circuit when turned off.
In addition, the first transistor T1 is located on the gate leakage path of the driving transistor Tdr, so that the leakage current on the gate leakage path of the driving transistor Tdr can be reduced when the first transistor T1 is turned off, the driving current formed by the driving transistor Tdr is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved. Fig. 5 is a schematic diagram illustrating a relationship between Flicker and a threshold voltage Vth of a first transistor of a display panel according to an embodiment of the present invention. As shown in fig. 5, when the array substrate is used to form a display panel, the pixel driving circuit drives the light emitting unit in the display panel to emit light, the larger the threshold voltage Vth of the first transistor T1, i.e., the more positive the threshold voltage of the first transistor T1, so that the smaller the gate leakage current of the driving transistor Tdr, the lower the Flicker value of the display panel, i.e., the more slight the Flicker of the display panel, so that the Flicker phenomenon of the display panel can be improved by biasing the threshold voltage of the first transistor T1, thereby improving the display image quality of the display panel.
Fig. 6 is a schematic structural diagram of a pixel driving circuit according to an embodiment of the present invention. As shown in fig. 6, the pixel driving circuit includes a threshold compensation transistor T3 and an initialization transistor T4; the gate of the initialization transistor T4 is connected with the first scanning signal input end S1, the first pole of the initialization transistor T4 is connected with the reference signal input end VREF1, the second pole of the initialization transistor T4 and the second pole of the threshold compensation transistor T3 are connected with the gate of the driving transistor Tdr, the gate of the threshold compensation transistor T3 is connected with the second scanning signal input end S2, the first pole of the threshold compensation transistor T3 is connected with the second pole of the driving transistor Tdr, and the first pole of the driving transistor Tdr is connected with the first voltage input end VDD; the first transistor T1 is a threshold compensation transistor T3 or an initialization transistor T4.
Specifically, as shown in fig. 6, the pixel driving circuit further includes a storage capacitor Cst, a data writing transistor T5, a first light emitting control transistor T6, a second light emitting control transistor T7, and a reset transistor T8, wherein a gate of the data writing transistor T5 is connected to the second scan signal input terminal S2, a first pole of the data writing transistor T5 is connected to the data signal input terminal VDATA, a second pole of the data writing transistor T5 is connected to a first pole of the driving transistor Tdr, a first pole of the driving transistor Tdr is connected to the first voltage input terminal VDD through the first light emitting control transistor T6, a first pole of the storage capacitor Cst is connected to a gate of the driving transistor Tdr, a second pole of the storage capacitor Cst is connected to the first voltage input terminal VDD, a gate of the first light emitting control transistor T6 and a gate of the second light emitting control transistor T7 are connected to the light emitting control signal input terminal EM, a first pole of the second light emitting control transistor T7 is connected to a second pole of the driving transistor Tdr, a first pole of the second light emitting control transistor T7 and a second pole of the reset transistor T8 is connected to the first voltage input terminal VSS 1, and a first voltage input terminal VSS of the reset transistor 1 is connected to the first voltage input terminal VDD 1. In the operation process of the pixel driving circuit, in the light emitting stage, the driving transistor Tdr forms a driving current according to the gate potential, and when the light emitting unit D1 is driven to emit light, the threshold compensation transistor T3 and the initialization transistor T4 are turned off and are located on different gate leakage paths of the driving transistor Tdr. By setting the first transistor T1 as the threshold compensation transistor T3 or the initialization transistor T4, the threshold voltage of the threshold compensation transistor T3 or the initialization transistor T4 is biased, so that the leakage current of the threshold compensation transistor T3 or the initialization transistor T4 can be reduced, and further, the leakage current on the gate leakage path of the driving transistor Tdr can be reduced, thereby improving the flicker phenomenon of the display panel and improving the display image quality of the display panel.
Note that fig. 6 exemplarily shows that the first transistor T1 is a threshold compensation transistor T3, which can reduce the leakage current of the gate of the driving transistor Tdr through the leakage path of the threshold compensation transistor T3. In other embodiments, the first transistor T1 may be the initializing transistor T4, and the leakage current of the gate of the driving transistor Tdr passing through the leakage current path of the initializing transistor T4 can be reduced, so as to improve the flicker phenomenon of the display panel.
On the basis of the above technical solutions, with continued reference to fig. 6, the pixel driving circuit further includes a second transistor T2, where the second transistor T2 is located on the gate drain path of the driving transistor Tdr, and the threshold voltage of the second transistor T2 is greater than the threshold voltage of the driving transistor Tdr; the second transistor T2 and the first transistor T1 are located on different gate leakage paths of the driving transistor Tdr.
Specifically, when the pixel driving circuit includes the threshold compensation transistor T3 and the initialization transistor T4, the gate leakage paths of the driving transistor Tdr include two, by setting the first transistor T1 and the second transistor T2 to be located on different gate leakage paths of the driving transistor Tdr, the threshold voltage of the first transistor T1 is biased, so that the leakage current on the leakage path on which the first transistor T1 is located can be reduced, and simultaneously the threshold voltage of the second transistor T2 is biased, the leakage current on the leakage path on which the second transistor T2 is located can be reduced, so that the leakage current on different gate leakage paths of the driving transistor Tdr can be reduced at the same time, and further, the gate leakage current of the driving transistor Tdr can be reduced, so that the flicker phenomenon of the display panel can be further improved, and the display quality of the display panel can be improved. Illustratively, in fig. 6, the first transistor T1 is illustratively shown as a threshold compensation transistor T3 for reducing the leakage current on the leakage path of the gate of the driving transistor Tdr through the threshold compensation transistor T3, and the second transistor T2 is shown as an initialization transistor T4 for reducing the leakage current on the leakage path of the gate of the driving transistor Tdr through the initialization transistor T4.
It should be noted that, in other embodiments, the first transistor T1 may be further configured as an initialization transistor T4, for reducing the leakage current of the gate of the driving transistor Tdr on the leakage path of the initialization transistor T4, and the second transistor T2 is a threshold compensation transistor T3, for reducing the leakage current of the gate of the driving transistor Tdr on the leakage path of the threshold compensation transistor T3, which also can reduce the leakage currents of the gates of the driving transistors Tdr on different leakage paths, thereby improving the flicker phenomenon of the display panel.
Fig. 7 is a schematic diagram of a structure of another pixel driving circuit according to an embodiment of the invention. As shown in fig. 7, the transistor on the gate-drain path of the driving transistor Tdr is a double-gate transistor.
Specifically, when the pixel driving circuit includes the first transistor T1, the first transistor T1 may be a dual-gate transistor, and the leakage current of the first transistor T1 may be further reduced based on the bias of the threshold voltage of the first transistor T1, so that the leakage current on the gate leakage path of the driving transistor Tdr where the first transistor T1 is located may be further reduced, and the gate potential holding time of the driving transistor Tdr is increased, thereby improving the flicker phenomenon of the display panel. When the pixel driving circuit includes the second transistor T2, at least one of the first transistor T1 and the second transistor T2 may be a double gate transistor. When the second transistor T2 is a dual-gate transistor, the leakage current of the second transistor T2 can be further reduced on the basis of the bias of the threshold voltage of the second transistor T2, so that the leakage current on the gate leakage path of the driving transistor Tdr where the second transistor T2 is located can be further reduced, the gate potential holding time of the driving transistor Tdr is increased, and the flicker phenomenon of the display panel is improved.
It should be noted that fig. 7 exemplarily shows that the first transistor T1 and the second transistor T2 are simultaneously double-gate transistors. In other embodiments, one of the first transistor T1 and the second transistor T2 may be provided as a double gate transistor.
The embodiment of the invention also provides a display panel. Fig. 8 is a schematic structural diagram of a display panel according to an embodiment of the present invention. As shown in fig. 8, the display panel 100 includes an array substrate according to any embodiment of the present invention. Since the display panel 100 includes the array substrate provided by any embodiment of the present invention, the display panel has the beneficial effects of the array substrate provided by any embodiment of the present invention, and will not be described herein.
The embodiment of the invention also provides a manufacturing method of the array substrate. Fig. 9 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 9, the manufacturing method of the array substrate includes:
s10, forming a pixel driving circuit on a substrate; the pixel driving circuit comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a grid electrode leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor.
According to the technical scheme, when the pixel driving circuit is formed on the substrate, the threshold voltage of the first transistor is larger than that of the driving transistor, so that the leakage current of the first transistor in the off state is smaller, the leakage current on the gate leakage path of the driving transistor where the first transistor is located can be reduced, the gate potential holding time of the driving transistor is prolonged, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
Fig. 10 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 10, the manufacturing method of the array substrate includes:
s20, forming a semiconductor layer on a substrate;
Specifically, fig. 11 is a schematic structural diagram of an array substrate corresponding to step S20 of the method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 11, before the semiconductor layer 120 is formed on the substrate 110, the buffer layer 130 may be formed on the substrate 110, and the buffer layer 130 may be used to block impurities such as water and oxygen, so as to prevent the impurities from entering the display panel and affecting the performance of the device. The buffer layer 130 may be silicon dioxide or silicon nitride, etc. The semiconductor layer 120 may be a polysilicon layer, and when the semiconductor layer 120 is formed on the substrate 110, excimer laser crystallization ((ExcimerLaser Annealing, ELA)) crystallization may be used.
S21, patterning the semiconductor layer to form a first channel region and at least one second channel region; wherein the first channel region is for forming a channel of the drive transistor and the at least one second channel region is for forming a channel of the first transistor;
Specifically, fig. 12 is a schematic structural diagram of an array substrate corresponding to step S21 of the method for manufacturing an array substrate according to the embodiment of the present invention. As shown in fig. 12, after patterning the semiconductor layer 120, a first channel region 121 and a second channel region 122 are formed, the first channel region 121 corresponding to a channel of the driving transistor, and the second channel region 122 corresponding to a channel of the first transistor. The gate leakage path of the driving transistor may include a plurality of, illustratively, a pixel driving circuit including a threshold compensation transistor and an initialization transistor; the grid electrode of the initialization transistor is connected with the first scanning signal input end, the first electrode of the initialization transistor is connected with the reference signal input end, the second electrode of the initialization transistor and the second electrode of the threshold compensation transistor are connected with the grid electrode of the driving transistor, the grid electrode of the threshold compensation transistor is connected with the second scanning signal input end, the first electrode of the threshold compensation transistor is connected with the second electrode of the driving transistor, and the first electrode of the driving transistor is connected with the first voltage input end; at this time, the initialization transistor and the threshold compensation transistor are both located on the gate-drain path of the driving transistor, and the first transistor is the threshold compensation transistor or the initialization transistor.
The semiconductor layer 120 is also used to form a source region and a drain region of the transistor, and is disposed on both sides of a channel region of the transistor. For example, source and drain regions of the driving transistor may be formed at both sides of the first channel region 121, and source and drain regions of the first transistor may be formed at both sides of the second channel region 122. In addition, when the pixel driving circuit further includes other transistors, channel regions of the other transistors may be simultaneously formed when the semiconductor layer 120 is patterned. Illustratively, when the pixel driving circuit further includes a data writing transistor, a light emission control transistor, and a reset transistor, channel regions of the data writing transistor, the light emission control transistor, and the reset transistor may be simultaneously formed when the semiconductor layer 120 is patterned. Since the data writing transistor, the light emission control transistor, and the reset transistor are not disposed on the gate leakage path of the driving transistor, after the subsequent ion implantation, the ion concentrations of the channel regions of the data writing transistor, the light emission control transistor, and the reset transistor may be the same as the ion concentration of the first channel region. Also, when a plurality of pixel driving circuits are included on the array substrate, a plurality of first channel regions 121 and a plurality of second channel regions 122 may be simultaneously formed when the semiconductor layer 120 is patterned, for forming a channel of a driving transistor and a channel of a first transistor in each pixel driving circuit, respectively.
S22, carrying out ion implantation on the second channel region to enable the ion concentration of the second channel region to be larger than that of the first channel region;
Specifically, fig. 13 is a schematic structural diagram of an array substrate corresponding to step S22 of the method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 13, P-ion implantation may be employed in ion implantation of the second channel region 122 in order to ensure channel conductivity of the transistor. After the second channel region 122 is ion-implanted, the ion concentration of the second channel region 122 is greater than the ion concentration of the first channel region 121, so that the threshold voltage of the first transistor formed by the second channel region 122 is greater than the threshold voltage of the driving transistor formed by the first channel region 121. Exemplary, table 2 is a table of the relationship between the channel ion implantation dose and the threshold voltage of a transistor according to an embodiment of the present invention. As can be seen from table 2, P-ions are ions implanted into the channel of the transistor, p+ ions are ions implanted into the source and drain regions of the transistor, and Ion is the on-current of the transistor. On the basis of unchanged ion dose injected into the source region and the drain region of the transistor, the channel ion injection dose of the transistor is increased from 1e11 to 1e12, and the threshold voltage of the transistor is biased from-4.52V to-1.30V. It is understood that the larger the channel ion implantation dose of the transistor is, the more positive the threshold voltage of the transistor is. By providing the second channel region 122 with ion implantation, the ion concentration of the second channel region 122 can be made greater than the ion concentration of the first channel region 121, so that the threshold voltage of the first transistor formed by the second channel region 122 is made greater than the threshold voltage of the driving transistor formed by the first channel region 121.
TABLE 2 channel ion implant dose versus threshold voltage for transistors
| P- | P+ | Threshold voltage Vth (V) | On-current Ion (A) | Leakage current Ioff (A) |
| 1e11 | 1e15 | -4.52 | 5.54e-6 | 6.25e-11 |
| 6e11 | 1e15 | -2.89 | 9.21e-6 | 2.13e-11 |
| 1e12 | 1e15 | -1.30 | 1.29e-5 | 7.79e-12 |
With continued reference to fig. 13, ion implanting the second channel region such that the second channel region has a greater ion concentration than the first channel region comprises:
The first channel region is shielded, and ion implantation is performed on the second channel region.
Specifically, when the second channel region 122 is ion-implanted, the first channel region 121 may be masked with a photoresist layer, so that the first channel region 121 is prevented from being ion-implanted at the same time. Illustratively, the first channel region 121 may be masked with photoresist. After the second channel region 122 is implanted, the photoresist layer needs to be removed, so that the subsequent process flow is facilitated.
S23, forming a driving transistor and a first transistor based on the first channel region and the second channel region, respectively.
Specifically, after the ion implantation is finished, the driving transistor can be formed at the position corresponding to the first channel region based on the manufacturing process flow of the transistor, the first transistor is formed at the position corresponding to the second channel region, and meanwhile, the first transistor is located on the gate leakage path of the driving transistor through line connection, so that the leakage current on the gate leakage path of the driving transistor is reduced when the first transistor is turned off, the maintenance time of the gate potential of the driving transistor is prolonged, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
Fig. 14 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 14, the manufacturing method of the array substrate includes:
s30, forming a semiconductor layer on a substrate;
S31, patterning the semiconductor layer to form a first channel region and at least one second channel region; wherein the first channel region is for forming a channel of the drive transistor and the at least one second channel region is for forming a channel of the first transistor;
S32, shielding the first channel region, and performing ion implantation on the second channel region;
S33, shielding the second channel region, and performing ion implantation on the first channel region; wherein the ion implantation concentration of the first channel region is less than the ion implantation concentration of the second channel region.
Specifically, fig. 15 is a schematic structural diagram of an array substrate corresponding to step S33 of the method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 15, after ion implantation is performed on the second channel region 122, ion implantation may be performed on the first channel region 121 again to ensure channel conductivity of the driving transistor formed by the first channel region 121. Also, by setting the ion implantation concentration of the first channel region 121 to be smaller than the ion implantation concentration of the second channel region 122, the ion concentration of the second channel region 122 can be made larger than the ion concentration of the first channel region 121, so that the threshold voltage of the first transistor formed by the second channel region 122 is made larger than the threshold voltage of the driving transistor formed by the first channel region 121. When the first transistor is positioned on the gate leakage path of the driving transistor, the leakage current on the gate leakage path of the driving transistor can be reduced when the first transistor is turned off, the maintenance time of the gate potential of the driving transistor is increased, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
It should be noted that, in the embodiment of the present invention, the first channel region 121 is masked, the second channel region 122 is ion-implanted, and then the second channel region 122 is masked, and the order of ion implantation of the first channel region 121 is only an example and not a limitation. In other embodiments, the step S32 and the step S33 may be sequentially exchanged, which is not described herein. In addition, when ion implantation is performed to the first channel region 121 and the second channel region 122, a voltage at the time of ion implantation may also be set so as to adjust the ion concentration in the first channel region 121 and the ion concentration in the second channel region 122.
S34, a driving transistor and a first transistor are formed based on the first channel region and the second channel region, respectively.
In other embodiments, the pixel driving circuit may further include a second transistor, the second transistor being located on a gate leakage path of the driving transistor, and the second transistor and the first transistor being located on different gate leakage paths of the driving transistor. Illustratively, the pixel driving circuit includes a threshold compensation transistor and an initialization transistor; the grid electrode of the initialization transistor is connected with the first scanning signal input end, the first electrode of the initialization transistor is connected with the reference signal input end, the second electrode of the initialization transistor and the second electrode of the threshold compensation transistor are connected with the grid electrode of the driving transistor, the grid electrode of the threshold compensation transistor is connected with the second scanning signal input end, the first electrode of the threshold compensation transistor is connected with the second electrode of the driving transistor, and the first electrode of the driving transistor is connected with the first voltage input end; at this time, the initialization transistor and the threshold compensation transistor are both located on the gate leakage paths of the driving transistor, and the first transistor and the second transistor are located on different gate leakage paths of the driving transistor. When the first transistor is an initialization transistor, the second transistor is a threshold compensation transistor.
The invention also provides a manufacturing method of the array substrate. Fig. 16 is a flowchart of another method for manufacturing an array substrate according to an embodiment of the present invention. As shown in fig. 16, the manufacturing method of the array substrate includes:
S40, forming a semiconductor layer on the substrate;
S41, patterning the semiconductor layer to form a first channel region and two second channel regions; wherein the first channel region is used for forming a channel of the driving transistor, the second channel region is used for forming a channel of the first transistor, and the second channel region is used for forming a channel of the second transistor;
Specifically, fig. 17 is a schematic structural diagram of an array substrate corresponding to step S41 of the method for manufacturing an array substrate according to the embodiment of the present invention. As shown in fig. 17, after patterning the semiconductor layer 120, a first channel region 121 and two second channel regions 122 are formed, wherein the first channel region 121 corresponds to a channel of a driving transistor, one second channel region 122 corresponds to a channel of the first transistor, and the other second channel region 122 corresponds to a channel of the second transistor.
S42, carrying out ion implantation on the second channel region to enable the ion concentration of the second channel region to be larger than that of the first channel region;
Specifically, fig. 18 is a schematic structural diagram of an array substrate corresponding to step S42 of the method for manufacturing an array substrate according to the embodiment of the present invention. As shown in fig. 18, ion implantation may be performed on all of the second channel region 122. P-ion implantation may be employed when ion implantation is performed on all of the second channel region 122 in order to ensure channel conductivity of the transistor. After ion implantation is performed on all the second channel regions 122, the ion concentration of the second channel regions 122 is greater than that of the first channel regions 121, so that the threshold voltage of the first transistors formed by the second channel regions 122 and the threshold voltage of the second transistors formed by the second channel regions 122 are greater than that of the driving transistors formed by the first channel regions 121.
With continued reference to fig. 18, when the second channel region 122 is ion-implanted, the first channel region 121 may be masked to avoid that the first channel region 121 is ion-implanted simultaneously when the second channel region 122 is ion-implanted, so as to ensure that the ion concentration of the second channel region 122 is greater than that of the first channel region 121.
In other embodiments, after the second channel region 122 is ion-implanted, the second channel region 122 may be masked, the first channel region 121 may be ion-implanted, and the ion implantation concentration of the first channel region 121 may be smaller than that of the second channel region 122, so that the channel conductivity of the driving transistor formed by the first channel region 121 may be ensured on the basis of ensuring that the ion concentration of the first channel region 121 is smaller than that of the second channel region 122.
S43, forming a driving transistor, a first transistor, and a second transistor based on the first channel region and the second channel region, respectively.
Specifically, after the ion implantation is finished, the driving transistor can be formed at the position corresponding to the first channel region based on the manufacturing process flow of the transistor, the first transistor is formed at the position corresponding to one second channel region, the second transistor is formed at the position corresponding to the other second channel region, and meanwhile, the first transistor and the second transistor are respectively located on different gate leakage paths of the driving transistor through circuit connection, so that leakage currents on the different gate leakage paths of the driving transistor are reduced when the first transistor and the second transistor are turned off, the maintenance time of the gate potential of the driving transistor is prolonged, the driving current formed by the driving transistor is stable, the flicker phenomenon of the display panel is reduced, and the display image quality of the display panel is improved.
Note that the above is only a preferred embodiment of the present invention and the technical principle applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit or scope of the invention, which is set forth in the following claims.
Claims (9)
1. An array substrate, characterized by comprising:
A substrate;
The pixel driving circuit is arranged on the substrate and comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a gate leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor, so that the threshold voltage of the first transistor is biased relative to that of the driving transistor, and the leakage current of the first transistor when the first transistor is turned off is reduced;
The pixel driving circuit further comprises a second transistor, wherein the second transistor is positioned on a grid leakage path of the driving transistor, and the threshold voltage of the second transistor is larger than that of the driving transistor; the second transistor and the first transistor are located on different gate leakage paths of the drive transistor;
The semiconductor layer in the array substrate is a polycrystalline silicon layer and is used for forming channels of the driving transistor, the first transistor and the second transistor.
2. The array substrate according to claim 1, wherein the pixel driving circuit includes a threshold compensation transistor and an initialization transistor; the grid electrode of the initialization transistor is connected with a first scanning signal input end, the first electrode of the initialization transistor is connected with a reference signal input end, the second electrode of the initialization transistor and the second electrode of the threshold compensation transistor are connected with the grid electrode of the driving transistor, the grid electrode of the threshold compensation transistor is connected with a second scanning signal input end, the first electrode of the threshold compensation transistor is connected with the second electrode of the driving transistor, and the first electrode of the driving transistor is connected with a first voltage input end;
the transistor on the grid leakage path of the driving transistor is a threshold compensation transistor; or the transistor on the gate leakage path of the drive transistor is a gate initialization transistor.
3. The array substrate of claim 1, wherein the transistor on the gate leakage path of the drive transistor is a double gate transistor.
4. The manufacturing method of the array substrate is characterized by comprising the following steps of:
Forming a pixel driving circuit on a substrate; the pixel driving circuit comprises a driving transistor and a first transistor, wherein the first transistor is positioned on a gate leakage path of the driving transistor, and the threshold voltage of the first transistor is larger than that of the driving transistor, so that the threshold voltage of the first transistor is biased relative to that of the driving transistor, and the leakage current of the first transistor when the first transistor is turned off is reduced; the pixel driving circuit further comprises a second transistor, wherein the second transistor is positioned on a grid leakage path of the driving transistor, and the threshold voltage of the second transistor is larger than that of the driving transistor; the second transistor and the first transistor are located on different gate leakage paths of the drive transistor; the semiconductor layer in the array substrate is a polycrystalline silicon layer and is used for forming channels of the driving transistor, the first transistor and the second transistor.
5. The method of manufacturing an array substrate according to claim 4, wherein forming a pixel driving circuit on the substrate comprises:
Forming a semiconductor layer on the substrate;
Patterning the semiconductor layer to form a first channel region and at least one second channel region; wherein the first channel region is used for forming a channel of the driving transistor, and at least one second channel region is used for forming a channel of the first transistor;
Performing ion implantation on the second channel region to enable the ion concentration of the second channel region to be larger than that of the first channel region;
The driving transistor and the first transistor are formed based on the first channel region and the second channel region, respectively.
6. The method of manufacturing an array substrate according to claim 5, wherein patterning the semiconductor layer to form a first channel region and at least one second channel region comprises:
patterning the semiconductor layer to form a first channel region and two second channel regions; wherein the first channel region is used for forming a channel of the driving transistor, one of the second channel regions is used for forming a channel of the first transistor, and one of the second channel regions is used for forming a channel of the second transistor;
Forming the driving transistor and the first transistor based on the first channel region and the second channel region, respectively, includes:
The driving transistor, the first transistor, and the second transistor are formed based on the first channel region and the second channel region, respectively.
7. The method of manufacturing an array substrate according to claim 5 or 6, wherein performing ion implantation on the second channel region to make the ion concentration of the second channel region greater than the ion concentration of the first channel region, comprises:
And shielding the first channel region, and performing ion implantation on the second channel region.
8. The method of manufacturing an array substrate according to claim 7, further comprising, after masking the first channel region and ion implanting the second channel region:
masking the second channel region and performing ion implantation on the first channel region; wherein the ion implantation concentration of the first channel region is smaller than the ion implantation concentration of the second channel region.
9. A display panel comprising the array substrate of any one of claims 1-3.
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