CN113594203A

CN113594203A - Phase change memory, manufacturing method and positioning method thereof and mask

Info

Publication number: CN113594203A
Application number: CN202110849635.9A
Authority: CN
Inventors: 张恒; 雷威锋; 刘峻; 张曙; 王晓娟; 孙冰洋; 李�瑞
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-07-27
Filing date: 2021-07-27
Publication date: 2021-11-02

Abstract

The embodiment of the disclosure discloses a phase change memory, a manufacturing method thereof, a positioning method thereof and a mask. The phase change memory includes: the phase change memory comprises a first conductive line, a phase change memory unit and a second conductive line which are sequentially stacked along a first direction; the phase change memory cell is vertical to the first conductive line and the second conductive line; the first conductive line includes: a first set of electrically conductive lines and a second set of electrically conductive lines alternately arranged along a second direction; wherein, along a third direction, the ends of the first set of conductive lines are not flush with the ends of the second set of conductive lines; and/or, the second conductive line comprises: a third set of electrically conductive lines and a fourth set of electrically conductive lines arranged alternately in a third direction; wherein, along the second direction, the end of the third group of conductive lines is not flush with the end of the fourth group of conductive lines; the first direction is perpendicular to a plane where the second direction and the third direction are located, and the second direction is intersected with the third direction.

Description

Phase change memory, manufacturing method and positioning method thereof and mask

Technical Field

The embodiment of the disclosure relates to the field of semiconductor devices, in particular to a phase change memory, a manufacturing method, a positioning method and a mask thereof.

Background

In the development and production processes of phase change memories, Failure Analysis (FA) is an essential important means for improving process conditions and product yield. Through failure analysis, research and development personnel can be helped to find out problems such as defects in design, mismatching of process parameters or misoperation in production. Necessary feedback information is provided for subsequent product design, and necessary supplement is provided for adjustment of the production process.

In the related art, a failed phase change memory cell can be located according to the position parameters of the word line and the position parameters of the bit line, and the failure analysis can be performed on the phase change memory cell through sample slicing and preparation. However, as the integration density and bit density of phase change memories increase, the number of word lines and bit lines increases and the feature size decreases, the difficulty of accurately positioning the phase change memory cells according to the word lines and bit lines increases, resulting in less efficient failure analysis. Therefore, how to accurately and quickly locate a failed phase change memory cell in the phase change memory to improve the efficiency of failure analysis is a technical problem to be solved urgently.

Disclosure of Invention

In view of this, the present disclosure provides a phase change memory, a method for manufacturing the same, a method for positioning the same, and a mask.

According to a first aspect of embodiments of the present disclosure, there is provided a phase change memory, including:

the phase change memory comprises a first conductive line, a phase change memory unit and a second conductive line which are sequentially stacked along a first direction; wherein the first and second conductive lines are parallel to the same plane and perpendicular to each other, the phase change memory cell being perpendicular to both the first and second conductive lines;

the first conductive line includes: a first set of electrically conductive lines and a second set of electrically conductive lines alternately arranged along a second direction; wherein, along a third direction, ends of the first set of conductive lines are not flush with ends of the second set of conductive lines;

and/or the presence of a gas in the gas,

the second conductive line includes: a third set of electrically conductive lines and a fourth set of electrically conductive lines arranged alternately in the third direction; wherein, along the second direction, ends of the third set of conductive lines are not level with ends of the fourth set of conductive lines;

the first direction is perpendicular to a plane where the second direction and the third direction are located, and the second direction and the third direction are intersected.

In some embodiments, the ends of the first set of conductive lines are not flush with the ends of the second set of conductive lines, comprising:

The length of the first set of conductive lines is the same as the length of the second set of conductive lines along the third direction, and the center line of the first set of conductive lines along the second direction is a first preset distance away from the center line of the second set of conductive lines along the second direction;

or the like, or, alternatively,

the lengths of the first set of conductive lines are different from the lengths of the second set of conductive lines along the third direction, and the center lines of the first set of conductive lines along the second direction coincide with the center lines of the second set of conductive lines along the second direction.

In some embodiments, the ends of the third set of conductive lines are not flush with the ends of the fourth set of conductive lines, comprising:

the length of the third set of conductive lines is the same as the length of the fourth set of conductive lines along the second direction, and the center line of the third set of conductive lines along the third direction is a second preset distance away from the center line of the fourth set of conductive lines along the third direction;

or the like, or, alternatively,

the third set of conductive lines has a length different from the fourth set of conductive lines along the second direction and a centerline of the third set of conductive lines along the third direction coincides with a centerline of the fourth set of conductive lines along the third direction.

In some embodiments, the first preset distance ranges between 80nm to 120nm when the length of the first set of conductive lines is the same as the length of the second set of conductive lines;

or the like, or, alternatively,

a range of variation of a first difference between the lengths of the first and second sets of conductive lines is between 100nm and 200nm when the lengths of the first and second sets of conductive lines are different.

In some embodiments, when the length of the third set of conductive lines is the same as the length of the fourth set of conductive lines, the second preset distance ranges between 80nm and 120 nm;

or the like, or, alternatively,

a range of variation of a second difference between the lengths of the third and fourth sets of conductive lines is between 100nm and 200nm when the lengths of the third and fourth sets of conductive lines are different.

In some embodiments, the first set of conductive lines comprises: a plurality of first sub-conductive lines are arranged in parallel along the second direction;

the second set of conductive lines includes: a plurality of second sub-conductive lines are arranged in parallel along the second direction;

the third set of conductive lines includes: a plurality of third sub-conductive lines are arranged in parallel along the third direction;

The fourth set of conductive lines comprises: and a plurality of fourth sub-conductive lines are arranged in parallel along the third direction.

According to a second aspect of the embodiments of the present disclosure, there is provided a method for manufacturing a phase change memory, the method including:

forming first and second mask regions on the plurality of memory stacks alternately arranged in a second direction; wherein, in a third direction, the ends of the first mask regions are not flush with the ends of the second mask regions;

etching a first rectangular ring according to the first mask region and the second mask region to form a first group of conductive lines and a second group of conductive lines which are alternately arranged along the second direction so as to form a first conductive line;

and/or the presence of a gas in the gas,

forming third mask regions and fourth mask regions alternately arranged in the third direction on a plurality of second rectangular rings; wherein, along the second direction, ends of the third mask regions are not flush with ends of the fourth mask regions;

etching the plurality of second rectangular rings according to the third mask region and the fourth mask region to form a third group of conductive lines and a fourth group of conductive lines alternately arranged along the third direction to form second conductive lines;

Wherein the second direction and the third direction intersect and are parallel to the same plane.

In some embodiments, said first mask region ends non-flush with said second mask region ends along said third direction, comprising:

in the third direction, the length of the first mask region is the same as the length of the second mask region, and the center line of the first mask region in the second direction is a first preset distance away from the center line of the second mask region in the second direction;

or the like, or, alternatively,

the first mask region has a length along the third direction that is different from a length of the second mask region, and a centerline of the first mask region along the second direction coincides with a centerline of the second mask region along the second direction.

In some embodiments, said second direction wherein the ends of said third mask regions are not flush with the ends of said fourth mask regions comprises:

the third mask region has the same length as the fourth mask region along the second direction, and the center line of the third mask region along the third direction is a second predetermined distance from the center line of the fourth mask region along the third direction;

Or the like, or, alternatively,

the third mask region has a length along the second direction that is different from a length of the fourth mask region, and a centerline of the third mask region along the third direction coincides with a centerline of the fourth mask region along the third direction.

In some embodiments, before the step of forming the first and second mask regions alternately arranged along the second direction on the plurality of memory stacks, the method further comprises:

etching a first conductive layer and a storage material lamination layer which are stacked along a first direction to form a plurality of first rectangular rings which are arranged in parallel along the second direction and a plurality of storage lamination layers which are arranged in parallel along the second direction respectively;

the first direction is perpendicular to a plane where the second direction and the third direction are located.

In some embodiments, after forming the first conductive lines, before forming the third and fourth masked regions on the plurality of second rectangular loops alternately arranged in the third direction, further comprises:

etching the storage lamination layer and a second conductive layer formed on the storage lamination layer to respectively form a plurality of phase change storage units distributed in an array and a plurality of second rectangular rings arranged in parallel along the third direction;

Wherein the first conductive line, the phase change memory cell, and the second conductive line are sequentially stacked along the first direction.

According to a third aspect of the embodiments of the present disclosure, there is provided a method for positioning a phase change memory cell included in the phase change memory in any of the embodiments, the method including:

when the phase change memory is indicated to comprise a target phase change memory unit which does not meet the preset requirement in the electrical detection result of the phase change memory, acquiring a position parameter indicating the position of the target phase change memory unit according to the detection result; wherein the location parameters include at least: indicating a first number of a target first conductive line electrically connected to the target phase change memory cell and a second number of a target second conductive line electrically connected to the target phase change memory cell;

obtaining a first number of first conductive lines included in each of the first set of conductive lines and obtaining a second number of the first conductive lines included in each of the second set of conductive lines; determining a location of the target first conductive line according to the first number, and the second number; locating an actual location of the target phase change memory cell in the phase change memory according to the location of the target first conductive line and the second number;

And/or the presence of a gas in the gas,

obtaining a third number of second conductive lines included in each of the third set of conductive lines and obtaining a fourth number of the second conductive lines included in each of the fourth set of conductive lines; determining a position of the target second conductive line according to the second number, the third number, and the fourth number; locating an actual location of the target phase change memory cell in the phase change memory according to the location of the target second conductive line and the first number.

According to a fourth aspect of the embodiments of the present disclosure, there is provided a mask used in the method for manufacturing the phase change memory in any of the above embodiments to form the phase change memory in any of the above embodiments, including:

a first side and a second side which are oppositely arranged; wherein the first side surface comprises first convex parts and first concave parts which are alternately arranged; the second side surface comprises second convex parts and second concave parts which are alternately arranged or second concave parts and second convex parts which are alternately arranged.

Compared with the mode of positioning the phase change memory unit one by digit lines or word lines in the related art, in the embodiment of the disclosure, the first conductive line is set as the first group of conductive lines and the second group of conductive lines with non-flush ends, the first group of conductive lines and the second group of conductive lines can be in a concave-convex shape, and/or the second conductive line is set as the third group of conductive lines and the fourth group of conductive lines with non-flush ends, the third group of conductive lines and the fourth group of conductive lines can be in a concave-convex shape, and when the test result indicates that the phase change memory unit which does not meet the preset requirement is included in the phase change memory, the concave-convex shape mark is used as a guide, so that the phase change memory unit can be accurately and quickly positioned.

Furthermore, the positioning accuracy of the phase change memory unit is increased, so that the accuracy of failure analysis is improved, correct information is fed back in time, and the yield of devices is improved. Because the positioning time of the phase change memory unit is reduced, the efficiency of failure analysis is favorably improved.

Drawings

FIGS. 1 a-1 c are schematic diagrams of a phase change memory shown in accordance with an exemplary embodiment;

FIGS. 2a and 2b are schematic layout views of the phase change memory shown in FIGS. 1a to 1 c;

3 a-3 e are schematic diagrams of a phase change memory shown in accordance with an embodiment of the present disclosure;

FIG. 4 is a flow chart illustrating a method of fabricating a phase change memory according to an embodiment of the present disclosure;

fig. 5a to 5k are schematic structural diagrams illustrating a method for manufacturing a phase change memory according to an embodiment of the disclosure;

FIG. 6 is a flow chart illustrating another method of fabricating a phase change memory according to an embodiment of the present disclosure;

FIG. 7 is a flow chart illustrating a method of fabricating yet another phase change memory according to an embodiment of the present disclosure;

FIG. 8 is a flow chart illustrating a method for phase change memory location according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a reticle according to an embodiment of the present disclosure.

Detailed Description

The technical solutions of the present disclosure will be further explained in detail with reference to the drawings and examples. While exemplary implementations of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is more particularly described in the following paragraphs with reference to the accompanying drawings by way of example. Advantages and features of the present disclosure will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present disclosure.

It is to be understood that the meaning of "on … …," "over … …," and "over … …" of the present disclosure should be read in the broadest manner such that "on … …" not only means that it is "on" something without intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of being "on" something with intervening features or layers therebetween.

In the disclosed embodiment, the term "a is connected to B" includes A, B where a is connected to B in contact with each other, or A, B where a is connected to B in a non-contact manner with other components interposed between the two.

In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not necessarily used for describing a particular order or sequence.

In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure, or a layer may be between any horizontal pair at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. The layer may comprise a plurality of sub-layers.

The technical means described in the embodiments of the present disclosure may be arbitrarily combined without conflict.

Fig. 1a and 1b are schematic diagrams illustrating a phase change memory 1000 according to an exemplary embodiment. Fig. 1a is a structural diagram of a phase change memory 1000 in the xoy plane, and referring to fig. 1a, the phase change memory 1000 includes a plurality of memory blocks. FIG. 1b is a partial schematic diagram of the S region in FIG. 1a, and referring to FIG. 1b, the phase change memory 1000 includes a Bottom Bit Line (BBL), a Word Line (WL), and a Top Bit Line (TBL). Fig. 1c is a projection of the wiring in the phase change memory 1000 in the xoy plane. Referring to FIG. 1c, phase change memory 1000 includes a bottom bit line, a bottom phase change memory cell, a word line, a top phase change memory cell, and a top bit line.

Note that, in the direction perpendicular to the xoy plane, the bottom bit line, the bottom phase change memory cell, the word line, the top phase change memory cell, and the top bit line are sequentially stacked. Within the xoy plane, a bottom phase change memory cell is located via the intersection of a bottom bit line and a word line, and a top phase change memory cell is located via the intersection of a word line and a top bit line.

Referring to fig. 1c, the phase change memory 1000 further includes: a bottom bit line contact for transmitting a first control signal to the bottom bit line; a word line contact for transmitting a second control signal to the word line; a top bit line contact for transmitting a third control signal to the top bit line. It will be appreciated that the bottom phase change memory cell may be activated in accordance with the first and second control signals and the top phase change memory cell may be activated in accordance with the second and third control signals.

FIG. 2a showsS in the phase change memory 1000₁Schematic of local bit lines. Referring to fig. 2a, the phase change memory includes a plurality of bit lines arranged in parallel in the x-direction. It is emphasized that the bit lines here can be either bottom or top bit lines. FIG. 2b shows S in the phase change memory 1000 ₂Schematic diagram of local word lines. Referring to fig. 2b, the phase change memory includes a plurality of word lines arranged in parallel in the y-direction. It is emphasized that S₂The region includes S₁And a region in which a plurality of phase change memory cells each located at an intersection of a single bit line and a single word line are located via a plurality of bit lines juxtaposed in the x direction and a plurality of word lines juxtaposed in the y direction.

In the related art, after the phase change memory is manufactured, a wafer test (wafer sort) is performed on the phase change memory to obtain a test result. When the test result indicates that the phase change memory comprises the phase change memory unit which does not meet the preset requirement, the phase change memory unit can be positioned according to the position parameters of the word line and the bit line, and the phase change memory unit can be subjected to failure analysis through slicing sample preparation.

However, as the integration density and bit density of the phase change memory increase, the number of word lines and bit lines increases, for example, S in fig. 2a₁The region may include 2K (1K 1024) bit lines, S in fig. 2b₂The region may comprise 2K word lines, i.e. S in FIG. 2a₁The region may include 2K by 2K phase change memory cells, and the word lines and bit lines have decreasing feature sizes, the spacing between adjacent word lines or adjacent bit lines has decreasing, and the word lines or bit lines are arranged more and more densely.

On one hand, the difficulty of accurately positioning the phase change memory cell according to the word line and the bit line is increased, if the positioning of the phase change memory cell is deviated, the result of failure analysis is influenced, wrong feedback information is formed, the process is not adjusted timely, and the yield of the device is reduced. On the other hand, the difficulty of quickly positioning the phase change memory cells according to the word lines and the bit lines increases, resulting in a less efficient failure analysis.

In view of the above, the embodiments of the present disclosure provide a phase change memory.

Fig. 3a to 3e are schematic diagrams illustrating a phase change memory 2000 according to an embodiment of the disclosure. As shown in fig. 3a and 3b, the phase change memory 2000 includes:

a first conductive line 2100, a phase change memory cell 2200, and a second conductive line 2300 stacked in this order in a first direction; wherein the first and second

conductive lines

2100 and 2300 are parallel to the same plane and perpendicular to each other, the phase change memory cell 2200 is perpendicular to both the first and second

conductive lines

2100 and 2300;

the first conductive line 2100 includes: a first set of conductive lines 2110 and a second set of conductive lines 2120 alternately arranged in a second direction; wherein, in a third direction, the ends of the first set of conductive lines 2110 are not flush with the ends of the second set of conductive lines 2120;

And/or the presence of a gas in the gas,

the second conductive line 2300 includes: a third and fourth sets of

conductive lines

2310 and 2320 alternately arranged in a third direction; wherein, along the second direction, the ends of the third set of conductive lines 2310 are not level with the ends of the fourth set of conductive lines 2320;

the first direction is perpendicular to a plane where the second direction and the third direction are located, and the second direction is intersected with the third direction.

Illustratively, referring to fig. 3b, the first conductive lines 2100 include a first set of conductive lines 2110 and a second set of conductive lines 2120 alternately arranged along the x-direction, wherein ends of the first set of conductive lines 2110 along the y-direction are located on different horizontal lines than ends of the second set of conductive lines 2120 along the y-direction, for example, ends of the first set of conductive lines 2110 are located on an AA 'horizontal line, and ends of the second set of conductive lines 2120 are located on a BB' horizontal line. The AA 'horizontal line does not coincide with the BB' horizontal line.

Illustratively, referring to fig. 3b, the second conductive line 2300 includes a third set of conductive lines 2310 and a fourth set of conductive lines 2320 alternately arranged along the y-direction, ends of the third set of conductive lines 2310 along the x-direction being located on different horizontal lines than ends of the fourth set of conductive lines 2320 along the x-direction, e.g., ends of the third set of conductive lines 2310 being located on the CC 'horizontal line and ends of the fourth set of conductive lines 2320 being located on the DD' horizontal line. The CC 'horizontal line is not coincident with the DD' horizontal line.

The following three schemes are included in this embodiment: the ends of the first set of conductive lines are not flush with the ends of the second set of conductive lines; the ends of the third set of electrically conductive lines are not flush with the ends of the fourth set of electrically conductive lines; the ends of the first set of conductive lines are not flush with the ends of the second set of conductive lines, and the ends of the third set of conductive lines are not flush with the ends of the fourth set of conductive lines.

Illustratively, the first conductive line 2100 may be a word line (word line) of a phase change memory, and the second conductive line 2300 may be a bit line (bit line) of the phase change memory. Alternatively, the first conductive line 2100 may be a bit line of a phase change memory and the second conductive line 2300 may be a word line of the phase change memory.

The constituent materials of the first and second

conductive lines

2100 and 2300 include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or any combination thereof. The first conductive line 2100 and the second conductive line 2300 may have the same conductive material or may have different conductive materials.

It is emphasized that the first plane in which the first conductive line 2100 is disposed and the second plane in which the second conductive line 2300 is disposed are parallel, and the first plane and the second plane do not overlap. Phase change memory cell 2200 is between the first plane and the second plane, and phase change memory cell 2200 is perpendicular to both the first plane and the second plane.

Illustratively, referring to FIG. 3b, the projection of the phase change memory cell 2200 in the xoy plane is located at the intersection of the first conductive line 2100 and the second conductive line 2300.

It should be noted that, as used herein, the z direction represents a first direction, the x direction represents a second direction, the y direction represents a third direction, the x direction is different from the y direction, and the z direction is perpendicular to the xoy plane. And will not be described in detail hereinafter. It should be noted that the x direction intersects the y direction, and the included angle between the x direction and the y direction includes an acute angle, a right angle, or an obtuse angle. Preferably, the x-direction is perpendicular to the y-direction.

In some embodiments, the ends of the first set of conductive wires 2110 are not flush with the ends of the second set of conductive wires 2120, including:

along the third direction, the length of the first set of conductive lines 2110 is the same as the length of the second set of conductive lines 2120, and the center line of the first set of conductive lines 2110 along the second direction is a first preset distance away from the center line of the second set of conductive lines 2120 along the second direction;

or the like, or, alternatively,

along the third direction, the length of the first set of conductive lines 2110 is different from the length of the second set of conductive lines 2120, and the center line of the first set of conductive lines 2110 along the second direction coincides with the center line of the second set of conductive lines 2120 along the second direction.

Illustratively, referring to FIGS. 3b and 3d, the length W of the first set of conductive lines 2110₁And a length W of the second set of conductive lines 2120₂In contrast, the first set of conductive lines 2110 are about the axis of symmetry L₁L₂Symmetrically, the second set of conductive lines 2120 also lie about the axis of symmetry L₁L₂Symmetry, axis of symmetry L ₁L₂Perpendicular to the y-axis, in which case the axis of symmetry L₁L₂Can represent the center line of the first set of conductive lines 2110 in the x-direction, and can also represent the center line of the second set of conductive lines 2120 in the x-directionThe solution is that when the y-axis is perpendicular to the x-axis, the axis of symmetry L₁L₂Parallel to the x-axis.

Illustratively, referring to fig. 3c and 3e, the length of the first set of conductive lines 2110 is the same as the length of the second set of conductive lines 2120, the first set of conductive lines 2110 is about a first axis of symmetry L₁L₂Symmetrically, the second set of conductive lines 2120 about the second axis of symmetry L₅L₆Symmetry, first axis of symmetry L₁L₂And a second axis of symmetry L₅L₆Are all perpendicular to the y-axis, in which case the first axis of symmetry L₁L₂Shown is the center line of the first set of conductive lines 2110 along the x-direction, the second axis of symmetry L₅L₆Shown is the center line of the second set of conductive lines 2120 along the x-direction, the first axis of symmetry L₁L₂And a second axis of symmetry L₅L₆A first preset distance from each other, it being understood that the first axis of symmetry L is when the y-axis is perpendicular to the x-axis₁L₂And a second axis of symmetry L₅L₆Are all parallel to the x-axis.

It is understood that, in the embodiments of the present disclosure, the first set of conductive lines and the second set of conductive lines may include at least two routing manners. In the process of designing the actual phase change memory, a person skilled in the art can reasonably select the wiring modes of the first group of conductive lines and the second group of conductive lines according to actual requirements, so that the adjustability and flexibility of the wiring modes of the first group of conductive lines and the second group of conductive lines are increased.

In some embodiments, the first preset distance ranges between 80nm to 120nm when the length of the first set of conductive lines is the same as the length of the second set of conductive lines. Preferably, the first predetermined distance is 100 nm.

Exemplarily, referring to fig. 3c and 3e, when the length of the first set of conductive lines 2110 is the same as the length of the second set of conductive lines 2120, the first axis of symmetry L₁L₂And a second axis of symmetry L₅L₆Is a first predetermined distance, which varies between 80nm and 120nm, preferably 100 nm. The first set of conductive wires 2110 are against the second set of conductive wires 2120The distance between the two proximal end portions is equal, i.e., the two end portions have equal lengths but do not overlap each other along the center line in the second direction.

In some embodiments, a first difference value between the length of the first set of conductive lines and the length of the second set of conductive lines varies between 100nm and 200nm when the length of the first set of conductive lines is different from the length of the second set of conductive lines. Preferably, the first difference is 150 nm.

Illustratively, referring to FIGS. 3b and 3d, when the length W of the first set of conductive lines 2110 is₁And a length W of the second set of conductive lines 2120₂At different times, the length W of the first set of conductive lines 2110 ₁And a length W of the second set of conductive lines 2120₂A first difference (W) therebetween₁-W₂) Ranges between 100nm and 200nm, preferably 150 nm. The distance between the two ends of the first and second sets of

conductive lines

2110 and 2120 close to each other is not equal, that is, the center lines of the two lines in the second direction are coincident although the lengths are not equal.

It is noted that the first difference here represents the absolute value of the difference between the length of the first set of conductive lines and the length of the second set of conductive lines, and the length of the first set of conductive lines in fig. 3b and 3d being greater than the length of the second set of conductive lines is merely an example for conveying the present disclosure to those skilled in the art, and it is understood that in other embodiments, the length of the first set of conductive lines may also be less than the length of the second set of conductive lines.

In some embodiments, the ends of the third set of conductive lines 2310 are not flush with the ends of the fourth set of conductive lines 2320, including:

the length of the third set of conductive lines 2310 is the same as the length of the fourth set of conductive lines 2320 along the second direction, and the center line of the third set of conductive lines 2310 along the third direction is a second preset distance from the center line of the fourth set of conductive lines 2320 along the third direction;

Or the like, or, alternatively,

the length of the third set of conductive lines 2310 is different from the length of the fourth set of conductive lines 2320 along the second direction, and the center line of the third set of conductive lines 2310 along the third direction coincides with the center line of the fourth set of conductive lines 2320 along the third direction.

Illustratively, referring to fig. 3b and 3c, the third set of conductive lines 2310 has a length W₃And a fourth set of length W of conductive lines 2320₄In contrast, the third set of conductive lines 2310 is about the axis of symmetry L₃L₄Symmetrically, the fourth set of conductive lines 2320 also pertains to the axis of symmetry L₃L₄Symmetry, axis of symmetry L₃L₄Perpendicular to the x-axis, in which case the axis of symmetry L₃L₄Either the center line of the third set of conductive lines 2310 in the y-direction or the center line of the fourth set of conductive lines 2320 in the y-direction, it is understood that the axis of symmetry L is when the x-axis is perpendicular to the y-axis₃L₄Parallel to the y-axis.

Illustratively, referring to fig. 3d and 3e, the lengths of the third set of conductive lines 2310 are the same as the lengths of the fourth set of conductive lines 2320, the third set of conductive lines 2310 being about a third axis of symmetry L₃L₄Symmetrically, the fourth set of conductive lines 2320 is about the fourth axis of symmetry L₇L₈Symmetry, third axis of symmetry L₃L₄And a fourth axis of symmetry L₇L₈Are all perpendicular to the x-axis, in which case the third axis of symmetry L₃L₄Shown is the center line of the third set of conductive lines 2310 in the y-direction, the fourth axis of symmetry L ₇L₈Shown is the center line of the fourth set of conductive lines 2320 along the y-direction, the third axis of symmetry L₃L₄And a fourth axis of symmetry L₇L₈At a second predetermined distance from each other, it being understood that the third axis of symmetry L is when the x-axis is perpendicular to the y-axis₃L₄And a fourth axis of symmetry L₇L₈Are all parallel to the y-axis.

It is understood that, in the embodiments of the present disclosure, the third and fourth sets of conductive lines may include at least two routing manners. In the process of designing the actual phase change memory, a person skilled in the art can reasonably select the wiring modes of the third group of conductive lines and the fourth group of conductive lines according to actual requirements, so that the adjustability and flexibility of the wiring modes of the third group of conductive lines and the fourth group of conductive lines are increased.

In some embodiments, the second predetermined distance ranges between 80nm to 120nm when the length of the third set of conductive lines is the same as the length of the fourth set of conductive lines. Preferably, the second predetermined distance is 100 nm.

Illustratively, referring to fig. 3d and 3e, when the lengths of the third and fourth sets of

conductive lines

2310 and 2320 are the same, the third axis of symmetry L₃L₄And a fourth axis of symmetry L₇L₈At a second predetermined distance ranging from 80nm to 120nm, preferably 100 nm. The distance between the two end portions of the third and fourth sets of

conductive lines

2310 and 2320 close to each other is equal, that is, the center lines in the second direction do not coincide although the lengths are equal.

In some embodiments, a variation range of the second difference value between the length of the third set of conductive lines and the length of the fourth set of conductive lines is between 100nm and 200nm when the length of the third set of conductive lines is different from the length of the fourth set of conductive lines. Preferably, the second difference is 150 nm.

Illustratively, referring to fig. 3b and 3c, when the third set of conductive lines 2310 has a length W₃And a fourth set of length W of conductive lines 2320₄At different times, the length W of the third set of conductive lines 2310₃And a fourth set of length W of conductive lines 2320₄A second difference (W) therebetween₃-W₄) Ranges between 100nm and 200nm, preferably 150 nm. The distances between the two end portions of the third and fourth sets of

conductive lines

2310 and 2320 close to each other are not equal, that is, the center lines of the two lines in the second direction are coincident although the lengths are not equal.

It is noted that the second difference here represents the absolute value of the difference between the lengths of the third set of conductive lines and the fourth set of conductive lines, and the length of the third set of conductive lines in fig. 3b and 3c being greater than the length of the fourth set of conductive lines is merely an example for conveying the disclosure to those skilled in the art, and it is understood that in other embodiments, the length of the third set of conductive lines may also be less than the length of the fourth set of conductive lines.

In some embodiments, the first predetermined distance and the second predetermined distance may be the same. In other embodiments, the first predetermined distance and the second predetermined distance may be different.

In some embodiments, the first difference and the second difference may be the same. In other embodiments, the first difference and the second difference may be different.

In some embodiments, the first set of conductive lines comprises: arranging a plurality of first sub-conductive lines in parallel along a second direction;

the second set of conductive lines includes: a plurality of second sub-conductive lines are arranged in parallel along a second direction;

the third set of conductive lines includes: a plurality of third sub-conductive lines are arranged in parallel along a third direction;

the fourth set of conductive lines includes: a plurality of fourth sub conductive lines are juxtaposed in the third direction.

Illustratively, referring to fig. 3b, the first group of conductive lines 2110 includes 4 first sub-conductive lines 2111 juxtaposed in the x-direction, the second group of conductive lines 2120 includes 4 second sub-conductive lines 2121 juxtaposed in the x-direction, and the third group of conductive lines 2310 includes 4 third sub-conductive lines 2311 juxtaposed in the y-direction; the fourth set of conductive lines 2320 includes 4 fourth sub-conductive lines 2321 juxtaposed in the y-direction.

It is emphasized that 4 of fig. 3b are merely illustrative and are not intended to convey the disclosure to those skilled in the art, however, the disclosure is not limited thereto. The number of first sub-conductive lines comprised by the first set of conductive lines 2110 may also be 8, 16, 32 or even more. The second set of conductive lines 2120, the third set of conductive lines 2310, and the fourth set of conductive lines 2320 are similar and not described further herein.

It should be noted that, here, the first sub conductive line and the second sub conductive line both represent the first conductive line, and the third sub conductive line and the fourth sub conductive line both represent the second conductive line, and the different reference numerals are only used to distinguish the difference in position or length between the first sub conductive line and the second sub conductive line, and between the third sub conductive line and the fourth sub conductive line, and are not used to represent a specific order.

In some embodiments, the first set of conductive lines 2110 includes: k first sub-conductive lines are arranged in parallel along a second direction; wherein K is a natural number;

the second set of conductive lines 2120 includes: l second sub-conductive lines are arranged in parallel along a second direction; wherein L is a natural number;

the third group of conductive lines 2310 includes: m third sub-conductive lines are arranged in parallel along a third direction; wherein M is a natural number;

the fourth set of conductive lines 2320 includes: n fourth sub-conductive lines are arranged in parallel along a third direction; wherein N is a natural number.

In some embodiments, the first set of conductive lines comprises the same number of first sub-conductive lines as the second set of conductive lines, i.e. the relationship: and the number of the first conductive lines included in the adjacent first group and second group is 2K or 2L.

In some embodiments, the first set of conductive lines comprises a different number of first sub-conductive lines than the second set of conductive lines, i.e. the relationship: k ≠ L, and the adjacent first and second sets of conductive lines include (K + L) number of first conductive lines.

In some embodiments, the third group of conductive lines includes the same number of third sub conductive lines as the fourth group of conductive lines, i.e. the relationship: and M is equal to N, and the number of the second conductive lines included in the adjacent third and fourth groups of conductive lines is 2M or 2N.

In some embodiments, the third set of conductive lines includes a different number of third sub-conductive lines than the fourth set of conductive lines, i.e., satisfies the relationship: and M ≠ N, and the number of the second conductive lines included in the adjacent third and fourth groups of conductive lines is (M + N).

In some embodiments, the adjacent two first sets of conductive lines 2110 comprise the same number of first sub-conductive lines;

the adjacent two second group conductive lines 2120 include the same number of second sub conductive lines;

the adjacent two third groups of conductive lines 2310 include the same number of third sub conductive lines;

The adjacent two fourth sets of conductive lines 2320 include the same number of fourth sub-conductive lines.

Illustratively, referring to fig. 3b, the first conductive line 2100 includes two first groups of conductive lines juxtaposed along the x-direction, the first group of conductive lines including 4 first sub-conductive lines, and the second first group of conductive lines including 4 first sub-conductive lines. The second set of conductive lines is located between two adjacent first sets of conductive lines.

Exemplarily, referring to fig. 3b, the first conductive line 2100 includes two second groups of conductive lines juxtaposed along the x-direction, the first second group of conductive lines includes 4 second sub conductive lines, and the second group of conductive lines includes 4 second sub conductive lines. The first set of conductive lines is located between two adjacent second sets of conductive lines.

Exemplarily, referring to fig. 3b, the second conductive line 2300 includes two third groups of conductive lines arranged in parallel in the y-direction, the first third group of conductive lines includes 4 third sub-conductive lines, and the second third group of conductive lines includes 4 third sub-conductive lines. The fourth set of conductive lines is located between two adjacent third sets of conductive lines.

Illustratively, referring to fig. 3b, the second conductive line 2300 includes two fourth groups of conductive lines arranged in parallel in the y-direction, the first fourth group of conductive lines including 4 fourth sub-conductive lines, and the second fourth group of conductive lines including 4 fourth sub-conductive lines. The third group of conductive lines is located between two adjacent fourth groups of conductive lines.

Taking fig. 3b as an example, the adjacent first and second sets of conductive lines may form a first set, the first set comprising 8 first conductive lines, and fig. 3b comprising two first sets. The adjacent third and fourth sets of conductive lines may constitute a second set comprising 8 second conductive lines, two second sets being comprised in fig. 3 b. As a result of the test, when the phase change memory cell 2200 ' in FIG. 3b fails, the area of the phase change memory cell 2200 ' can be quickly located according to the first and second sets, and then the location of the phase change memory cell 2200 ' can be accurately located according to the second and fourth sets of conductive lines. The accurate positioning of the phase change memory unit is facilitated.

Fig. 4 is a flowchart illustrating a method of fabricating a phase change memory according to an embodiment of the disclosure. Referring to fig. 4, the method includes the steps of:

s110: forming first and second mask regions on the plurality of memory stacks alternately arranged in a second direction; wherein, along the third direction, the end of the first mask region is not flush with the end of the second mask region;

s120: etching the first rectangular ring according to the first mask region and the second mask region to form a first group of conductive lines and a second group of conductive lines which are alternately arranged along a second direction so as to form a first conductive line;

S130: forming third mask regions and fourth mask regions alternately arranged in a third direction on the plurality of second rectangular rings; wherein, along the second direction, an end of the third mask region is not flush with an end of the fourth mask region;

s140: etching a plurality of second rectangular rings according to the third mask region and the fourth mask region to form a third group of conductive lines and a fourth group of conductive lines which are alternately arranged along a third direction so as to form second conductive lines;

In the embodiment of the present disclosure, by forming the first conductive line and the second conductive line, since the first conductive line includes the first group of conductive lines and the second group of conductive lines whose ends are not even, the first group of conductive lines and the second group of conductive lines may be in a shape of "concave-convex"; the second conductive wire comprises a third group of conductive wires and a fourth group of conductive wires, the ends of the third group of conductive wires and the fourth group of conductive wires are not flush, the third group of conductive wires and the fourth group of conductive wires can be concave-convex, when the test result indicates that the phase change memory comprises a phase change memory unit which does not meet the preset requirement, the concave-convex mark is used as a guide, and the phase change memory unit is favorably and accurately and quickly positioned.

Fig. 5a to 5k are schematic structural diagrams illustrating a method for manufacturing a phase change memory according to an embodiment of the disclosure. The following describes the manufacturing method of the present disclosure in further detail with reference to fig. 4 and fig. 5a to 5 k.

In some embodiments, before the step of forming the first mask regions and the second mask regions alternately arranged along the second direction on the plurality of memory stacks, the method further comprises:

etching the first conductive layer and the storage material lamination which are stacked along the first direction to respectively form a plurality of first rectangular rings which are arranged in parallel along the second direction and a plurality of storage laminations which are arranged in parallel along the second direction;

the first direction is perpendicular to the plane where the second direction and the third direction are located.

Exemplarily, referring to fig. 5a, a substrate structure 100 and a first stack structure 200 are formed in a stacked arrangement.

Illustratively, the first stacked structure 200 covering the substrate structure 100 may be formed by a thin film deposition process. The thin film deposition process includes, but is not limited to, a Chemical Vapor Deposition (CVD) process, a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, an Atomic Layer Deposition (ALD) process, or a combination thereof.

In some embodiments, the forming the first stacked structure covering the substrate structure includes: a first conductive layer, a memory material stack, and a sacrificial layer are formed stacked in a first direction.

Exemplarily, referring to fig. 5a, a first conductive layer 201, a memory material stack and a sacrificial layer 210 are sequentially formed on a substrate structure 100. Here, a memory material stack, comprising: the first adhesive layer 202, the first electrode layer 203, the gate layer 204, the second electrode layer 205, the first barrier layer 206, the phase-change memory layer 207, the second barrier layer 208, and the third electrode layer 209 are sequentially stacked in the z direction.

A substrate structure 100 comprising: a substrate 101, an interconnect line 102, a first dielectric layer 103, a second dielectric layer 104, and a connection structure 105.

The first stacked structure 200 includes: the phase change memory device comprises a first conductive layer 201, a first adhesive layer 202, a first electrode layer 203, a gate layer 204, a second electrode layer 205, a first barrier layer 206, a phase change memory layer 207, a second barrier layer 208, a third electrode layer 209 and a first sacrificial layer 210 which are sequentially stacked along the z direction.

The constituent materials of the substrate 101 include: a semiconductor material. Such as elemental semiconductor materials (silicon, germanium), group iii-v compound semiconductor materials, group ii-vi compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art.

The constituent materials of the interconnect line 102 include: a conductive material. Such as copper or aluminum, etc.

The composition materials of the first dielectric layer 103 and the second dielectric layer 104 include: an oxide or a nitride. For example, silicon oxide or silicon nitride.

The constituent materials of the connection structure 105 include: a conductive material. Such as tungsten, tantalum nitride, titanium nitride, or the like.

The composition materials of the first conductive layer 201, the first barrier layer 206 and the second barrier layer 208 include: a conductive material. Such as tungsten, tantalum, or titanium nitride.

The composition material of the first adhesive layer 202 includes: a metal nitride. Such as tungsten nitride or titanium nitride.

The constituent materials of the first electrode layer 203, the second electrode layer 205, and the third electrode layer 209 include: carbon materials such as amorphous carbon (alpha phase carbon) or carbon nanotubes. The first electrode layer 203, the second electrode layer 205 and the third electrode layer 209 are all electrode layers, and include materials which may be the same or different, and different reference numerals are only used for distinguishing the differences in positions and are not necessarily used for describing a specific sequence or precedence order.

The material composition of the gate layer 204 includes: threshold selection switch (Ovonic threshold switching OTS) material, e.g. Zn_aTe_b、Ge_aTe_b、Nb_aO_bOr Si _aAs_bTe_cAnd the like. Here, a, b, and c may include positive numbers.

The composition materials of the phase-change memory layer 207 include: chalcogenide-based alloys. For example, a GST (Ge-Sb-Te) alloy. The constituent material of the phase-change memory layer 207 may also include any other suitable phase-change material.

The composition material of the first sacrificial layer 210 includes: a nitride; for example, silicon nitride, silicon oxynitride, or the like.

Illustratively, referring to fig. 5b, the first stacked structure 200 is etched along the z-direction to form first stacked bodies and first gaps 330 alternately arranged along the x-direction in the first storage regions 300 of the first stacked structure 200, the first stacked bodies including the first rectangular ring 310 and the storage stacks 320. And a first groove 340 is formed in the first connection region of the first stacked structure 200.

It is understood that by etching down in the z direction, a plurality of first gaps 330 juxtaposed in the x direction may be formed, the plurality of first gaps 330 dividing the first conductive layer 201 into a plurality of first rectangular loops 310 juxtaposed in the x direction, each first rectangular loop 310 extending in the y direction; dividing the memory material stack into a plurality of memory stacks 320 juxtaposed along the x-direction, each memory stack 320 extending along the y-direction; the first sacrifice layer 210 is divided into a plurality of first sacrifice strips juxtaposed in the x direction, each of which extends in the y direction.

Next, a first mask region and a second mask region are formed.

Exemplarily, as shown with reference to fig. 5b, 5c and 5d, the first gap 330 and the first groove 340 are filled to form a first isolation structure 410' in the first storage region 300 and the first connection region 400. A first masking material layer 420 'is formed covering the first isolation structure 410' and the first stacked body. The first masking material layer 420' is patterned to form first and

second masking regions

421 and 422 arranged alternately in the x-direction, as shown in fig. 5 d. It will be appreciated that first and

second mask regions

421 and 422, which are alternately disposed along the x-direction, can constitute the first mask layer 420. Fig. 5d shows a top view of the first rectangular ring 310 and the first mask layer 420. Referring to FIG. 5d, the first mask layer 420, located in the first memory region 300, includes first and

second mask regions

421 and 422 alternately arranged along the x-direction, the first mask regions 421 overlying the predefinable formation regions of the first set of conductive lines and the second mask regions 422 overlying the predefinable formation regions of the second set of conductive lines.

It is noted that a memory stack 320 is also included between the first rectangular ring 310 and the first mask layer 420, and the memory stack 320 is not shown in fig. 5d in order to facilitate the communication of the present disclosure to a person skilled in the art.

Then, a first conductive line is formed.

Illustratively, with reference to fig. 5d and 5e, the first mask layer 420 is used as an etching mask layer to etch the first isolation structure 410' and the end portion of the first rectangular ring 310 downward along the z-direction, so as to form the structure shown in fig. 5 e. It is understood that during the etching process, the first isolation structure 410' in the first connection region 400 is removed to form the first isolation layer 410 in the first storage region 300. The end portions of the first rectangular rings 310 not covered by the first mask layer 420 are removed to form a plurality of first conductive lines 311.

It is understood that during the etching process, the exposed ends of the first rectangular ring 310 under the first mask region 421 can be removed to form the first set of conductive lines 3111 according to the etching down of the first mask region 421, and the exposed ends of the first rectangular ring 310 under the second mask region 422 can be removed according to the etching down of the second mask region 422 to form the second set of conductive lines 3112.

Fig. 5f shows a top view of the first conductive line 311. Referring to fig. 5d, the first conductive lines 311 include a first group of conductive lines 3111 and a second group of conductive lines 3112 alternately arranged in the x-direction; along the y-direction, the ends of the first set of conductive lines 3111 are not flush with the ends of the second set of conductive lines 3112.

In some embodiments, said first direction wherein the ends of the first mask regions are not flush with the ends of the second mask regions comprises:

the length of the first mask region is different from the length of the second mask region along the third direction, and a centerline of the first mask region along the second direction coincides with a centerline of the second mask region along the second direction.

Illustratively, referring to fig. 5d, the first mask region 421 and the second mask region 422 have different lengths along the y-direction, and a center line of the first mask region 421 along the x-direction coincides with a center line of the second mask region 422 along the x-direction.

It is noted that here the centre line of the first mask area in the second direction represents a straight line through the centre of the first mask area and parallel to the second direction. For example, the first mask region 421 shown in fig. 5d is rectangular, a line connecting two diagonal corners of the rectangle 421 can define a center of the rectangle 421, a straight line passing through the center and parallel to the x-direction represents a center line of the first mask region along the second direction, and a straight line passing through the center and parallel to the y-direction represents a center line of the first mask region along the third direction. The second mask region is the same, and is not described herein again.

It is understood that the first conductive lines shown in fig. 3b, 3d and 5f can be formed by using the first mask region and the second mask region in the embodiments of the present disclosure as etching mask layers.

the length of the first mask region is the same as the length of the second mask region along the third direction, and the center line of the first mask region along the second direction is a first preset distance away from the center line of the second mask region along the second direction.

It is understood that the first conductive line shown in fig. 3c and 3e can be formed by using the first mask region and the second mask region in the embodiments of the present disclosure as an etching mask layer.

In some embodiments, after forming the first conductive lines, before forming third masked regions and fourth masked regions alternately arranged in a third direction on the plurality of second rectangular loops, further comprises:

etching the storage lamination and a second conductive layer formed on the storage lamination to respectively form a plurality of phase change storage units distributed in an array manner and a plurality of second rectangular rings arranged in parallel along a third direction;

The first conductive line, the phase change memory unit and the second conductive line are sequentially stacked along a first direction.

Fig. 5g shows a cross-sectional view of fig. 5e at line EE'. Referring to fig. 5g, the method further includes: a second conductive layer 502 is formed over the plurality of memory stacks 320. Illustratively, a second adhesive layer 501, a second conductive layer 502, and a second sacrificial layer 503 covering the first isolation layer 410 and the memory stack 320 are sequentially formed along the z-direction. Here, the material of the second adhesive layer 501 may be the same as that of the first adhesive layer 202, the material of the second conductive layer 502 may be the same as that of the first conductive layer 201, and the material of the second sacrificial layer 503 may be the same as that of the first sacrificial layer 210.

Illustratively, referring to fig. 5h, the second sacrificial layer 503, the second conductive layer 502, the second adhesion layer 501 and the storage stack 320 are etched along the z-direction to form a second stack and second gaps alternately arranged along the y-direction in the second storage region 600, the second stack including a second rectangular ring 610 and a phase-change memory cell 620. And a second groove is formed in the second connection region 700.

It is understood that a plurality of second gaps juxtaposed in the y-direction may be formed by etching down in the z-direction, the second gaps exposing the first conductive lines 311, the plurality of second gaps separating the second conductive layer 502 into a plurality of second rectangular loops 610 juxtaposed in the y-direction, each second rectangular loop 610 extending in the x-direction; the memory stack 320 is divided into a plurality of phase change memory cells 620 arranged in an array in the xoy plane, and each phase change memory cell 620 is electrically insulated from each other; the second sacrifice layer 503 is divided into a plurality of second sacrifice strips juxtaposed in the y direction, each of which extends in the x direction.

Next, a third mask region and a fourth mask region are formed.

Exemplarily, as shown with reference to fig. 5h and 5i, the second gap and the second groove are filled to form a second isolation structure 710' in the second storage region 600 and the second connection region 700. A second masking material layer 720 'is formed overlying the second isolation structures 710' and the second stack. The second masking material layer 720' is patterned to form third and

fourth masking regions

721, 722 that are alternately arranged in the y-direction, as shown in fig. 5 i. It will be appreciated that the third 721 and fourth 722 mask regions alternating in the y-direction can constitute the second mask layer 720.

Fig. 5i shows a top view of the second rectangular ring 610 and the second mask layer 720. Referring to FIG. 5i, the second mask layer 720, located in the second memory region 600, includes third mask regions 721 and fourth mask regions 722 alternately arranged along the y-direction, the third mask regions 721 overlying the predefinable formation regions for the third set of conductive lines and the fourth mask regions 722 overlying the predefinable formation regions for the fourth set of conductive lines.

It is noted that a phase change memory cell 620 is also included between the second rectangular ring 610 and the second mask layer 720, and in order to facilitate the communication of the present disclosure to those skilled in the art, the phase change memory cell 620 is not shown in fig. 5 i.

Thereafter, a second conductive line is formed.

Illustratively, with reference to fig. 5i and 5j, the second mask layer 720 is used as an etching mask layer to etch the second isolation structure 710' and the end portion of the second rectangular ring 610 downward along the z-direction, so as to form the structure shown in fig. 5 j. It is to be understood that during the etching process, the second isolation structure 710' in the second connection region 700 is removed to form a second isolation layer 710 in the second storage region 600. The end portions of the second rectangular rings 610 not covered by the second mask layer 720 are removed to form a plurality of second conductive lines 611.

It is understood that during the etching process, the exposed ends of the second rectangular loop 610 under the third mask region 721 can be removed to form the third set of conductive lines 6111 according to etching down the third mask region 721, and the exposed ends of the second rectangular loop 610 under the fourth mask region 722 can be removed to form the fourth set of conductive lines 6112 according to etching down the fourth mask region 722.

Fig. 5k shows a top view of the second conductive line 611. Referring to fig. 5k, the second conductive line 611 includes a third group of conductive lines 6111 and a fourth group of conductive lines 6112 alternately arranged in the y-direction; the ends of the third set of conductive lines 6111 and the fourth set of conductive lines 6112 are not flush along the x-direction.

In some embodiments, said second direction wherein the ends of the third mask region are not flush with the ends of the fourth mask region comprises:

the third mask region has a length along the second direction that is different from the length of the fourth mask region, and a centerline of the third mask region along the third direction coincides with a centerline of the fourth mask region along the third direction.

Illustratively, referring to FIG. 5i, the third mask region 721 is of a different length than the fourth mask region 722 along the x-direction, and a centerline of the third mask region 721 along the y-direction coincides with a centerline of the fourth mask region 722 along the y-direction.

It is noted that here the centre line of the third mask area in the third direction represents a straight line through the centre of the third mask area and parallel to the third direction. For example, the third mask area 721 shown in fig. 5i is rectangular, a line connecting two diagonal corners of the rectangle 721 may define a center of the rectangle 721, a line passing through the center and parallel to the y-direction represents a center line of the third mask area along the third direction, and a line passing through the center and parallel to the x-direction represents a center line of the third mask area along the second direction. The fourth mask region is the same, and is not described herein again.

It is understood that, using the third mask region and the fourth mask region in the embodiments of the present disclosure as etching mask layers, the second conductive line can be formed as shown in fig. 3b, 3c, and 5 i.

the third mask region has a length along the second direction that is the same as the fourth mask region, and a centerline of the third mask region along the third direction is a second predetermined distance from a centerline of the fourth mask region along the third direction.

It is understood that the second conductive line shown in fig. 3d and 3e can be formed by using the third mask region and the fourth mask region in the embodiments of the present disclosure as etching mask layers.

Fig. 6 is a flow chart illustrating another method of fabricating a phase change memory according to an embodiment of the disclosure.

Referring to fig. 6, the method includes the steps of:

s210: forming first and second mask regions on the plurality of memory stacks alternately arranged in a second direction; wherein, along the third direction, the end of the first mask region is not flush with the end of the second mask region;

S220: etching the first rectangular ring according to the first mask region and the second mask region to form a first group of conductive lines and a second group of conductive lines which are alternately arranged along a second direction so as to form a first conductive line; wherein the second direction and the third direction intersect and are parallel to the same plane.

In some embodiments, after forming the first and second sets of conductive lines alternating along the second direction, the method further comprises:

forming a second mask layer on the plurality of second rectangular rings; wherein, along the second direction, the end of the second mask layer is flush; and etching the second rectangular ring according to the second mask layer to form a plurality of second conductive wires which are arranged in parallel along the third direction and are flush with the end parts along the second direction.

Compared with the related art in which a plurality of first conductive lines are formed in parallel along the second direction and have flush ends, and a plurality of second conductive lines are formed in parallel along the third direction and have flush ends, by using the method in the embodiment of the present disclosure, a first group of conductive lines and a second group of conductive lines can be formed, wherein the first group of conductive lines and the second group of conductive lines are alternately formed along the second direction and have non-flush ends, so as to form the first conductive lines, and a plurality of second conductive lines are formed in parallel along the third direction and have flush ends along the second direction.

Fig. 7 is a flowchart illustrating a method of fabricating a phase change memory according to an embodiment of the present disclosure.

Referring to fig. 7, the method includes the steps of:

s310: forming third mask regions and fourth mask regions alternately arranged in a third direction on the plurality of second rectangular rings; wherein, along the second direction, an end of the third mask region is not flush with an end of the fourth mask region;

s320: etching a plurality of second rectangular rings according to the third mask region and the fourth mask region to form a third group of conductive lines and a fourth group of conductive lines which are alternately arranged along a third direction so as to form second conductive lines; wherein the second direction and the third direction intersect and are parallel to the same plane.

In some embodiments, before forming the third mask regions and the fourth mask regions alternately arranged in the third direction on the second rectangular rings, the method further includes:

forming a first mask layer on the plurality of memory stacks; wherein, along the third direction, the end of the first mask layer is flush; etching the first rectangular ring according to the first mask layer to form a plurality of first conductive wires which are arranged in parallel along the second direction and are flush with the end portions of the first rectangular ring along the third direction;

compared with the related art in which a plurality of first conductive lines are formed in parallel along the second direction and have flush end portions, and a plurality of second conductive lines are formed in parallel along the third direction and have flush end portions, by using the method in the embodiment of the present disclosure, a plurality of first conductive lines can be formed in parallel along the second direction and have flush end portions along the third direction, and a third group of conductive lines and a fourth group of conductive lines can be formed in an alternating manner along the third direction and have non-flush end portions, so as to form the second conductive lines.

Fig. 8 is a flowchart illustrating a method for locating a phase change memory according to an embodiment of the disclosure. The method is used for positioning the phase change memory cell included in the phase change memory in any of the embodiments, and as shown in fig. 8, the method includes the following steps:

s410: when the phase change memory is indicated to comprise a target phase change memory unit which does not meet the preset requirement in the electrical detection result of the phase change memory, acquiring a position parameter indicating the position of the target phase change memory unit according to the detection result; wherein the location parameters at least include: indicating a first number of a target first conductive line electrically connected to a target phase change memory cell and a second number of a target second conductive line electrically connected to the target phase change memory cell;

s420: obtaining a first number of first conductive lines included in each first set of conductive lines and obtaining a second number of first conductive lines included in each second set of conductive lines; determining a location of a target first conductive line according to the first number, and the second number; locating an actual position of a target phase change memory cell in the phase change memory according to the position of the target first conductive line and the second number;

and/or the presence of a gas in the gas,

Obtaining a third number of second conductive lines included in each third set of conductive lines and obtaining a fourth number of second conductive lines included in each fourth set of conductive lines; determining the position of the target second conductive line according to the second number, the third number and the fourth number; the actual location of the target phase change memory cell in the phase change memory is located according to the location of the target second conductive line and the first number.

The positioning method of the present disclosure will be further described in detail below by taking the phase change memory 2000 shown in fig. 3b as an example.

Illustratively, the phase change memory 2000 is wafer tested and the test results are obtained. When the detection result indicates that the phase change memory cell 2200 ' is failed, the first number 16 (e.g., the 16 th first conductive line from left to right) of the first conductive line 2100 electrically connected to the phase change memory cell 2200 ' is acquired, and the second number 16 (e.g., the 16 th second conductive line from top to bottom) of the second conductive line 2300 electrically connected to the phase change memory cell 2200 ' is acquired.

The first set of conductive lines includes a first number of first conductive lines of 4 and the second set of conductive lines includes a second number of first conductive lines of 4, and the phase change memory cell 2200' is located on the second set of conductive lines based on the first number 16, the first number 4, and the second number 4.

The third set of conductive lines includes a third number of second conductive lines of 4 and the fourth set of conductive lines includes a fourth number of second conductive lines of 4, and the phase change memory cells 2200' are precisely located at the second fourth set of conductive lines according to the second number 16, the third number 4, and the fourth number 4.

By using the positioning method of the embodiment of the disclosure, when the phase change memory is electrically tested, the phase change memory unit can be accurately and quickly positioned, and the accuracy of failure analysis is improved.

Fig. 9 is a schematic structural diagram of a reticle 3000 according to an embodiment of the present disclosure. The mask 3000 is used in the method for manufacturing the phase change memory in any of the embodiments to form the phase change memory in any of the embodiments, and referring to fig. 9, the mask 3000 includes:

oppositely disposed first 3100 and second 3200 sides; wherein the first side surface 3100 includes first convex portions 3110 and first concave portions 3120 alternately arranged; the second side 3200 includes second convex portions 3210 and second concave portions 3220 alternately arranged or second concave portions and second convex portions alternately arranged.

The mask 3000 comprises the following materials: and (3) chromium.

Exemplarily, the first side surface 3100 includes first convex portions 3110 and first concave portions 3120 alternately arranged; when the second side 3200 includes the second protrusions 3210 and the second recesses 3220 alternately, the first mask layer 420 in fig. 5d may be formed by exposing and developing the first mask material layer 420' in fig. 5c using a mask according to the embodiment of the present disclosure, and the first rectangular ring 310 is etched according to the first mask layer 420, so as to form the first set of conductive lines and the second set of conductive lines as shown in fig. 3b and 3 d.

It is understood that the first side surface includes first convex portions and first concave portions alternately arranged; when the second side surface includes the second concave portions and the second convex portions which are alternately arranged, the first group of conductive lines and the second group of conductive lines as shown in fig. 3c and 3e can be formed by using the mask in the embodiment of the present disclosure.

Exemplarily, the first side surface 3100 includes first convex portions 3110 and first concave portions 3120 alternately arranged; when the second side 3200 includes the second protrusions 3210 and the second recesses 3220 alternately, the second mask layer 720 in fig. 5i may be formed by performing an exposure and development process on the second mask material layer 720' in fig. 5h by using a mask in the embodiment of the present disclosure, and the second rectangular ring 610 is etched according to the second mask layer 720, so as to form the third group of conductive lines and the fourth group of conductive lines as shown in fig. 3b and 3 c.

It is understood that the first side surface includes first convex portions and first concave portions alternately arranged; when the second side surface includes the second concave portions and the second convex portions which are alternately arranged, the third group of conductive lines and the fourth group of conductive lines as shown in fig. 3d and 3e can be formed by using the mask in the embodiment of the present disclosure.

It is understood that the mask shown in fig. 9 is merely an illustration for conveying the disclosure to those skilled in the art, and those skilled in the art can reasonably set the sizes of the first convex portion and the first concave portion and the second convex portion and the second concave portion according to the design requirements in the actual phase change memory manufacturing process.

In the embodiments provided in the present disclosure, it should be understood that the disclosed apparatus, system, and method may be implemented in other ways. The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A phase change memory, comprising:

and/or the presence of a gas in the gas,

2. The phase change memory of claim 1, wherein the ends of the first set of conductive lines are not flush with the ends of the second set of conductive lines, comprising:

or the like, or, alternatively,

3. The phase change memory of claim 1, wherein the ends of the third set of conductive lines are not flush with the ends of the fourth set of conductive lines, comprising:

or the like, or, alternatively,

4. The phase change memory of claim 2, wherein the first preset distance ranges between 80nm and 120nm when the length of the first set of conductive lines is the same as the length of the second set of conductive lines;

or the like, or, alternatively,

5. The phase change memory of claim 3, wherein the second predetermined distance ranges between 80nm and 120nm when the length of the third set of conductive lines is the same as the length of the fourth set of conductive lines;

Or the like, or, alternatively,

6. The phase change memory according to claim 1,

the first set of conductive lines includes: a plurality of first sub-conductive lines are arranged in parallel along the second direction;

7. A method for manufacturing a phase change memory, the method comprising:

And/or the presence of a gas in the gas,

8. The method of claim 7 wherein said end of said first mask region being non-flush with an end of said second mask region along said third direction comprises:

or the like, or, alternatively,

9. The method of claim 7 wherein said ends of said third mask region being non-flush with ends of said fourth mask region along said second direction comprises:

or the like, or, alternatively,

10. The method of claim 7, wherein prior to the step of forming first and second mask regions on the plurality of memory stacks alternating in the second direction, the method further comprises:

11. The method of claim 10, further comprising, after forming the first conductive line, prior to forming the third and fourth masked regions on the plurality of second rectangular loops alternately arranged in the third direction:

12. A method for locating a phase change memory cell included in the phase change memory according to any one of claims 1 to 6, the method comprising:

when the phase change memory is indicated to comprise a target phase change memory unit which does not meet the preset requirement in the electrical detection result of the phase change memory, acquiring a position parameter indicating the position of the target phase change memory unit according to the electrical detection result; wherein the location parameters include at least: indicating a first number of a target first conductive line electrically connected to the target phase change memory cell and a second number of a target second conductive line electrically connected to the target phase change memory cell;

and/or the presence of a gas in the gas,

13. A mask used in the method for manufacturing the phase change memory according to any one of claims 7 to 11 to form the phase change memory according to any one of claims 1 to 6, comprising: