CN113517334A - Power MOSFET device with high-K dielectric groove and preparation method thereof - Google Patents
Power MOSFET device with high-K dielectric groove and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a power MOSFET device with a high-K dielectric groove and a preparation method thereof, wherein the device sequentially comprises the following components from bottom to top: the device comprises a first metal layer, an N + substrate, an N-epitaxial layer and a main body structure layer; the N-epitaxial layer is internally provided with a plurality of groove well structures, the groove well structures extend downwards from the upper surface of the N-epitaxial layer, and the depth of the groove well structures is smaller than the thickness of the N-epitaxial layer; a high-K dielectric groove is arranged between two adjacent groove well structures, and the depth of the high-K dielectric groove is the same as the thickness of the N-epitaxial layer; the upper surface of the high-K dielectric groove region is provided with a groove gate, the groove gate is positioned between two adjacent main body structure layers, and a second metal layer is arranged on the groove gate; and a device source electrode is formed on the main body structure layer. The power MOSFET device provided by the invention combines the trench gate, the high-K dielectric trench and the trench well, obtains the maximum breakdown voltage, reduces the on-resistance to the maximum extent and improves the device performance.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a power MOSFET device with a high-K dielectric trench and a preparation method thereof.
Background
With the continuous development of semiconductor technology, higher requirements are put on power devices in electronic power systems. A Power Metal-Oxide-Semiconductor Field Effect Transistor (Power MOSFET), also called a Power MOSFET, is a Field Effect Transistor that controls drain current with gate voltage, and has the remarkable characteristics of simple driving circuit, low driving Power, high switching speed and high operating frequency; however, the current capacity is small, the withstand voltage is low, and the power electronic device is only used for a low-power electronic device and cannot be widely applied to the high-voltage field.
In recent years, efforts have been made to improve the relationship between the on-resistance Ron and the breakdown voltage VB of the field effect transistor, and attempts have been made to obtain the minimum on-resistance while maintaining a high breakdown voltage. In 1991, Chen Xin assist of electronics technology university independently proposed a Composite Buffer (CB) structure, and proposed that the structure has Ron ^ VB1.32This successfully breaks the "silicon limit" of conventional voltage barriers. The CB structure is also a Super Junction (SJ) voltage-resistant layer which is well known at present. A MOSFET using a super junction voltage withstanding layer is called a super junction MOSFET (SJ-MOSFET). The on-resistance of the SJ-MOSFET can be an order of magnitude lower than that of a conventional power MOSFET at the same breakdown voltage.
However, based on the development of the electronic power technology, the existing super junction MOSFET device performance methods such as low on-resistance and high breakdown voltage still cannot use all scenes; in addition, the existing super junction MOSFET has a certain charge balance problem, which limits the application range to some extent.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a power MOSFET device having a high-K dielectric trench and a method for fabricating the same. The technical problem to be solved by the invention is realized by the following technical scheme:
a power MOSFET device having a high-K dielectric trench comprising, in order from bottom to top: the device comprises a first metal layer, an N + substrate, an N-epitaxial layer and a main body structure layer; wherein,
a plurality of groove trap structures are arranged in the N-epitaxial layer, extend downwards from the upper surface of the N-epitaxial layer and are smaller than the thickness of the N-epitaxial layer in depth;
a high-K dielectric groove is arranged between two adjacent groove well structures, and the depth of the high-K dielectric groove is the same as the thickness of the N-epitaxial layer; the trench well structure, the high-K dielectric trench, and the N-epitaxial layer therebetween together form a three-dimensional super junction structure;
the upper surface of the high-K dielectric groove region is provided with a groove gate, the groove gate is positioned between two adjacent main structure layers, and a second metal layer is arranged on the groove gate;
and a device source electrode is formed on the main body structure layer.
In one embodiment of the invention, the doping concentration of the trench well structure is gradually reduced from bottom to top.
In one embodiment of the present invention, the trench well structure includes a first trench well and a second trench well; the second trench well starts from the upper surface of the N-epitaxial layer and extends towards the inside of the N-epitaxial layer;
the first groove trap is positioned below the second groove trap and has a certain distance with the N-epitaxial layer so as to form a depletion region.
In one embodiment of the present invention, a width of the first trench well is smaller than a width of the second trench well.
In one embodiment of the present invention, a depth of the first trench well is smaller than a depth of the second trench well.
In one embodiment of the present invention, the ion doping concentration of the first trench well is greater than the ion doping concentration of the second trench well.
In an embodiment of the present invention, the body structure layer includes a P + substrate, an N + doped region, and a P + doped region, the P + substrate is located on the N-epitaxial layer, the N + doped region and the P + doped region are both located on the P + substrate, and the P + doped region is located between two N + doped regions.
In one embodiment of the present invention, an ion doping concentration of the P + substrate is greater than an ion doping concentration of the second trench well and less than an ion implantation concentration of the P + doping region.
In one embodiment of the present invention, the high-K dielectric trench region is formed by high-K dielectric ion implantation, the high-K dielectric ions comprising a nitride or a metal oxide.
Another embodiment of the present invention also provides a method for fabricating a power MOSFET device having a high-K dielectric trench, comprising the steps of:
selecting a first metal layer as a device drain electrode, and growing an N + substrate on the first metal layer;
epitaxially growing an N-epitaxial layer on the N + substrate for multiple times, and performing etching and ion implantation after each growth to form a trench well structure;
performing ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region;
performing ion implantation on the surface of the sample for multiple times to form a main structure layer;
and manufacturing a trench gate structure and a source electrode to finish the preparation of the device.
The invention has the beneficial effects that:
1. according to the invention, the groove well structure is arranged in the epitaxial layer of the device to form a depletion region between the groove well and the epitaxial layer, so that the area of the depletion region of the device is increased, the breakdown voltage is improved, meanwhile, the high-K dielectric groove structure is also arranged between the groove well structures, the electric field distribution in the drift region is changed, the transverse component of the electric field is reduced, the vertical electric field is uniformly distributed, and the breakdown voltage is further improved;
2. the K dielectric groove structure is formed by adopting a high-K dielectric substance ion implantation technology, and a part of N & lt- & gt drift region is replaced, so that the equivalent dielectric constant of the drift region is increased, the electric field is optimized, and the charge balance problem is improved; meanwhile, for a high-K dielectric, the higher the dielectric constant is, the stronger the MIS capacitance effect is, so that the device has higher impurity concentration and smaller on-resistance;
3. the ion implantation concentration of the trench well structure is set to be in a non-uniform mode which is gradually reduced from bottom to top, and the relationship between breakdown voltage and on-resistance is compromised under the condition that a depletion region is kept to be the largest;
4. the power MOSFET device with the high-K dielectric groove combines the groove gate, the high-K dielectric groove and the groove well, obtains the maximum breakdown voltage, reduces the on-resistance to the maximum extent and improves the device performance.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention;
FIG. 2a is an equipotential surface of a conventional trench;
FIG. 2b is an equipotential surface of a high-K dielectric trench provided by an embodiment of the present invention;
fig. 3 is a flowchart of a method for fabricating a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention;
FIGS. 4a-4j are schematic diagrams illustrating a process for fabricating a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention;
description of reference numerals:
1-a first metal layer; a 2-N + epitaxial region; a 3-N-epitaxial region; 4-a first trench well; 5-a second trench well; 6-high-K dielectric trenches; a 7-P + implantation region; 8-a trench gate; a 9-N + implant region; a 10-P + implant region; 11-a third metal layer; 12-a silicon dioxide layer; 13-second metal layer.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention, which sequentially includes, from bottom to top: the structure comprises a first metal layer 1, an N + substrate 2, an N-epitaxial layer 3 and a main body structure layer; wherein,
a plurality of groove trap structures are arranged in the N-epitaxial layer 3, extend downwards from the upper surface of the N-epitaxial layer 3, and the depth of the groove trap structures is smaller than the thickness of the N-epitaxial layer 3;
a high-K dielectric trench 6 is arranged between two adjacent trench well structures, and the depth of the high-K dielectric trench 6 is the same as the thickness of the N-epitaxial layer 3; the trench well structure, the high-K dielectric trench 6 and the N-epitaxial layer 3 therebetween together form a three-dimensional super junction structure;
the upper surface of the high-K dielectric groove region 6 is provided with a groove gate 8, the groove gate 8 is positioned between two adjacent main structure layers, and a second metal layer 11 is arranged on the groove gate;
a device source 13 is formed on the body structure layer.
Specifically, the first metal layer 1 is the drain of the MOSFET device and is located on the back side of the N + substrate region 2. The second metal layer 13 is used to provide the trench gate 8 with a gate voltage.
In the embodiment, the trench gate structure is adopted, so that the channel length is shortened compared with a planar gate structure, and the high-K dielectric trench below the trench can adjust the distribution of current carriers and reduce the on-resistance.
Further, the trench well structure may include a plurality of vertically distributed trench wells, the doping concentration of which is gradually decreased from bottom to top. In the embodiment, the ion implantation concentration of the trench well structure is set to be in a non-uniform mode which is gradually reduced from bottom to top, and the relationship between the breakdown voltage and the on-resistance is compromised under the condition that the depletion region is kept to be the maximum.
For example, in the present embodiment, the trench well structure may include a first trench well 4 and a second trench well 5; the second trench well 5 starts from the upper surface of the N-epitaxial layer 3 and extends towards the inside of the N-epitaxial layer 3;
the first trench well 4 is located below the second trench well 5 with a certain distance from the N-epitaxial layer 3 to form a depletion region.
Wherein, the width and the depth of the first trench trap 4 are both smaller than the width and the depth of the second trench trap 5, and the ion doping concentration of the first trench trap 4 is greater than the ion doping concentration of the second trench trap 5.
In the present embodiment, the first trench well and the second trench well use a deep trench filling technique, that is, in the deep trench filling method, the plurality of first trench wells and the plurality of second trench wells may be generated by an epitaxial method or chemical vapor deposition.
Furthermore, the present embodiment also forms the high-K dielectric trench region 6 by high-K dielectric ion implantation, wherein the high-K dielectric ions comprise nitride or metal oxide, such as Si3N4、Al2O3、TiO2And the like.
Specifically, in the embodiment, a high-K dielectric trench structure is formed by adopting a high-K dielectric ion implantation technology, and a part of an N-drift region is replaced, so that the equivalent dielectric constant of the drift region is increased, an electric field is optimized, and the charge balance problem is improved; meanwhile, for a high-K dielectric, the higher the dielectric constant is, the stronger the MIS capacitance effect is, so that the device has higher impurity concentration and smaller on-resistance.
Referring to fig. 2a-2b, fig. 2a is an equipotential surface of a conventional common channel, and fig. 2b is an equipotential surface of a high-K dielectric trench according to an embodiment of the present invention; comparing fig. 2a and 2b, it can be seen that the high-K material trench alters the electric field distribution in the drift region making it more uniform and compact. Due to the modulation of the HK species on the E-field, the lateral component of the electric field is very small and the vertical electric field distribution is very uniform, thus achieving a very high breakdown voltage.
Multiple experiments have shown that the extended high-K material trench brings more MIS capacitance in the drift region, thereby enhancing assisted depletion, and therefore the on-resistance is reduced and the sensitivity to charge balance is also weakened. The breakdown voltage is raised by twelve percent and the on-resistance is reduced by fifty percent compared to a mosfet device without a dielectric trench.
This embodiment is through set up the trench well structure in the device epitaxial layer in order to form the depletion region between trench well and epitaxial layer, has increased device depletion region area, has improved breakdown voltage, simultaneously, still is provided with high K dielectric trench structure between the trench well structure, has changed the electric field distribution in the drift region, makes the transverse component of electric field reduce, and vertical electric field distributes evenly, has further promoted breakdown voltage.
In this embodiment, the body structure layer includes a P + substrate 7, an N + doped region 9 and a P + doped region 10, the P + substrate 7 is located on the N-epitaxial layer 3, the N + doped region 9 and the P + doped region 10 are both located on the P + substrate 7, and the P + doped region 10 is located between the two N + doped regions 9.
The ion doping concentration of the P + substrate 7 is greater than that of the second trench well 5 and less than that of the P + doping region 10.
Furthermore, a third metal layer 11 is disposed on the P + doped region 10 and a portion of the N + doped region 9 to serve as a source of the device, and the third metal layer 11 is separated from the second metal layer 13 by a silicon dioxide layer 12.
The power MOSFET device with the high-K dielectric groove combines the groove gate, the high-K dielectric groove and the groove well, obtains the maximum breakdown voltage, reduces the on-resistance to the maximum extent and improves the device performance.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing a power MOSFET device having a high-K dielectric trench. Referring to fig. 3, fig. 3 is a flowchart of a method for manufacturing a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention, which includes the following steps:
s1: selecting a first metal layer as a device drain electrode, and growing an N + substrate on the first metal layer;
s2: epitaxially growing an N-epitaxial layer on the N + substrate for multiple times, and etching and implanting ions after each growth to form a trench well structure;
s3: performing ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region;
s4: performing ion implantation on the surface of the sample for multiple times to form a main structure layer;
the main structure layer comprises a P + substrate, an N + doping region and a P + doping region, the P + substrate is located on the upper portion of the N-epitaxial layer, the N + doping region and the P + doping region are located on the P + substrate, and the P + doping region is located between the two N + doping regions.
S5: and manufacturing a trench gate structure and a source electrode to finish the preparation of the device.
In the process of preparing the power MOSFET device with the high-K dielectric groove, the multi-time epitaxy technology and the ion implantation technology are adopted, so that the process difficulty is reduced.
The preparation process of the present invention will be described in detail below with reference to the accompanying drawings. Referring to fig. 4a-4j, fig. 4a-4j are schematic views illustrating a manufacturing process of a power MOSFET device having a high-K dielectric trench according to an embodiment of the present invention, which specifically includes:
step 1: a first metal, e.g. copper, is chosen as a first metal layer 1 and an N + substrate 2 is grown thereon, as shown in fig. 4 a.
Specifically, since the conducting channel of the trench power MOSFET is from the source on the surface of the silicon wafer to the drain on the back surface, in order to reduce conduction, the doping concentration of the silicon substrate must be increased as much as possible, and a high-concentration red phosphorus doped silicon substrate is generally used, and the doping concentration is generally 1 × 1013cm-3～1×1013cm-3。
Step 2: a portion of the polysilicon 3 is first epitaxial on the N + substrate 2 as shown in fig. 4 b.
And step 3: and (3) performing groove etching on the epitaxial layer formed by the part of the polycrystalline silicon 3, performing projection and exposure through a photomask, and forming a first groove on the epitaxial monocrystalline silicon by adopting dry etching, as shown in fig. 4 c.
And 4, step 4: p + ion implantation is performed on the first trench by a deep trench filling technique to form a first trench well 4, as shown in fig. 4 d.
Specifically, the doping concentration of the first trench well is 1 × 1015cm-3～1×1017cm-3。
And 5: the epitaxy of the N-material continues in the N-epitaxial layer 3, this time with an epitaxial layer thickness greater than the first, as shown in fig. 4 e.
Step 6: and (3) performing groove etching on the epitaxial layer, performing projection and exposure through a photomask, and forming a second groove on the epitaxial monocrystalline silicon by adopting dry etching, as shown in fig. 4 f.
And 7: p + ion implantation is performed on the second trench by a deep trench filling technique, where the ion concentration is lower than that in the first trench well, to form a second trench well 5, as shown in fig. 4 g.
Specifically, the doping concentration of the second trench well is 1 × 1014cm-3～1×1016cm-3The ion concentration is about one order of magnitude lower compared to the first trench.
And 8: a high-K dielectric trench is formed by ion implantation of a high-K dielectric material, as shown in fig. 4 h.
Specifically, a material having a relative dielectric constant of 100 to 2000, such as TiO, is usually selected for use herein2. The higher the relative dielectric constant of a material, the more intense the electric field in its drift region.
And step 9: continuing to form the P + substrate 7, the N + doped region 9 and the P + doped region 10 on the N-epitaxial layer 3 in sequence by ion implantation, thereby forming a body layer structure during the formation, as shown in fig. 4 i.
Step 10: a trench gate 8 is formed and the entire device surface is covered with metal and silicon dioxide to form the device gate and source as shown in figure 4 j.
To this end, the fabrication of power mosfet devices with extended high-K dielectric trenches and three-dimensional superjunctions is completed.
It is noted that, in the present embodiment, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A power MOSFET device having a high-K dielectric trench comprising, in order from bottom to top: the device comprises a first metal layer (1), an N + substrate (2), an N-epitaxial layer (3) and a main body structure layer; wherein,
a plurality of groove trap structures are arranged in the N-epitaxial layer (3), extend downwards from the upper surface of the N-epitaxial layer (3), and the depth of each groove trap structure is smaller than the thickness of the N-epitaxial layer (3);
a high-K dielectric trench (6) is arranged between two adjacent trench well structures, and the depth of the high-K dielectric trench (6) is the same as the thickness of the N-epitaxial layer (3); the trench well structure, the high-K dielectric trench (6) and the N-epitaxial layer (3) therebetween together form a three-dimensional superjunction structure;
the upper surface of the high-K dielectric groove region (6) is provided with a groove gate (8), the groove gate (8) is positioned between two adjacent main structure layers, and a second metal layer (13) is arranged on the groove gate;
and a device source electrode (13) is formed on the main body structure layer.
2. The power MOSFET device of claim 1, wherein the trench well structure has a doping concentration that gradually decreases from bottom to top.
3. A power MOSFET device according to claim 1, characterized in that the trench well structure comprises a first trench well (4) and a second trench well (5); wherein the second trench well (5) starts from the upper surface of the N-epitaxial layer (3) and extends towards the inside of the N-epitaxial layer (3);
the first groove trap (4) is positioned below the second groove trap (5) and has a certain distance with the N-epitaxial layer (3) to form a depletion region.
4. A power MOSFET device according to claim 3, characterized in that the width of the first trench well (4) is smaller than the width of the second trench well (5).
5. A power MOSFET device according to claim 3, characterized in that the depth of the first trench well (4) is smaller than the depth of the second trench well (5).
6. A power MOSFET device according to claim 3, characterized in that the ion doping concentration of the first trench well (4) is larger than the ion doping concentration of the second trench well (5).
7. A power MOSFET device according to claim 3, characterized in that the body structure layer comprises a P + substrate (7), an N + doped region (9) and a P + doped region (10), the P + substrate (7) being located on the N-epitaxial layer (3), the N + doped region (9) and the P + doped region (10) both being located on the P + substrate (7), and the P + doped region (10) being located between two N + doped regions (9).
8. Power MOSFET device according to claim 6, characterized in that the ion doping concentration of the P + substrate (7) is larger than the ion doping concentration of the second trench well (5) and smaller than the ion implantation concentration of the P + doped region (10).
9. The power MOSFET device of claim 1, wherein the high-K dielectric trench region (6) is formed by high-K dielectric ion implantation, the high-K dielectric ions comprising a nitride or a mos.
10. A method for preparing a power MOSFET device with a high-K dielectric trench is characterized by comprising the following steps:
selecting a first metal layer as a device drain electrode, and growing an N + substrate on the first metal layer;
epitaxially growing an N-epitaxial layer on the N + substrate for multiple times, and performing etching and ion implantation after each growth to form a trench well structure;
performing ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region;
performing ion implantation on the surface of the sample for multiple times to form a main structure layer;
and manufacturing a trench gate structure and a source electrode to finish the preparation of the device.
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