CN113497139A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113497139A
CN113497139A CN202010192561.1A CN202010192561A CN113497139A CN 113497139 A CN113497139 A CN 113497139A CN 202010192561 A CN202010192561 A CN 202010192561A CN 113497139 A CN113497139 A CN 113497139A
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Prior art keywords
opening
forming
isolation
dielectric layer
gate
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Chinese (zh)
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王楠
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202010192561.1A priority Critical patent/CN113497139A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a method of forming the same, wherein the method comprises: providing a substrate, wherein the substrate is provided with a grid structure and an isolation structure, the grid structure extends along a first direction, and the grid structure is positioned on the isolation structure; forming a dielectric layer on the isolation structure, wherein the dielectric layer exposes the top surface of the gate structure; forming a first opening in the dielectric layer, wherein the side wall of the first opening is exposed out of the grid structure, and the surface of the isolation structure is exposed out of the first opening; after the first opening is formed, removing the gate structure exposed from the side wall of the first opening, and forming a second opening in the gate structure, wherein the second opening exposes the surface of the isolation structure, and is adjacent to and communicated with the first opening in a second direction, and the second direction is perpendicular to the first direction; and forming an isolation layer in the first opening and the second opening. The method has the advantages of larger process window, shorter process period and better performance of the formed semiconductor structure.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
In the conventional semiconductor field, a conventional planar metal-oxide semiconductor field effect transistor (MOSFET) has a weak ability to control a channel current, resulting in a serious leakage current. A Fin field effect transistor (Fin FET) is an emerging multi-gate device, which generally includes a Fin portion protruding from a surface of a semiconductor substrate, a gate structure covering a portion of a top surface and a sidewall of the Fin portion, and source-drain doped regions in the Fin portion located at both sides of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor (MOSFET), the fin type MOSFET has stronger short channel inhibition capability and stronger working current, and is widely applied to various semiconductor devices.
However, as the device size is further reduced, the difficulty of forming the isolation in the gate structure of the finfet increases, which hinders the overall circuit performance improvement due to device scaling.
In a Fin field effect transistor (Fin FET) formed by using the conventional process, a process window and device performance need to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of the formed semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor structure, including: the semiconductor device comprises a substrate, a grid structure and an isolation structure, wherein the grid structure extends along a first direction and is positioned on the surface of the isolation structure; the dielectric layer is positioned on the isolation structure and exposes the top surface of the grid structure; the first opening is positioned in the dielectric layer, the surface of the side wall of the grid structure is exposed out of the first opening, and the surface of the isolation structure is exposed out of the first opening; a second opening in the gate structure, the second opening exposing the surface of the isolation structure, the second opening being adjacent to and in communication with the first opening in a second direction, the second direction being perpendicular to the first direction; an isolation layer within the first opening and the second opening.
Optionally, the first opening is also located in a part of the isolation structure.
Optionally, the second opening is also located in a part of the isolation structure.
Optionally, the substrate includes a substrate and a fin portion located on a surface of the substrate, and the gate structure crosses over a portion of a top surface and a sidewall surface of the fin portion.
Optionally, the fin portion includes a plurality of fin portion layers arranged along a normal of the substrate surface, a groove is formed between adjacent fin portion layers, and the gate structure is further located in the groove.
Optionally, the first opening is located between adjacent fin portions, and the second opening is located between adjacent fin portions.
Optionally, the material of the isolation layer includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Optionally, the top surface of the dielectric layer is flush with the top surface of the gate structure, and the top surface of the isolation layer is flush with the top surface of the dielectric layer.
Optionally, the surface of the side wall of the gate structure is provided with a side wall structure; the side wall structure is made of materials including: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a gate structure and an isolation structure, the gate structure extends along a first direction, and the gate structure is positioned on the isolation structure; forming a dielectric layer on the isolation structure, wherein the dielectric layer exposes the top surface of the grid structure; forming a first opening in the dielectric layer, wherein the side wall of the first opening is exposed out of the grid structure, and the surface of the isolation structure is exposed out of the first opening; after the first opening is formed, removing the gate structure exposed from the side wall of the first opening, and forming a second opening in the gate structure, wherein the second opening exposes the surface of the isolation structure, and is adjacent to and communicated with the first opening in a second direction, and the second direction is perpendicular to the first direction; and forming an isolation layer in the first opening and the second opening.
Optionally, the top surface of the dielectric layer is flush with the top surface of the gate structure; the side wall surface of the grid structure is provided with a side wall structure.
Optionally, the method for forming the first opening includes: forming a mask layer on the gate structure and the surface of the dielectric layer, wherein the mask layer exposes part of the surface of the dielectric layer, the gate structure and the surface of the side wall structure; etching the dielectric layer by taking the mask layer as a mask until the surface of the isolation structure is exposed, forming an initial first opening in the dielectric layer, and exposing the side wall structure on the surface of the side wall of the grid structure by the initial first opening; and removing the exposed side wall structure of the initial first opening, forming a first opening in the dielectric layer, and exposing the surface of the grid structure by the first opening.
Optionally, the method for forming the first opening further includes: etching the dielectric layer, and after exposing the isolation structure, over-etching part of the isolation structure; and etching the side wall structure, and after exposing the isolation structure, over-etching part of the isolation structure to form the first opening in the dielectric layer.
Optionally, the method for forming the second opening includes: and after the first opening is formed, etching the gate structure by taking the mask layer as a mask until the surface of the isolation structure is exposed, and forming a second opening in the gate structure, wherein the second opening is adjacent to and communicated with the first opening.
Optionally, the method for forming the second opening further includes: and after the grid structure is etched and the isolation structure is exposed, over-etching part of the isolation structure to form the second opening in the grid structure.
Optionally, the forming method of the dielectric layer includes: forming a dielectric material film covering the gate structure on the isolation structure; and flattening the dielectric material film until the top surface of the grid structure is exposed, and forming the dielectric layer on the isolation structure.
Optionally, the forming method of the isolation layer includes: after the first opening and the second opening are formed, an isolation material film is formed on the surfaces of the first opening, the second opening, the grid structure and the dielectric layer; and flattening the isolating material film until the grid structure and the surface of the dielectric layer are exposed, and forming the isolating layer in the first opening and the second opening.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
according to the forming method of the semiconductor structure provided by the technical scheme of the invention, a first opening is formed in the dielectric layer, and the side wall of the first opening is exposed out of the grid structure; and after the first opening is formed, etching the grid structure exposed by the first opening, thereby forming a second opening in the grid structure. The process difficulty for etching the dielectric layer material is low, so that the first opening is easy to form in the dielectric layer, and the first opening is formed in a good shape. After the first opening is formed, the side wall of the first opening is exposed out of the surface of the grid structure, so that the exposed area of the surface of the grid structure is increased, the subsequent process of etching the grid structure material is facilitated, the process difficulty of forming the second opening penetrating through the grid structure in the grid structure is reduced, the appearance of the formed second opening is good, and the performance of the formed semiconductor structure is further facilitated to be improved. The method has the advantages of larger process window, shorter process period and better performance of the formed semiconductor structure.
Further, after the first opening and the second opening are formed, an isolation material film is filled in the first opening and the second opening, so that an isolation layer is formed in the first opening and the second opening. The first opening and the second opening are adjacent and communicated with each other along the second direction, namely, the size of the first opening and the size of the second opening along the second direction are larger than that of the second opening, so that the difficulty of filling the isolating material film in the first opening and the second opening is reduced, the isolating layer is formed, and the process time and the cost are saved.
Further, the method for forming the first opening further includes: after the dielectric layer is etched to expose the isolation structure, over-etching part of the isolation structure; and etching the side wall structure, and after exposing the isolation structure, over-etching part of the isolation structure. Through over-etching part of the isolation structure, the surface of the side wall of the grid structure can be fully exposed, the difficulty of forming a second opening by subsequently etching the grid structure is reduced, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-5 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 6 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of existing semiconductor structures is poor.
The reason for the poor performance of the semiconductor structure will be described in detail below with reference to the accompanying drawings, and fig. 1 to 5 are schematic structural views of steps of a method for forming a semiconductor structure.
Referring to fig. 1 and 2, fig. 1 is a schematic cross-sectional view taken along a tangential direction of a-a1 in fig. 2, where a tangential line of a-a1 is located between adjacent fins 202, fig. 2 is a top view taken along a direction F (perpendicular to the substrate) in fig. 1, and a substrate 100 is provided, where the substrate 100 includes a fin 101, the substrate 100 has a gate structure 120, an isolation structure 110, and a dielectric layer 130, the gate structure 120 extends along a first direction X and crosses the fin 101, the gate structure 120 is located on the isolation structure 110, and the dielectric layer 130 is located on a surface of the isolation structure 110 and covers sidewalls of the gate structure 120.
Referring to fig. 3 and 4, fig. 3 is a schematic cross-sectional view of the gate structure 120 cut from fig. 1, fig. 4 is a schematic cross-sectional view taken along a direction of a-a1 from fig. 2, and fig. 4 is a schematic view of the mask layer omitted for convenience of illustration.
Forming a mask layer 140 on the surfaces of the gate structure 120 and the dielectric layer 130, wherein the mask layer exposes a part of the gate structure 120; etching the gate structure 120 by using the mask layer as a mask until the surface of the isolation structure 110 is exposed, forming an opening 150 in the gate structure 120, wherein the opening 150 penetrates through the gate structure 120 in a second direction Y, and the second direction Y is perpendicular to the first direction X; after the opening 150 is formed, the mask layer 140 is removed.
Referring to fig. 5, fig. 5 is a schematic view based on fig. 3, and an isolation layer 160 is formed in the opening 150.
In the above method, by etching a part of the gate structure 120, an opening 150 is formed in the gate structure 120, and the opening 150 penetrates through the gate structure 120 along the second direction Y, so that the isolation layer 160 formed in the opening 150 can block the gate structure 120 where the opening 150 is located, thereby meeting the process requirements.
However, since the material of the gate structure 120 includes: metals such as one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride. The difficulty of the metal etching process in the current etching process is still high, and as the process node requirement is smaller, the size of the gate structure 120 is smaller, and the difficulty of forming the opening 150 by etching is higher. In addition, the material of the gate structure 120 is likely to remain in the opening 150, which is likely to reduce the isolation effect of the isolation layer 160 formed in the opening 150, and even cause leakage current, so that the performance of the semiconductor structure is poor.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a dielectric layer on the isolation structure, wherein the dielectric layer exposes the top surface of the grid structure; forming a first opening in the dielectric layer, wherein the side wall of the first opening is exposed out of the grid structure, and the surface of the isolation structure is exposed out of the first opening; after the first opening is formed, removing the gate structure exposed from the side wall of the first opening, and forming a second opening in the gate structure, wherein the second opening exposes the surface of the isolation structure, and is adjacent to and communicated with the first opening in a second direction, and the second direction is perpendicular to the first direction; and forming an isolation layer in the first opening and the second opening. The method has the advantages of larger process window, shorter process period and better performance of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 6 to 20 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 6 to 8, fig. 6 is a top view perpendicular to a substrate plane direction, fig. 7 is a schematic cross-sectional view taken along a tangential direction of B-B1 in fig. 6, fig. 8 is a schematic cross-sectional view taken along a tangential direction of a-a1 in fig. 6, a substrate 200 is provided, the substrate 200 has a gate structure 210 and an isolation structure 220 thereon, the gate structure 210 extends along a first direction X, and the gate structure 210 is located on the isolation structure 220.
In this embodiment, the base 200 includes a substrate 201 and a fin 202 located on a surface of the substrate 201, and the gate structure 210 spans a portion of a top surface and a sidewall surface of the fin 202.
In the present embodiment, the fin 202 is formed by etching the substrate 201.
In another embodiment, the method of forming the substrate includes: forming a fin material film on the substrate; forming a patterned layer on the surface of the fin material film; and etching the fin part material layer by taking the patterning layer as a mask until the surface of the substrate is exposed to form a fin part.
In other embodiments, the fin is a planar substrate, and the gate structure is formed on the planar substrate surface.
In this embodiment, the substrate 200 is made of silicon; in other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide; in other embodiments, the base may also be a silicon-on-insulator Substrate (SOI) or a germanium-on-insulator substrate (GOI).
In this embodiment, the gate structure 210 includes: the gate electrode layer 212 is located on the surface of the gate dielectric layer 211 and the surface of the side wall of the fin portion 202.
In this embodiment, the gate dielectric layer 211 is made of a high-K dielectric material, and the high-K dielectric material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide. In other embodiments, the material of the gate dielectric layer is silicon oxide.
In this embodiment, the material of the gate electrode layer 212 is a metal, and the metal material includes one or more of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride. In other embodiments, the material of the gate electrode layer is polysilicon.
In the present embodiment, the sidewall surface of the gate structure 210 has a sidewall structure 215.
The material of the sidewall structure 215 is an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.
In this embodiment, the material of the sidewall structure 215 is silicon nitride.
Note that the a-a1 tangent is located between adjacent fins 202.
With continued reference to fig. 6 to 8, a dielectric layer 230 is formed on the isolation structure 220, wherein the dielectric layer 230 exposes the top surface of the gate structure 210.
The dielectric layer 230 is an interlayer dielectric (ILD) used to provide support for the subsequent formation of the first opening.
In this embodiment, the top surface of the dielectric layer 230 is flush with the top surface of the gate structure 210.
The method for forming the dielectric layer 230 comprises the following steps: forming a dielectric material film (not shown) on the isolation structure 220 to cover the gate structure 210; the dielectric material film is planarized until the top surface of the gate structure 210 is exposed, and the dielectric layer 230 is formed on the isolation structure 220.
The material of the dielectric layer 230 is different from that of the sidewall structure 215.
The dielectric layer 230 is made of an insulating material, and the insulating material includes: silicon oxide, silicon nitride, silicon oxynitride, or titanium dioxide.
In this embodiment, the material of the dielectric layer 230 is silicon oxide.
Specifically, in this embodiment, the dielectric material film also covers the top surface and the sidewall surface of the fin 202.
Next, a first opening is formed in the dielectric layer 230, a sidewall of the first opening exposes the gate structure 210, and a bottom of the first opening exposes the surface of the isolation structure 220, and refer to fig. 9 to 14 for a process of forming the first opening.
Referring to fig. 9 to 11, fig. 9 is a schematic view based on fig. 6, fig. 10 is a schematic view based on fig. 7, and fig. 11 is a schematic view based on fig. 8, wherein a masking layer 235 is formed on the surfaces of the gate structure 210 and the dielectric layer 230, and the masking layer 235 exposes a portion of the surface of the dielectric layer 230, the surface of the gate structure 210, and the surface of the sidewall spacer structure 215; and etching the dielectric layer 230 by using the mask layer 235 as a mask until the surface of the isolation structure 220 is exposed, forming an initial first opening 231 in the dielectric layer 230, and exposing the sidewall structure 215 on the surface of the sidewall of the gate structure 210 by using the initial first opening 231.
The process for etching the dielectric layer 230 includes: one or two of the dry etching process and the wet etching process are combined.
In this embodiment, the process of etching the dielectric layer 230 is a dry etching process.
The dielectric layer 230 is easily etched by using the dry etching process, so that the process difficulty for forming the initial first opening 231 is low. The dry etching process parameters comprise: the etching gas used includes: a gas containing a fluorocarbon or a hydrofluorocarbon.
The bottom of the initial first opening 231 exposes the surface of the isolation structure 220.
In this embodiment, the method for forming the initial first opening 231 further includes: after the dielectric layer 230 is etched to expose the isolation structure 220 at the bottom of the dielectric layer 230, a portion of the isolation structure 220 is over-etched.
By over-etching part of the isolation structure 220, the sidewall surface of the sidewall structure 215 is favorably exposed sufficiently, so that the sidewall structure 215 on the sidewall surface of the gate structure 210 can be subsequently removed sufficiently, and the sidewall surface of the gate structure 210 is favorably exposed sufficiently.
Referring to fig. 12 to 14, fig. 12 is a schematic view based on fig. 9, fig. 13 is a schematic view based on fig. 10, and fig. 14 is a schematic view based on fig. 11, in which the sidewall structures 215 exposed by the initial first openings 231 are removed, first openings 240 are formed in the dielectric layer 230, and the surfaces of the gate structures 210 are exposed by the first openings 240.
The first opening 240 is used to provide a space for forming an isolation layer together with a subsequently formed second opening.
In this embodiment, the method for forming the first opening 240 further includes: after the sidewall structure 215 is etched to expose the isolation structure 220, a portion of the isolation structure 220 is over-etched, and the first opening 240 is formed in the dielectric layer 230.
By etching part of the isolation structure 220, it is favorable to ensure that the sidewall surface of the gate structure 210 can be fully exposed, so that the difficulty of forming the second opening by subsequently etching the gate structure 210 is favorably reduced, and the performance of the formed semiconductor structure is favorably improved.
It should be noted that, in this embodiment, the gate structure 210 includes a gate dielectric layer 211 and a gate electrode layer 212 located on the surface of the gate dielectric layer 211, the sidewall spacer structure 215 is located on the surface of the sidewall of a portion of the gate dielectric layer 211, and after removing the sidewall spacer structure 215, a portion of the gate dielectric layer 211 in the gate structure 210 is exposed, so that the method for forming the first opening 240 further includes: after removing the sidewall spacer structure 215, the exposed portion of the gate dielectric layer 211 is removed.
In the present embodiment, the sidewall of the first opening 240 exposes the sidewall surface of the gate electrode layer 212 in the gate structure 210.
Referring to fig. 15 to 17, fig. 15 is a schematic view based on fig. 12, fig. 16 is a schematic view based on fig. 13, and fig. 17 is a schematic view based on fig. 14, after the first opening 240 is formed, the gate structure 210 exposed by the sidewall of the first opening 240 is removed, a second opening 250 is formed in the gate structure 210, the second opening 250 exposes the surface of the isolation structure 220, and the second opening 250 is adjacent to and communicates with the first opening 240 in a second direction Y, which is perpendicular to the first direction X.
The second opening 250 is used to provide a space for the subsequent formation of the isolation layer together with the first opening 240.
The method for forming the second opening 250 includes: after the first opening 240 is formed, the gate structure 210 is etched by using the mask layer 235 as a mask until the surface of the isolation structure 220 is exposed, and the second opening 250 is formed in the gate structure 210, wherein the second opening 250 is adjacent to and communicated with the first opening 240.
Specifically, in this embodiment, the gate electrode layer 212 and the gate dielectric layer 211 located at the bottom of the gate electrode layer 212 are etched.
The method for forming the second opening 250 further includes: after the gate structure 210 is etched to expose the isolation structure 220, a portion of the isolation structure 220 is over-etched, and the second opening 250 is formed in the gate structure 210.
By etching a portion of the isolation structure 220, the gate structure 210 exposed by the mask layer is ensured to be sufficiently removed, and the generation of leakage current caused by the byproduct generated by etching the gate structure 210 remaining in the second opening 250 is avoided.
By first forming a first opening 240 in the dielectric layer 230, the sidewall of the first opening 240 exposes the gate structure 210; after the first opening 240 is formed, the gate structure 210 exposed by the first opening 240 is etched, so as to form a second opening 250 in the gate structure 210. Due to the low difficulty of the process for etching the material of the dielectric layer 230, the first opening is easily formed in the dielectric layer 230, and the first opening 240 is formed in a good shape. After the first opening 240 is formed, since the sidewall of the first opening 240 exposes the surface of the gate structure, the exposed area of the surface of the gate structure 240 is increased, which is beneficial to the subsequent process of etching the material of the gate structure 240, so that the process difficulty of forming the second opening 250 penetrating through the gate structure 210 in the gate structure is reduced, and the appearance of the formed second opening 250 is better, thereby being beneficial to improving the performance of the formed semiconductor structure.
Referring to fig. 18 to 20, an isolation layer 260 is formed in the first opening 240 and the second opening 250.
The isolation layer 260 is located in the first opening 240 and the second opening 250, and the second opening 250 penetrates through the gate structure 210 along the second direction Y, so that the isolation layer 260 can isolate the gate structure 210 along the second direction Y.
The method for forming the isolation layer 260 includes: after the first opening 240 and the second opening 250 are formed, an isolation material film (not shown) is formed on the surfaces of the first opening 240, the second opening 250, the gate structure 210 and the dielectric layer 230; the isolation material film is planarized until the surfaces of the gate structure 210 and the dielectric layer 230 are exposed, and the isolation layer 260 is formed in the first opening 240 and the second opening 250.
After the first opening 240 and the second opening 250 are formed, an isolation material film is filled in the first opening 240 and the second opening 250, so that an isolation layer 260 is formed in the first opening 240 and the second opening 250. Since the first opening 240 and the second opening 250 are adjacent to and communicated with each other along the second direction Y, that is, the size of the first opening 240 and the second opening 250 along the second direction Y is larger than that of the second opening 250, the difficulty of filling an isolation material film in the first opening 240 and the second opening 250 is reduced, thereby facilitating the formation of the isolation layer 260 and saving the process time and cost.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 18 to 20, including: the semiconductor device comprises a substrate 200, wherein a gate structure 210 and an isolation structure 220 are arranged on the substrate 200, the gate structure 210 extends along a first direction X, and the gate structure 210 is located on the surface of the isolation structure 220; a dielectric layer 230 on the isolation structure 220, wherein the dielectric layer 230 exposes the top surface of the gate structure 210; a first opening 240 in the dielectric layer 230, wherein the first opening 240 exposes a sidewall surface of the gate structure 210, and the first opening 210 exposes a surface of the isolation structure 220; a second opening 250 in the gate structure 210, wherein the second opening 250 exposes the surface of the isolation structure, and the second opening 250 is adjacent to and communicated with the first opening 240 in a second direction Y, which is perpendicular to the first direction X; an isolation layer 260 within the first opening 240 and the second opening 250.
The first opening 240 is also located within a portion of the isolation structure 220.
The second opening 250 is also located in a portion of the isolation structure 220.
The substrate 200 includes a substrate 201 and a fin 202 located on a surface of the substrate 201, and the gate structure 210 spans a portion of a top surface and a sidewall surface of the fin 202.
In other embodiments, the fin includes a plurality of fin layers arranged along a normal of the substrate surface, a groove is formed between adjacent fin layers, and the gate structure is further located in the groove.
The first openings 240 are located between adjacent fins 202, and the second openings 250 are located between adjacent fins 202.
The material of the isolation layer 260 includes: an insulating material.
The insulating material includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the isolation layer 260 is silicon oxide.
The top surface of the dielectric layer 230 is flush with the top surface of the gate structure 210, and the top surface of the isolation layer 260 is flush with the top surface of the dielectric layer 230.
The sidewall surface of the gate structure 210 has a sidewall structure 215; the material of the sidewall structure 215 includes: an insulating material.
The insulating material includes: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
In this embodiment, the material of the sidewall structure 215 is silicon nitride.
The gate structure 210 includes: a gate dielectric layer 211 on the surface of the substrate 200 and a gate electrode layer 212 on the surface of the gate dielectric layer 211.
In this embodiment, the gate dielectric layer 211 is located on a portion of the top surface and the sidewall surface of the fin 202.
The gate dielectric layer 211 comprises: silicon oxide or a high K dielectric material. In this embodiment, the gate dielectric layer 211 is made of a high-K dielectric material.
The high-K dielectric material comprises: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide.
In other embodiments, the material of the gate dielectric layer is silicon oxide.
The material of the gate electrode layer 212 includes: polysilicon or metal. In this embodiment, the material of the gate electrode layer 212 is metal. The metal material includes: one or more combinations of copper, tungsten, aluminum, titanium, nickel, titanium nitride, and tantalum nitride.
In other embodiments, the material of the gate electrode layer is polysilicon.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (17)

1. A semiconductor structure, comprising:
the semiconductor device comprises a substrate, a grid structure and an isolation structure, wherein the grid structure extends along a first direction and is positioned on the surface of the isolation structure;
the dielectric layer is positioned on the isolation structure and exposes the top surface of the grid structure;
the first opening is positioned in the dielectric layer, the surface of the side wall of the grid structure is exposed out of the first opening, and the surface of the isolation structure is exposed out of the first opening;
a second opening in the gate structure, the second opening exposing the surface of the isolation structure, the second opening being adjacent to and in communication with the first opening in a second direction, the second direction being perpendicular to the first direction;
an isolation layer within the first opening and the second opening.
2. The semiconductor structure of claim 1, wherein the first opening is also located within a portion of an isolation structure.
3. The semiconductor structure of claim 1, wherein the second opening is also located within a portion of the isolation structure.
4. The semiconductor structure of claim 1, wherein the base comprises a substrate and a fin on a surface of the substrate, the gate structure spanning a portion of a top surface and a sidewall surface of the fin.
5. The semiconductor structure of claim 4, wherein the fin comprises a plurality of fin layers arranged along a normal to a surface of the substrate, wherein a recess is formed between adjacent fin layers, and wherein the gate structure is further located in the recess.
6. The semiconductor structure of claim 4, wherein the first opening is located between adjacent fins and the second opening is located between adjacent fins.
7. The semiconductor structure of claim 1, wherein a material of the isolation layer comprises: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
8. The semiconductor structure of claim 1, wherein a top surface of the dielectric layer is flush with a top surface of the gate structure, and wherein a top surface of the isolation layer is flush with the top surface of the dielectric layer.
9. The semiconductor structure of claim 1, wherein a sidewall structure is formed on a sidewall surface of the gate structure; the side wall structure is made of materials including: silicon oxide, silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.
10. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a gate structure and an isolation structure, the gate structure extends along a first direction, and the gate structure is positioned on the isolation structure;
forming a dielectric layer on the isolation structure, wherein the dielectric layer exposes the top surface of the grid structure;
forming a first opening in the dielectric layer, wherein the side wall of the first opening is exposed out of the grid structure, and the surface of the isolation structure is exposed out of the first opening;
after the first opening is formed, removing the gate structure exposed from the side wall of the first opening, and forming a second opening in the gate structure, wherein the second opening exposes the surface of the isolation structure, and is adjacent to and communicated with the first opening in a second direction, and the second direction is perpendicular to the first direction;
and forming an isolation layer in the first opening and the second opening.
11. The method of claim 10, wherein a top surface of the dielectric layer is flush with a top surface of the gate structure; the side wall surface of the grid structure is provided with a side wall structure.
12. The method of forming a semiconductor structure of claim 11, wherein the method of forming the first opening comprises: forming a mask layer on the gate structure and the surface of the dielectric layer, wherein the mask layer exposes part of the surface of the dielectric layer, the gate structure and the surface of the side wall structure; etching the dielectric layer by taking the mask layer as a mask until the surface of the isolation structure is exposed, forming an initial first opening in the dielectric layer, and exposing the side wall structure on the surface of the side wall of the grid structure by the initial first opening; and removing the exposed side wall structure of the initial first opening, forming a first opening in the dielectric layer, and exposing the surface of the grid structure by the first opening.
13. The method of forming a semiconductor structure of claim 12, wherein the method of forming the first opening further comprises: etching the dielectric layer, and after exposing the isolation structure, over-etching part of the isolation structure; and etching the side wall structure, and after exposing the isolation structure, over-etching part of the isolation structure to form the first opening in the dielectric layer.
14. The method of forming a semiconductor structure according to claim 12, wherein the method of forming the second opening comprises: and after the first opening is formed, etching the gate structure by taking the mask layer as a mask until the surface of the isolation structure is exposed, and forming a second opening in the gate structure, wherein the second opening is adjacent to and communicated with the first opening.
15. The method of forming a semiconductor structure of claim 14, wherein the method of forming the second opening further comprises: and after the grid structure is etched and the isolation structure is exposed, over-etching part of the isolation structure to form the second opening in the grid structure.
16. The method of forming a semiconductor structure of claim 11, wherein the method of forming a dielectric layer comprises: forming a dielectric material film covering the gate structure on the isolation structure; and flattening the dielectric material film until the top surface of the grid structure is exposed, and forming the dielectric layer on the isolation structure.
17. The method of forming a semiconductor structure of claim 11, wherein the method of forming the isolation layer comprises: after the first opening and the second opening are formed, an isolation material film is formed on the surfaces of the first opening, the second opening, the grid structure and the dielectric layer; and flattening the isolating material film until the grid structure and the surface of the dielectric layer are exposed, and forming the isolating layer in the first opening and the second opening.
CN202010192561.1A 2020-03-18 2020-03-18 Semiconductor structure and forming method thereof Pending CN113497139A (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216354A (en) * 2017-06-29 2019-01-15 台湾积体电路制造股份有限公司 Metal gate structure cutting technique
CN109860115A (en) * 2017-11-30 2019-06-07 台湾积体电路制造股份有限公司 The cutting method of IC apparatus structure
CN110600471A (en) * 2018-06-12 2019-12-20 三星电子株式会社 Semiconductor device having gate isolation layer and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109216354A (en) * 2017-06-29 2019-01-15 台湾积体电路制造股份有限公司 Metal gate structure cutting technique
CN109860115A (en) * 2017-11-30 2019-06-07 台湾积体电路制造股份有限公司 The cutting method of IC apparatus structure
CN110600471A (en) * 2018-06-12 2019-12-20 三星电子株式会社 Semiconductor device having gate isolation layer and method of manufacturing the same

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