CN113363164A - Square chip packaging method and packaging structure thereof - Google Patents

Square chip packaging method and packaging structure thereof Download PDF

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Publication number
CN113363164A
CN113363164A CN202110727870.9A CN202110727870A CN113363164A CN 113363164 A CN113363164 A CN 113363164A CN 202110727870 A CN202110727870 A CN 202110727870A CN 113363164 A CN113363164 A CN 113363164A
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China
Prior art keywords
chip
square
packaging
hard board
layer
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CN202110727870.9A
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Chinese (zh)
Inventor
杨斌
李潮
崔成强
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Guangdong Xinhua Microelectronics Technology Co ltd
Guangdong Fozhixin Microelectronics Technology Research Co ltd
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Priority to CN202110727870.9A priority Critical patent/CN113363164A/en
Publication of CN113363164A publication Critical patent/CN113363164A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The application provides a square chip packaging method and a packaging structure thereof, wherein the square chip packaging method comprises the following steps: a1, manufacturing a folding substrate with a circuit layer, wherein the folding substrate comprises six hard board areas which can be folded into a square body and a soft board area arranged between two adjacent hard board areas; a2, arranging a chip module or a heat dissipation device on each hard board area, arranging a chip module on at least one hard board area, and electrically connecting the chip module with the circuit layer to obtain a square chip expansion structure; a3, folding the square chip unfolding structure, and bonding the multiple chip modules or the chip modules and the heat dissipation device through the colloid, thereby obtaining the square chip packaging structure. This application is through unfolding the structure with the square body chip and folding, can directly obtain square body chip packaging structure, can be integrated with a plurality of chip module encapsulation, and the integrated level is high, and process flow is simple, and the cost of manufacture is low.

Description

Square chip packaging method and packaging structure thereof
Technical Field
The application relates to the field of chip packaging, in particular to a square chip packaging method and a packaging structure thereof.
Background
Modern electronic information technology is rapidly developed, and electronic products are gradually developed in the directions of miniaturization, portability and multi-functionalization. As electronic products are miniaturized, their package structures are also high-density, high-precision, fine-pitch, highly reliable, multi-layered, and high-speed transmission.
At present, because two-dimensional plane integration technique pastes dress with the biggest face direction with all components and parts, wherein, has some great components and parts of volume and can occupy packaging structure's most area and space for packaging structure's components and parts are pasted dress quantity and are limited, and the integration level is low, and between a plurality of components and parts and the encapsulation circuit the key with need certain span, increased wiring length, also can influence the transmission of signal. Therefore, with the development of the three-dimensional integration technology, two or more components are stacked and packaged by using a multi-chip stacking and packaging process, and circuit interconnection is formed among the components, so that the packaging space can be effectively utilized, higher integration level is realized, the components are directly interconnected, the length of an interconnection line is obviously shortened, the signal transmission is faster, and the interference is less. However, in the current three-dimensional integration technology, a plurality of components need to be stacked and packaged layer by layer, and then interconnection between the components is realized by using TSV (Through Silicon Via), TMV (Through Molding Via) and TGV (Through glass Via).
Therefore, there is a great need for improvement in the art.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method for packaging a square chip and a packaging structure thereof, which can solve the problem of complicated multi-chip packaging process, greatly improve packaging efficiency, and reduce cost.
The embodiment of the application provides a method for packaging a square chip, which comprises the following steps:
a1, manufacturing a folded substrate with a circuit layer, wherein the folded substrate comprises six hard board areas capable of being folded into a square body and a soft board area arranged between two adjacent hard board areas;
a2, arranging a chip module or a heat dissipation device on each hard board area, arranging the chip module on at least one hard board area, and electrically connecting the chip module with the circuit layer to obtain a square chip expansion structure;
a3, folding the square chip unfolding structure, and bonding the chip modules or the chip modules and the heat dissipation device through glue to obtain the square chip packaging structure.
Preferably, in the method for packaging a square chip in the embodiment of the present application, in the step a1, the method includes the following steps:
a11, providing a carrier plate to form a first polyimide film layer;
a12, arranging a circuit layer on the first polyimide film layer;
a13, arranging a second polyimide film layer on the circuit layer, and thus obtaining the flexible circuit board;
a14, dividing the flexible circuit board into a plurality of folding substrates, wherein each folding substrate comprises six hard board areas which can be folded into a square body and a soft board area arranged between two adjacent hard board areas.
Preferably, in the method for packaging a square chip in the embodiment of the present application, in the step a2, the method includes the following steps:
a21, opening the second polyimide film layer on at least one hard board area in each folded substrate to form hole sites, wherein the hole sites are used for exposing the pad areas of the circuit layer;
a22, arranging a chip module or a heat dissipation device on the second polyimide film layer, arranging the chip module on at least one hard board area in each folded substrate, and electrically connecting the chip module with the bonding pad area of the circuit layer;
a23, removing the carrier board, and cutting the flexible circuit board to obtain a plurality of square chip unfolding structures, wherein each square chip unfolding structure comprises only one folded substrate.
Preferably, in the method for packaging a square chip in the embodiment of the present application, in the step a12, the method includes the following steps:
a121, providing a photosensitive dry film or photosensitive ink, and covering the photosensitive dry film or the photosensitive ink on the first polyimide film layer;
a122, exposing and developing the photosensitive dry film or the photosensitive ink to form a first patterned through hole;
a123, electroplating and depositing copper in the first patterned through hole to form a preset circuit;
and A124, removing the film from the photosensitive dry film or the photosensitive ink, and covering a dielectric material layer on the first polyimide film layer to obtain the circuit layer.
Preferably, in the method for packaging a square chip in the embodiment of the present application, in the step a12, the method includes the following steps:
a121, providing a copper foil, and pressing the copper foil on the first polyimide film layer;
a122, etching the copper foil to form a preset circuit and form a second patterned through hole;
and A123, arranging a dielectric material layer in the second patterned through hole to obtain a circuit layer.
Preferably, in the method for packaging a square chip in an embodiment of the present application, the flexible board region includes a plurality of leads.
Preferably, the method for packaging a square chip in an embodiment of the present application further includes the following steps:
and partially cutting the flexible board area to ensure that two adjacent leads in the flexible board area are hollowed out.
Preferably, in the method for packaging a square chip in an embodiment of the present application, the leads are arc leads.
Preferably, in the method for packaging a square chip in an embodiment of the present application, in the step a3, the colloid is one of silver colloid, copper colloid, silica gel, or silica gel doped with graphene.
The embodiment of the application also provides a square chip packaging structure, which comprises a folding substrate with a circuit layer, wherein the folding substrate comprises six hard board areas folded into a square body and a soft board area arranged between two adjacent hard board areas; each hard board area is provided with a chip module or a heat dissipation device, at least one hard board area is provided with the chip module, and the chip module is electrically connected with the circuit layer; and the plurality of chip modules or the chip modules and the heat dissipation device are bonded through glue.
Has the advantages that: the square chip packaging method provided by the embodiment of the application comprises the steps of manufacturing a plurality of folding substrates with circuit layers in advance, wherein each folding substrate comprises six hard board areas capable of being folded into a square body and a soft board area arranged between two adjacent hard board areas, then arranging a chip module or a heat dissipation device on each hard board area, obtaining a square chip unfolding structure, folding the square chip unfolding structure, and directly obtaining the square chip packaging structure.
Drawings
Fig. 1 is a flowchart of a method for packaging a square chip according to an embodiment of the present disclosure.
Fig. 2 is a detailed schematic diagram of each step of a method for packaging a square chip according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a folded substrate in a method for packaging a square chip according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it is to be noted that the terms "front side", "back side", and the like refer to orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships that are conventionally laid out when products of the application are used, and are only used for convenience in describing the application and simplifying the description, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the application.
It should also be noted that, unless expressly stated or limited otherwise, the terms "disposed" and "connected" are to be construed broadly, e.g., as meaning fixedly connected, detachably connected, or integrally connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic flow chart of a method for packaging a square bulk chip according to some embodiments of the present application, and fig. 2 is a detailed schematic diagram of each step of the method for packaging a square bulk chip according to the embodiments of the present application. The method for packaging the square chip comprises the following steps:
a1, manufacturing a folded substrate 100 with a circuit layer 10, wherein the folded substrate 100 comprises six hard board areas 11 capable of being folded into a square body and a soft board area 12 arranged between two adjacent hard board areas 11;
a2, arranging a chip module 20 or a heat dissipation device 30 on each hard board area 11, arranging a chip module 20 on at least one hard board area 11, and electrically connecting the chip module 20 with the circuit layer 10 to obtain a square chip expansion structure;
and A3, folding the square chip unfolding structure, and bonding the chip modules 20 or the chip modules 20 and the heat dissipation device 30 through glue to obtain the square chip packaging structure.
It should be noted that, in practical applications, a plurality of square chip package structures can be manufactured at one time in a large board level package manner, so as to improve the production efficiency. Specifically, in the large board level package manner, step a1 includes the following steps:
a11, providing a carrier plate to form a first polyimide film layer 50;
a12, arranging a circuit layer 10 on the first polyimide film layer 50;
a13, arranging a second polyimide film layer 40 on the circuit layer 10, thereby obtaining a flexible circuit board;
and A14, dividing the flexible printed circuit board into a plurality of folding substrates 100, wherein each folding substrate 100 comprises six hard board areas 11 capable of being folded into a square body and a soft board area 12 arranged between two adjacent hard board areas 11.
Specifically, please refer to fig. 3 at the same time, fig. 3 is a schematic structural diagram of a folded substrate in a method for packaging a quad chip according to an embodiment of the present disclosure. In fig. 3, the circuit layer 10 is provided with a pad region for electrically connecting with the chip module 20. In order to electrically connect the die set 20 and the pad region of the circuit layer 10, in step a2, the method specifically includes the following steps:
a21, performing hole opening treatment on the second polyimide film layer 40 on at least one hard board region 11 in each folded substrate 100 to form hole positions, wherein the hole positions are used for exposing the pad region of the circuit layer 10;
a22, disposing a die module 20 or a heat spreader 30 on the second polyimide film 40, and disposing the die module 20 on at least one hard board region 11 of each of the folded substrates 100, and electrically connecting the die module 20 and the pad region of the circuit layer 10;
a23, removing the carrier board, and cutting the flexible circuit board to obtain a plurality of square chip unfolding structures, wherein each square chip unfolding structure comprises only one folded substrate 100.
In step a22, a conductive copper pillar may be formed by electroplating to deposit copper, and the conductive copper pillar is used to lead out the pad of the circuit layer 10 and electrically connect with the electrical signal connection bump of the chip module 20. In addition, the conductive copper pillar may also be connected to the heat dissipation assembly 30 for rapidly transferring the heat of the package structure to the heat dissipation assembly 30 and then rapidly dissipating the heat from the heat dissipation assembly 30.
It should be further noted that the carrier may be one of a glass carrier, an organic carrier, a stainless steel carrier, an alloy carrier, a glass carrier, an FR2 carrier, an FR4 carrier, an FR5 carrier, or a BT carrier. The first polyimide film layer 50 may be bonded to the carrier through a temporary bonding adhesive layer, and the carrier may be removed in step a23 by thermal disassembly, mechanical disassembly, or laser disassembly.
In practical applications, the chip module 20 may be a system-level package structure pre-packaged by the packaging layer 60, or may be a single chip. The material of the encapsulation layer 60 is one of epoxy resin, silica gel, or polyimide. The chip module 20 may be attached to the folding substrate 100, and then the chip module 20 is locally packaged by the packaging layer 60, that is, only the rigid board region 11 is plastically packaged, but the flexible board region 12 is not plastically packaged, so that the flexible board region 12 can be bent, and further, each square chip unfolding structure can be folded. In practical applications, the polyimide film may be laminated on the chip module 20 to plastically package the chip module 20, so as to prevent the flowing packaging material from flowing to the flexible board region 12 and affecting the bending performance of the flexible board region 12. In addition, the bottom surface of the hard board region 11 provided with the chip module 20 can be drilled for copper deposition, and a soldering layer and solder balls are provided to electrically lead out the chip module 20.
The heat dissipation device 30 may be formed by only multiple layers of heat conductive interface material layers, and preferably, the heat dissipation device 30 may be formed by sequentially stacking the heat conductive interface material layers and the heat sink (the heat conductive interface material layers and the heat sink are sequentially disposed according to specific situations, so that the heat conductive interface material layers need to be connected to the chip module 20 after the folded structure of each square chip is folded). The thermal interface material layer is used for conducting heat generated by the chip module 20 to the heat sink, and then dissipating heat generated by the chip module 20 through the heat sink.
Specifically, in practical application, the heat-conducting interface material layer may be one of heat-conducting silicone grease, a heat-conducting silicone sheet, a heat-conducting phase-change material, or a heat-conducting double-sided adhesive tape, and the heat sink is one or a combination of two or more of a metal plate, a graphite film, a graphene film, a heat pipe, or a vapor chamber containing heat dissipation fins. For example, a heat pipe or a vapor chamber may be disposed on the heat conducting interface material layer, and a graphite film or a graphene film may be disposed on the heat pipe or the vapor chamber, so that the heat generated by the chip module 20 is first transferred to the heat pipe or the vapor chamber through the heat conducting interface material layer, then transferred to the graphite film or the graphene film, and then transferred into the air directly or through a metal plate having heat dissipation fins, thereby forming an efficient heat dissipation system.
Preferably, in the method for packaging a square chip in the embodiment of the present application, the forming manner of the circuit layer 10 may be various, and the following embodiment specifically describes the forming manner.
Example 1
In example 1, step a12 specifically includes the following steps:
a121, providing a photosensitive dry film or photosensitive ink, and covering the photosensitive dry film or the photosensitive ink on the first polyimide film layer 50;
a122, exposing and developing the photosensitive dry film or the photosensitive ink to form a first patterning through hole;
a123, electroplating and depositing copper in the first patterned through hole to form a preset circuit;
and A124, removing the photosensitive dry film or the photosensitive ink, and covering a dielectric material layer on the first polyimide film layer to obtain the circuit layer 10.
Example 2
In embodiment 2, step a12 specifically includes the following steps:
a121, providing a copper foil, and pressing the copper foil on the first polyimide film layer 50;
a122, etching the copper foil to form a preset circuit and form a second patterned through hole;
and A123, arranging a dielectric material layer in the second patterned through hole to obtain the circuit layer 10.
Both of the above manners can provide the wiring layer 10 on the first polyimide film layer 50, but it is preferable that the manner in example 1 is less harmful to the first polyimide film layer 50. In practical applications, the material of the dielectric material layer may be one of ABF, liquid crystal polymer, polyimide, and high polymer polypropylene.
Further, in the method for packaging a square chip in the embodiment of the present application, the flexible board region 12 includes a plurality of leads, and the thickness ranges of the first polyimide film layer 50 and the second polyimide film layer 40 are both 10 to 2000 microns.
In practical application, the method for packaging a square chip in the embodiment of the present application further includes the following steps:
the flexible board area 12 is partially cut, so that two adjacent leads in the flexible board area 12 are hollowed out.
In addition, in the method for packaging a square chip of the embodiment of the present application, the leads are arc leads to increase the bending performance of the flexible board region 12.
Preferably, in the method for packaging a square chip in the embodiment of the present application, in step a3, the colloid is one of silver colloid, copper colloid, silica gel, or silica gel doped with graphene. And further, the thermal expansion coefficient of the gel may be set to be greater than that of the encapsulation layer 60.
Further, the embodiment of the present application further provides a square chip package structure, including a folded substrate 100 having a circuit layer 10, where the folded substrate 100 includes six hard board regions 11 folded into a square and a soft board region 12 disposed between two adjacent hard board regions 11; each hard board area 11 is provided with a chip module 20 or a heat dissipation device 30, at least one hard board area 11 is provided with the chip module 20, and the chip module 20 is electrically connected with the circuit layer 10; the plurality of chip modules 20 or the chip module 20 and the heat dissipation device 30 are bonded by an adhesive.
The square chip packaging method and the packaging structure thereof provided by the embodiment of the application are characterized in that a plurality of folding substrates with circuit layers are manufactured in advance, each folding substrate comprises six hard board areas capable of being folded into a square body and a soft board area arranged between every two adjacent hard board areas, then a chip module or a heat dissipation device is arranged on each hard board area, a square chip unfolding structure can be obtained, the square chip unfolding structure is folded, the square chip packaging structure can be directly obtained, a plurality of chip modules can be packaged and integrated, the integration level is high, the process flow is simple, and the manufacturing cost is low.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method for packaging a cube chip is characterized by comprising the following steps:
a1, manufacturing a folded substrate with a circuit layer, wherein the folded substrate comprises six hard board areas capable of being folded into a square body and a soft board area arranged between two adjacent hard board areas;
a2, arranging a chip module or a heat dissipation device on each hard board area, arranging the chip module on at least one hard board area, and electrically connecting the chip module with the circuit layer to obtain a square chip expansion structure;
a3, folding the square chip unfolding structure, and bonding the chip modules or the chip modules and the heat dissipation device through glue to obtain the square chip packaging structure.
2. The method for packaging a square chip as claimed in claim 1, wherein the step a1 comprises the following steps:
a11, providing a carrier plate to form a first polyimide film layer;
a12, arranging a circuit layer on the first polyimide film layer;
a13, arranging a second polyimide film layer on the circuit layer, and thus obtaining the flexible circuit board;
a14, dividing the flexible circuit board into a plurality of folding substrates, wherein each folding substrate comprises six hard board areas which can be folded into a square body and a soft board area arranged between two adjacent hard board areas.
3. The method for packaging a square chip according to claim 2, wherein the step a2 comprises the following steps:
a21, opening the second polyimide film layer on at least one hard board area in each folded substrate to form hole sites, wherein the hole sites are used for exposing the pad areas of the circuit layer;
a22, arranging a chip module or a heat dissipation device on the second polyimide film layer, arranging the chip module on at least one hard board area in each folded substrate, and electrically connecting the chip module with the bonding pad area of the circuit layer;
a23, removing the carrier board, and cutting the flexible circuit board to obtain a plurality of square chip unfolding structures, wherein each square chip unfolding structure comprises only one folded substrate.
4. The method for packaging a square chip according to claim 2, wherein the step a12 comprises the following steps:
a121, providing a photosensitive dry film or photosensitive ink, and covering the photosensitive dry film or the photosensitive ink on the first polyimide film layer;
a122, exposing and developing the photosensitive dry film or the photosensitive ink to form a first patterned through hole;
a123, electroplating and depositing copper in the first patterned through hole to form a preset circuit;
and A124, removing the film from the photosensitive dry film or the photosensitive ink, and covering a dielectric material layer on the first polyimide film layer to obtain the circuit layer.
5. The method for packaging a square chip according to claim 2, wherein the step a12 comprises the following steps:
a121, providing a copper foil, and pressing the copper foil on the first polyimide film layer;
a122, etching the copper foil to form a preset circuit and form a second patterned through hole;
and A123, arranging a dielectric material layer in the second patterned through hole to obtain a circuit layer.
6. The method of claim 1, wherein the board area comprises a plurality of leads.
7. The method of packaging a quad chip as claimed in claim 6, further comprising the steps of:
and partially cutting the flexible board area to ensure that two adjacent leads in the flexible board area are hollowed out.
8. The method of claim 7, wherein the leads are arcuate leads.
9. The method of claim 1, wherein in the step A3, the colloid is one of silver colloid, copper colloid, silica gel, or silica gel doped with graphene.
10. The square chip packaging structure is characterized by comprising a folding substrate with a circuit layer, wherein the folding substrate comprises six hard board areas folded into a square body and a soft board area arranged between two adjacent hard board areas; each hard board area is provided with a chip module or a heat dissipation device, at least one hard board area is provided with the chip module, and the chip module is electrically connected with the circuit layer; and the plurality of chip modules or the chip modules and the heat dissipation device are bonded through glue.
CN202110727870.9A 2021-06-29 2021-06-29 Square chip packaging method and packaging structure thereof Withdrawn CN113363164A (en)

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Inventor after: Yang Bin

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Inventor before: Cui Chengqiang

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Application publication date: 20210907