CN113299605B - Display panel and preparation method thereof - Google Patents
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- CN113299605B CN113299605B CN202110501650.4A CN202110501650A CN113299605B CN 113299605 B CN113299605 B CN 113299605B CN 202110501650 A CN202110501650 A CN 202110501650A CN 113299605 B CN113299605 B CN 113299605B
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- 238000002360 preparation method Methods 0.000 title abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 134
- 239000000463 material Substances 0.000 claims description 20
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 238000009826 distribution Methods 0.000 abstract description 14
- 230000000694 effects Effects 0.000 abstract description 6
- 238000002161 passivation Methods 0.000 description 16
- 230000000149 penetrating effect Effects 0.000 description 8
- 239000010408 film Substances 0.000 description 7
- 230000001965 increasing effect Effects 0.000 description 7
- 239000007772 electrode material Substances 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 230000035515 penetration Effects 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000002708 enhancing effect Effects 0.000 description 4
- 229910010272 inorganic material Inorganic materials 0.000 description 4
- 239000011147 inorganic material Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The application discloses a display panel and a preparation method thereof, wherein the preparation method of the display panel comprises the following steps: providing a substrate; preparing a substrate layer on the substrate; preparing a plurality of grooves on the substrate layer; and preparing electrode wires on the substrate layer and in the grooves, wherein the electrode wires are embedded electrode wires. The application has the technical effects that the embedded electrode wiring reduces the line width, increases the distribution density of the electrode wiring, increases the distribution density of the sub-pixels and improves the aperture opening ratio of the display panel.
Description
Technical Field
The application relates to the field of display, in particular to a display panel and a preparation method thereof.
Background
The TFT-LCD is popular because of its advantages of good quality, low cost, light weight, convenient carrying, long service life, clear picture, high reliability, etc. TFT-LCD products are seen everywhere in our daily life, as large as commercial advertisements and as small as smartwatches. Because of its high reliability, it is also used in a large number in the military industry, such as aerospace and the like. Although many advanced display modes such as OLED, QD, LED, micro-LED, ink screen, etc. are now emerging, the TFT-LCD has not been completely replaced for various reasons such as cost, lifetime, reliability, materials, technical hurdles, etc. TFT-LCDs still occupy a large market share.
With the progress of social science and technology and the improvement of life quality of people, especially the expansion of application scenes, more and higher requirements are put forward on display screens by people. The display screen has the advantages of simple display from the original to the current readable and writable, interactive and high response speed, high color gamut, high contrast ratio and the like. These high demands for display quality have prompted panel manufacturers to continue technological innovations, seeking new solutions to meet consumer needs. The OLED display technology can not only meet the requirements of high response speed, high color gamut, high contrast, etc., but also integrate many functions such as TP, sensor, etc. Moreover, the OLED can be made thinner, flexible, and the like. The disadvantage of the OLED is the lifetime problem of the luminescent material, as well as the higher cost, which reduces the market competitiveness of the OLED.
Although the advent of OLED has divided the market for TFT-LCDs, resulting in a decrease in the market share of TFT-LCDs, the innovation of TFT-LCDs has never been stopped. In recent years, in order to stabilize market share, the display quality of the TFT-LCD is greatly improved. Such as dual cell technology, mini backlight technology, etc.
The current common methods for improving the pixel aperture ratio are as follows:
(1) The electrode wiring is made finer, but the resistance is increased, so that the delay phenomenon of RC is more serious;
(2) Adopting DBS technology to shade instead of BM shading;
(3) The novel semiconductor material is adopted, so that the size of the TFT is reduced;
(4) Transparent electrode wiring is adopted, but transparent electrode wiring materials are immature and the like;
New methods are needed to further enhance the aperture ratio of the pixels.
Disclosure of Invention
The application aims to provide a display panel and a preparation method thereof, which can solve the technical problem that the prior display panel has poor effect of improving the pixel aperture ratio.
The application provides a preparation method of a display panel, which comprises the following steps: providing a substrate; preparing a substrate layer on the base plate; preparing a plurality of grooves on the substrate layer; and preparing electrode wires on the substrate layer and in the grooves, wherein the electrode wires are embedded electrode wires.
Further, in the step of preparing a plurality of grooves on the substrate layer, sequentially performing exposure, development and solidification treatment on the substrate layer to form the grooves; the depth of the groove is 2-5 micrometers.
Further, in the step of preparing electrode wires on the substrate layer and in the grooves, a metal film is formed on the substrate layer and in the grooves entirely; patterning the metal film by adopting modes of exposure, development and etching to form electrode wiring; the electrode trace fills into the recess and extends onto the substrate layer.
Further, the thickness of the metal film is greater than the depth of the groove; the thickness of the metal film arranged on the substrate layer is 0.2-0.5 micrometers.
Further, the step of preparing the electrode trace on the substrate layer and in the groove includes preparing the gate trace and preparing the source-drain electrode trace sequentially.
Further, in the step of preparing the gate wiring, a first substrate layer is prepared on the substrate; preparing a plurality of first grooves on the first substrate layer; and preparing the grid electrode wiring on the first substrate layer and in the first groove.
Further, the step of preparing the gate wire further includes: preparing a gate insulating layer on the first substrate layer and the gate wire; and depositing a layer of semiconductor material on the gate insulating layer to form an active layer, wherein the active layer is arranged opposite to the gate wiring.
Further, in the step of preparing the source-drain electrode wiring, a layer of transparent substrate material is coated on the active layer and the gate insulating layer to form a second substrate layer, and a second groove is formed on the second substrate layer; and forming the source-drain electrode wiring in the second deposition layer and the second groove.
The present application also provides a display panel including: a substrate; a substrate layer disposed on the substrate; a plurality of grooves are formed in the substrate layer; and electrode wires filled in the grooves and extending to the upper surface of the substrate layer, wherein the electrode wires are embedded electrode wires.
Further, the line width of the electrode wiring is a vertical line width, and the vertical line width is 2-5 micrometers.
The embedded grid electrode wiring and/or source-drain electrode wiring changes most of the horizontal line width into the vertical line width, reduces the occupied area of the electrode wiring on the substrate layer, increases the distribution density of the electrode wiring, further increases the distribution density of the sub-pixels, enhances the aperture ratio of the pixels, and further can improve the contrast ratio, the penetration rate or the transparency of the display panel.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present application;
FIG. 2 is a schematic diagram of an embodiment of the present application after a groove preparation step;
FIG. 3 is a cross-sectional view of an electrode trace preparation step according to an embodiment of the present application;
FIG. 4 is a top view of an electrode trace provided by an embodiment of the present application;
FIG. 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present application;
fig. 6 is a top view of a display panel according to an embodiment of the present application.
Reference numerals illustrate:
1. a substrate; 2. a first substrate layer; 3. a gate trace; 4. a gate insulating layer; 5. an active layer; 6. a second substrate layer; 7. source-drain electrode wiring; 8. a passivation layer; 9. a sub-pixel;
21. A first groove;
31. a first gate trace; 32. a second gate trace;
61. A second groove; 62. a contact hole;
71. a first source-drain electrode trace; 72. a second source drain electrode wiring; 73. a third source-drain electrode wiring;
81. and passivating the layer through hole.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and description only, and is not intended to limit the application. In the present application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
The embodiment of the application provides a display panel and a preparation method thereof. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.
The application provides a preparation method of a display panel, which comprises the following steps: providing a substrate; preparing a substrate layer on the substrate; preparing a plurality of grooves on the substrate layer; and preparing electrode wires on the substrate layer and in the grooves.
As shown in fig. 1, the method for manufacturing a display panel provided in this embodiment includes the above-mentioned manufacturing steps, where the electrode trace includes a gate trace and a source drain electrode trace, and the steps for manufacturing the gate trace and/or the source drain electrode trace may all use the above-mentioned method, and in this embodiment, the steps S1 to S8 are specifically included in this embodiment, where the above-mentioned manufacturing method is used for both the electrode traces.
S1 provides a substrate 1, wherein the substrate 1 is a hard substrate, typically a glass substrate, and plays a role of supporting a thin film.
S2 a first substrate layer 2 is prepared on the substrate 1 and a number of first grooves 21 are prepared on the substrate layer 2 (see fig. 2). Specifically, a transparent substrate material is coated on the whole surface of the substrate 1 to form the substrate layer 2, a plurality of first grooves 21 are formed on the first substrate layer 2 by adopting modes of exposure, development, curing treatment and the like in sequence, the first grooves 21 can be through hole structures penetrating through the first substrate layer 2 or groove structures not penetrating through the first substrate layer 2, the depth of the first grooves 21 is 2-5 micrometers, the first grooves 21 are strip-shaped grooves, and the first grooves 21 are used for filling electrode materials.
And S3, preparing electrode wires on the first substrate layer 2 and in the first groove 21, wherein the electrode wires are grid wires 3, and the grid wires 3 are embedded electrode wires. Specifically, a metal film is formed on the upper surface of the first substrate layer 2 and the entire inner surface of the first groove 21, and the metal film is patterned by exposing, developing and etching in sequence to form the gate trace 3 (see fig. 3 and 4), wherein the gate trace 3 is filled into the first groove 21 and extends to the upper surface of the first substrate layer 2, in this embodiment, the gate trace disposed in the first groove 21 is defined as a first gate trace 31, the gate trace disposed on the upper surface of the first substrate layer 2 is defined as a second gate trace 32, and the first gate trace 31 and the second gate trace 32 are disposed perpendicular to each other in a top view (see fig. 4).
At this time, since the first groove 21 is a long-strip-shaped groove and has a deeper depth, the volume of the first groove 21 is larger, that is, the proportion of the first gate trace 31 disposed in the first groove 21 is larger, the proportion of the second gate trace 32 is smaller, the thickness of the second gate trace 32 is 0.2-0.5 micrometer, and the orthographic projection area of the second gate trace 32 on the first substrate layer 2 is also micrometer-sized, that is, the line width of the gate trace 3 prepared by the embodiment is changed from the original horizontal line width to the vertical line width, and on the premise of providing the same amount of gate material, the thickness and the surface area of the second gate trace 32 are greatly reduced due to the existence of the first gate trace 31, the horizontal line width of the gate trace 3 is reduced to be less than 2 micrometers, which is equivalent to greatly reducing the line width of the gate trace 3, and enhancing the distribution density of the gate trace 3.
S4, preparing a gate insulating layer 4 on the first substrate layer 2 and the gate wire 3, specifically, depositing a layer of inorganic insulating material on the first substrate layer 2 and the gate wire 3, wherein the inorganic insulating material may include one or more mixed materials such as silicon oxide, silicon nitride, silicon oxynitride and the like, so as to form the gate insulating layer 4, and the gate insulating layer 4 has a good insulating effect and prevents a short circuit problem between the gate wire 3 and the source drain electrode wire 7.
S5 an active layer 5 is prepared on the gate insulating layer 4, specifically, a layer of semiconductor material is deposited on the upper surface of the gate insulating layer 4, in this embodiment, the semiconductor material includes an amorphous silicon material (a-Si), and an active layer 5 is formed, where the active layer 5 is disposed opposite to the gate trace 3.
S6 preparing a second substrate layer 6 on the upper surfaces of the active layer 5 and the gate insulating layer 4, and forming a plurality of second grooves 61 on the second substrate layer 6. Specifically, a layer of transparent substrate material is deposited on the upper surfaces of the active layer 5 and the gate insulating layer 4 to form a second substrate layer 6, where the second substrate layer 6 is the same as or different from the material used in the first substrate layer 2, and both functions as a substrate and as a support.
And a plurality of second grooves 61 are formed on the second substrate layer 6 by adopting modes of exposure, development, curing treatment and the like in sequence, wherein the second grooves 61 can be through hole structures penetrating through the second substrate layer 6 or groove structures not penetrating through the second substrate layer 6, the depth of the second grooves 61 is 2-5 micrometers, the second grooves 61 are strip-shaped grooves, and the second grooves 61 are used for filling electrode materials.
At the same time of preparing the second groove 61, a contact hole 62 can also be prepared, the contact hole 62 is disposed opposite to the active layer 5, and a part of the active layer 5 is exposed, and the contact hole 62 is used as a connection channel between the source drain electrode wire 7 and the active layer 5. After the contact hole 62 is formed, the conductive treatment may be performed, and after the portion of the active layer 5 exposed in the contact hole 62 is conductive, the electrical connection between the active layer 5 and the source-drain electrode trace 7 may be realized, and the portion of the active layer 5 that is not exposed still maintains the semiconductor characteristic and serves as a channel region.
And S7, preparing electrode wires on the second substrate layer 6, in the second groove 61 and in the contact hole 62, wherein the electrode wires are the source-drain electrode wires 7, and the source-drain electrode wires 7 are embedded electrode wires. Specifically, a metal film is formed on the upper surface of the second substrate layer 6, the second recess 61 and the contact hole 62, and is subjected to patterning processing by sequentially exposing, developing and etching, so as to form the source-drain electrode trace 7, and the source-drain electrode trace 7 is filled into the second recess 61 and the contact hole 62 and extends to the upper surface of the second substrate layer 6. In this embodiment, the source-drain electrode trace disposed in the second groove 61 is defined as a first source-drain electrode trace 71, the source-drain electrode trace disposed on the upper surface of the second substrate layer 6 is defined as a second source-drain electrode trace 72, the source-drain electrode trace disposed in the contact hole 62 is defined as a third source-drain electrode trace 73, and the first source-drain electrode trace 71 and the second source-drain electrode trace 72 are disposed perpendicular to each other in a top view (see fig. 6), and the third source-drain electrode 73 serves as an electrical connection channel between the source-drain electrode trace 7 and the active layer 5.
In this case, similarly, since the second groove 61 is a long groove and has a deeper depth, the volume of the second groove 61 is larger, that is, the proportion of the first source-drain electrode trace 71 disposed in the second groove 61 is larger, the proportion of the second source-drain electrode trace 72 is smaller, the thickness of the second source-drain electrode trace 72 is 0.2-0.5 micrometer, and the area of the orthographic projection of the second source-drain electrode trace 72 on the second substrate layer 6 is also micrometer, that is, the line width of the source-drain electrode trace 7 prepared in this embodiment is changed from the original horizontal line width to the vertical line width, and on the premise of providing the same amount of source-drain electrode material, the thickness and the surface area of the second source-drain electrode trace 72 are greatly reduced due to the presence of the first source-drain electrode trace 71, so that the horizontal line width of the source-drain electrode trace 7 is reduced to less than 2 micrometers, which is equivalent to greatly reducing the line width of the source-drain electrode trace 7 and enhancing the source-drain electrode trace 7.
S8, preparing a passivation layer 8 and a sub-pixel 9 on the source-drain electrode trace 7 (see fig. 5 and 6), specifically, depositing a layer of inorganic material on the upper surface of the source-drain electrode trace 7, where the inorganic material is an insulating material, so as to form the passivation layer 8. A passivation layer via 81 (see fig. 6) is formed by opening a hole in the passivation layer 8, the passivation layer via 81 facilitating connection of the electrode of the sub-pixel 9 with the source-drain electrode trace 7.
Because one sub-pixel 9 corresponds to one source-drain electrode trace 7 and one gate trace 3, when the line widths of the gate trace 3 and the source-drain electrode trace 7 are reduced, the distribution density of the gate trace 3 and the source-drain electrode trace 7 is increased, the distribution density of the sub-pixel 9 is further increased, and the aperture ratio of the pixel is greatly improved without increasing the resistance, so that the contrast, the penetration rate or the transparency of the display panel obtained by the preparation can be improved.
The technical effect of the manufacturing method of the display panel of the embodiment is that the embedded gate wiring and/or source-drain electrode wiring changes most of the horizontal line width into the vertical line width, reduces the occupied area of the electrode wiring on the substrate layer, increases the distribution density of the electrode wiring, further increases the distribution density of the sub-pixels, enhances the aperture ratio of the pixels, and further can improve the contrast ratio, the penetration ratio or the transparency of the manufactured display panel.
The present embodiment also provides a display panel, including: the electrode wiring part is arranged in the groove and extends to the upper surface of the substrate layer, the electrode wiring is an embedded electrode wiring, the electrode wiring comprises a gate wiring and a source-drain electrode wiring, and the gate wiring and/or the source-drain electrode wiring are/is the embedded electrode wiring.
As shown in fig. 2 to 6, in this embodiment, the gate wiring and the source/drain electrode wiring are embedded electrode wirings, and the display panel includes a substrate 1, a first substrate layer 2, a gate wiring 3, a gate insulating layer 4, an active layer 5, a second substrate layer 6, a source/drain electrode wiring 7, a passivation layer 8, and a subpixel 9.
The substrate 1 is a hard substrate, typically a glass substrate, and serves to support a thin film.
As shown in fig. 2, the first substrate layer 2 is disposed on the upper surface of the substrate 1, and the substrate layer 2 has a plurality of first grooves 21 thereon. The first groove 21 may be a through hole structure penetrating through the first substrate layer 2, or may be a groove structure not penetrating through the first substrate layer 2, the depth of the first groove 21 is 2-5 micrometers, the first groove 21 is a strip groove, and the first groove 21 is used for filling electrode materials.
As shown in fig. 3 and 4, the gate wire 3 is disposed on the first substrate layer 2 and in the first groove 21, the gate wire 3 is an embedded electrode wire, and the gate wire 3 is made of a metal material. The gate wire 3 is filled into the first groove 21 and extends to the upper surface of the first substrate layer 2, in this embodiment, the gate wire disposed in the first groove 21 is defined as a first gate wire 31, the gate wire disposed on the upper surface of the first substrate layer 2is defined as a second gate wire 32, and the first gate wire 31 and the second gate wire 32 are disposed perpendicular to each other in a top view.
At this time, since the first groove 21 is a long-strip-shaped groove and has a deeper depth, the volume of the first groove 21 is larger, that is, the proportion of the first gate trace 31 disposed in the first groove 21 is larger, the proportion of the second gate trace 32 is smaller, the thickness of the second gate trace 32 is 0.2-0.5 micrometer, and the orthographic projection area of the second gate trace 32 on the first substrate layer 2 is also micrometer-sized, that is, the line width of the gate trace 3 prepared by the embodiment is changed from the original horizontal line width to the vertical line width, and on the premise of providing the same amount of gate material, the thickness and the surface area of the second gate trace 32 are greatly reduced due to the existence of the first gate trace 31, the horizontal line width of the gate trace 3 is reduced to be less than 2 micrometers, which is equivalent to greatly reducing the line width of the gate trace 3, and enhancing the distribution density of the gate trace 3.
The gate insulating layer 4 is disposed on the first substrate layer 2 and the gate trace 3, the material of the gate insulating layer 4 is an inorganic insulating material, the inorganic insulating material may include one or more mixed materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., the gate insulating layer 4 has a good insulating effect, so that a short circuit problem is prevented between the gate trace 3 and the source drain electrode trace 7.
The active layer 5 is disposed on the gate insulating layer 4, the active layer 5 is disposed opposite to the gate trace 3, and the active layer 5 is made of a semiconductor material, which in this embodiment includes an amorphous silicon material (a-Si).
The second substrate layer 6 is disposed on the upper surfaces of the active layer 5 and the gate insulating layer 4, and the second substrate layer 6 has a plurality of second grooves 61 and contact holes 62 thereon. The second substrate layer 6 is the same as or different from the material used for the first substrate layer 2, and serves as a substrate and a support.
The second groove 61 may be a through hole structure penetrating through the second substrate layer 6, or may be a groove structure not penetrating through the second substrate layer 6, the depth of the second groove 61 is 2-5 micrometers, the second groove 61 is a strip groove, and the second groove 61 is used for filling electrode materials.
The contact hole 62 is disposed opposite to the active layer 5, exposing a portion of the active layer 5, and the contact hole 62 is used as a connection channel between the source drain electrode trace 7 and the active layer 5. After the portion of the active layer 5 exposed in the contact hole 62 is conductive, the active layer 5 and the source-drain electrode trace 7 may be electrically connected, and the portion of the active layer 5 that is not exposed still maintains the semiconductor characteristics and serves as a channel region.
As shown in fig. 5 and 6, the source-drain electrode wire 7 is disposed on the second substrate layer 6, in the second recess 61 and in the contact hole 62, and the source-drain electrode wire 7 is an embedded electrode wire. The source-drain electrode trace 7 is filled into the second recess 61 and the contact hole 62, and extends to the upper surface of the second substrate layer 6. In this embodiment, the source-drain electrode trace disposed in the second groove 61 is defined as a first source-drain electrode trace 71, the source-drain electrode trace disposed on the upper surface of the second substrate layer 6 is defined as a second source-drain electrode trace 72, the source-drain electrode trace disposed in the contact hole 62 is defined as a third source-drain electrode trace 73, the first source-drain electrode trace 71 and the second source-drain electrode trace 72 are disposed perpendicular to each other in a top view, and the third source-drain electrode 73 is used as an electrical connection channel between the source-drain electrode trace 7 and the active layer 5.
In this case, similarly, since the second groove 61 is a long groove and has a deeper depth, the volume of the second groove 61 is larger, that is, the proportion of the first source-drain electrode trace 71 disposed in the second groove 61 is larger, the proportion of the second source-drain electrode trace 72 is smaller, the thickness of the second source-drain electrode trace 72 is 0.2-0.5 micrometer, and the area of the orthographic projection of the second source-drain electrode trace 72 on the second substrate layer 6 is also micrometer, that is, the line width of the source-drain electrode trace 7 prepared in this embodiment is changed from the original horizontal line width to the vertical line width, and on the premise of providing the same amount of source-drain electrode material, the thickness and the surface area of the second source-drain electrode trace 72 are greatly reduced due to the presence of the first source-drain electrode trace 71, so that the horizontal line width of the source-drain electrode trace 7 is reduced to less than 2 micrometers, which is equivalent to greatly reducing the line width of the source-drain electrode trace 7 and enhancing the source-drain electrode trace 7.
The passivation layer 8 is arranged on the source-drain electrode wiring 7 to prepare the passivation layer 8, the passivation layer 8 is made of an inorganic material, and the inorganic material is an insulating material to form the passivation layer 8. A passivation layer via 81 is formed by opening a hole in the passivation layer 8, and the passivation layer via 81 facilitates connection between the electrode of the sub-pixel 9 and the source/drain electrode trace 7.
The sub-pixels 9 are disposed on the passivation layer 8 and extend into the passivation layer through holes 81, and the sub-pixels can realize the light emitting function of the display panel.
Because one sub-pixel 9 corresponds to one source-drain electrode trace 7 and one gate trace 3, when the line widths of the gate trace 3 and the source-drain electrode trace 7 are reduced, the distribution density of the gate trace 3 and the source-drain electrode trace 7 is increased, the distribution density of the sub-pixel 9 is further increased, and the aperture ratio of the pixel is greatly improved without increasing the resistance, so that the contrast, the penetration rate or the transparency of the display panel obtained by the preparation can be improved.
The technical effect of the display panel of this embodiment is that the embedded gate wiring and/or source-drain electrode wiring changes most of the horizontal line width into the vertical line width, reduces the occupied area of the electrode wiring on the substrate layer, increases the distribution density of the electrode wiring, further increases the distribution density of the sub-pixels, enhances the aperture ratio of the pixels, and further can improve the contrast ratio, the penetration ratio or the transparency of the display panel.
The foregoing has described in detail a display panel and a method for manufacturing the same, which are provided by the embodiments of the present application, wherein specific examples are applied to illustrate the principles and embodiments of the present application, and the above examples are only used to help understand the method and core idea of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (6)
1. A method for manufacturing a display panel, comprising the steps of:
Providing a substrate;
Preparing a substrate layer on the base plate;
preparing a plurality of grooves on the substrate layer; and
Preparing electrode wires on the substrate layer and in the grooves, wherein the electrode wires are embedded electrode wires;
the step of preparing electrode wires on the substrate layer and in the grooves comprises the steps of sequentially preparing a grid electrode wire and a source-drain electrode wire, wherein one sub-pixel corresponds to one source-drain electrode wire and one grid electrode wire;
The step of preparing the gate wire comprises the following steps: preparing a first substrate layer on the substrate; preparing a plurality of first grooves on the first substrate layer; preparing the grid wire on the first substrate layer and in the first groove, wherein the grid wire is filled in the first groove and extends to the upper surface of the first substrate layer; preparing a gate insulating layer on the first substrate layer and the gate wire; depositing a layer of semiconductor material on the gate insulating layer to form an active layer, wherein the active layer is arranged opposite to the gate wiring;
the step of preparing the source-drain electrode wiring comprises the following steps: coating a layer of transparent substrate material on the active layer and the gate insulating layer to form a second substrate layer, and forming a second groove on the second substrate layer; and forming source-drain electrode wires on the second substrate layer and in the second grooves, wherein the source-drain electrode wires are filled in the second grooves and extend to the upper surfaces of the second substrate layer.
2. The method of manufacturing a display panel according to claim 1, wherein in the step of manufacturing grooves on the substrate layer,
Sequentially exposing, developing and curing the substrate layer to form the grooves; the depth of the groove is 2-5 micrometers.
3. The method of manufacturing a display panel according to claim 1, wherein in the step of manufacturing electrode wires on the substrate layer and in the grooves,
Forming a metal film on the substrate layer and on the whole inside the groove;
Patterning the metal film by adopting modes of exposure, development and etching to form the electrode wiring;
The electrode trace fills into the recess and extends onto the substrate layer.
4. The method for manufacturing a display panel according to claim 3,
The thickness of the metal film is larger than the depth of the groove;
the thickness of the metal film arranged on the substrate layer is 0.2-0.5 micrometers.
5. A display panel, comprising:
A substrate;
The first substrate layer is arranged on the surface of the substrate and is provided with a plurality of first grooves;
The grid electrode wire is arranged on the first substrate layer and in the first groove, is an embedded electrode wire, is filled in the first groove and extends to the upper surface of the first substrate layer;
the grid insulation layer is arranged on the first substrate layer and the grid wiring;
an active layer disposed on the gate insulating layer;
The second substrate layer is arranged on the surfaces of the active layer and the gate insulating layer and is provided with a plurality of second grooves; and
The source-drain electrode wire is arranged on the second substrate layer and in the second groove, the source-drain electrode wire is an embedded electrode wire, and the source-drain electrode wire is filled in the second groove and extends to the upper surface of the second substrate layer, and one sub-pixel corresponds to one source-drain electrode wire and one grid wire.
6. The display panel of claim 5, wherein,
The line width of the electrode wiring is a vertical line width, and the vertical line width is 2-5 microns.
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| CN208766968U (en) * | 2018-09-29 | 2019-04-19 | 昆山国显光电有限公司 | A kind of flexible display panels and flexible display apparatus |
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