CN113284910B - Display backboard, manufacturing method and display device - Google Patents
Display backboard, manufacturing method and display device Download PDFInfo
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- CN113284910B CN113284910B CN202110489331.6A CN202110489331A CN113284910B CN 113284910 B CN113284910 B CN 113284910B CN 202110489331 A CN202110489331 A CN 202110489331A CN 113284910 B CN113284910 B CN 113284910B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
The embodiment of the application provides a display backboard, a manufacturing method and a display device, wherein the display backboard comprises a substrate, a thin film transistor and an interlayer dielectric layer, the interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the second dielectric layer is far away from the substrate relative to the first dielectric layer; the compactness of the second dielectric layer is lower than that of the first dielectric layer; the interlayer dielectric layer is provided with a via hole, the part of the via hole on the second dielectric layer is of a wet etching structure, and the part of the via hole on the first dielectric layer is of a dry etching structure. In this embodiment, the interlayer dielectric layers are manufactured into laminated structures with different compactness, the dielectric layers with low compactness are positioned on the outer side, the wet etching is adopted to manufacture the via holes, the dielectric layers with high compactness are positioned on the inner side, and the via holes are continuously manufactured through dry etching after the wet etching of the outer side is finished, so that the via holes with wet etching structures and dry etching structures are obtained, the photoresist denaturation can be avoided, the high uniformity can be ensured, and the product yield of the display backboard is improved.
Description
Technical Field
The embodiment of the application relates to the technical field of display devices, in particular to a display backboard, a manufacturing method and a display device.
Background
The display back plate of the large-sized, high-resolution display device generally adopts a top gate type thin film transistor, which has a higher on-state current (Ion), a higher aperture ratio, and a better stability than a bottom gate type thin film transistor.
The top gate type thin film transistor comprises an active layer, a gate insulating layer, a gate, a source electrode, a drain electrode and an interlayer dielectric layer, wherein the source electrode and the drain electrode are connected with the active layer through a via hole on the interlayer dielectric layer. In the case where the semiconductor material in the thin film transistor is a metal oxide, for example IGZO, pure silicon oxide is used for the interlayer dielectric layer in order to achieve better stability of oxide characteristics.
When the thickness of the interlayer dielectric layer made of silicon oxide is large, a large overetching amount is needed for forming a via hole on the interlayer dielectric layer in a dry etching mode, the dry etching time is long due to the large overetching amount, photoresist is easy to denature and not be stripped cleanly after long-time dry etching, and metal lap joint failure is easy to form a dark point when denatured photoresist is accumulated in the via hole; however, when forming a via hole on the interlayer dielectric layer by wet etching, uniformity is poor, and the SiO2 etching liquid can corrode the IGZO layer to cause poor contact of the via hole, so that a wet etching and dry etching method is adopted.
Disclosure of Invention
In view of the above, an objective of the embodiments of the present application is to provide a display back plate, a manufacturing method and a display device.
In a first aspect, an embodiment of the present application provides a display back plate, including a substrate and a thin film transistor disposed on the substrate, where the thin film transistor includes an active layer, a gate, a source, a drain, and an interlayer dielectric layer, the gate is disposed on a side of the active layer away from the substrate, and the interlayer dielectric layer separates the gate, the source, and the drain;
the interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the second dielectric layer is far away from the substrate relative to the first dielectric layer; the compactness of the second medium layer is lower than that of the first medium layer; the interlayer dielectric layer is provided with a via hole, the part of the via hole on the second dielectric layer is of a wet etching structure, and the part of the via hole on the first dielectric layer is of a dry etching structure. In the display backboard, the interlayer dielectric layers are manufactured into laminated structures with different compactness, the dielectric layers with low compactness are positioned on the outer side, the wet etching is adopted to manufacture the via holes, the dielectric layers with high compactness are positioned on the inner side, and the via holes with wet etching structures and dry etching structures are obtained by continuously manufacturing the via holes through dry etching after the wet etching of the outer side is finished.
In one possible embodiment, the gate is made of an oxidation resistant metal.
In a possible implementation manner, the grid electrode is made of an oxidizable metal, the interlayer dielectric layer further comprises a third dielectric layer, the third dielectric layer is close to the substrate relative to the first dielectric, and the compactness of the third dielectric layer is lower than that of the first dielectric layer; the via includes a dry etched structure in the third dielectric layer.
In one possible embodiment, the thickness of the third dielectric layer and the first dielectric layer are each smaller than the thickness of the second dielectric layer. In one possible implementation, the active layer is made of a metal oxide semiconductor material, and the interlayer dielectric layer is made of silicon oxide.
In one possible embodiment, the substrate is provided with a metallic light shielding layer and a buffer layer, the buffer layer being remote from the substrate relative to the metallic light shielding layer and being close to the substrate relative to the active layer;
the buffer layer is provided with a first via hole formed by dry etching, a metal protection layer covering the metal shading layer is arranged in the first via hole, the interlayer dielectric layer is provided with a second via hole communicated with the first via hole, and the source electrode is connected to the metal protection layer through the second via hole and the first via hole.
In one possible embodiment, a semiconductor layer is disposed on a side of the buffer layer away from the substrate, the semiconductor layer including the active layer, and the metal protection layer is formed by conducting the semiconductor layer.
In one possible embodiment, a semiconductor layer is disposed on a side of the buffer layer remote from the substrate, the semiconductor layer including the active layer, the active layer including a channel region and conductive source and drain regions, the metal protection layer being located in the source region.
In one possible embodiment, the display back plate includes a storage capacitor, the storage capacitor includes a first electrode, a second electrode, and a third electrode that are stacked, and the first electrode, the second electrode, and the third electrode are insulated from each other;
in one possible implementation manner, the display backboard is of a bottom emission structure, the source electrode is connected with a pixel electrode, and a color film layer is arranged between the pixel electrode and the substrate.
In one possible embodiment, the display back plate further includes a passivation layer and a planarization layer stacked on a side of the source electrode and the drain electrode away from the substrate.
In a second aspect, an embodiment of the present application provides a method for manufacturing a display back panel, including:
obtaining a substrate;
manufacturing an active layer, a gate insulating layer and a gate on one side of the substrate;
sequentially depositing a first dielectric layer and a second dielectric layer on one side of the grid electrode far away from the substrate, wherein the compactness of the second dielectric layer is lower than that of the first dielectric layer;
wet etching the second dielectric layer, dry etching the first dielectric layer to form a via hole. In one possible implementation manner, the fabricating an active layer, a gate insulating layer and a gate on one side of the substrate includes:
depositing a metal shading layer and a buffer layer covering the metal shading layer on one side of the substrate;
etching the buffer layer to form a first via hole exposing the metal shading layer;
and manufacturing an active layer opposite to the metal shading layer on one side of the buffer layer far away from the substrate, and manufacturing a metal protection layer covering the first via hole.
In one possible implementation manner, the fabricating an active layer opposite to the metal light shielding layer, fabricating a metal protection layer covering the second via hole, includes:
depositing a semiconductor layer by adopting a metal oxide semiconductor material;
forming a channel region pattern and a first pattern corresponding to the first via hole through a patterning process;
and conducting the first pattern to form the active layer channel and source drain metal electric connection layer.
In one possible implementation manner, the wet etching the second dielectric layer, and dry etching the first dielectric layer to form a via hole include:
manufacturing a second via hole and a third via hole, wherein the second via hole is communicated with the first via hole;
the manufacturing method further comprises the following steps:
and manufacturing a source electrode and a drain electrode through a composition process, wherein the drain electrode is connected with the active layer through the third via hole, and the source electrode is connected with the first via hole and the metal protection layer through the second via hole.
In a third aspect, embodiments of the present application also provide a display device, including a display back plate according to any one of the embodiments of the first aspect.
In one possible embodiment, the display device is an organic light-emitting semiconductor display device, and the display device further includes an organic light-emitting semiconductor light-emitting device including an anode, an organic material functional layer, and a cathode, which are sequentially stacked; the anode is connected to the source.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is apparent that the drawings in the following description are only one or more embodiments of the present application, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
Fig. 1 is a schematic structural diagram of a display back plate according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for fabricating a display back plate according to an embodiment of the present application;
FIG. 3 is a schematic diagram showing a structure of a back plate during a manufacturing process according to an embodiment of the present application;
FIG. 4 is a schematic diagram showing a second structure of the back plate during the manufacturing process according to the embodiment of the application;
fig. 5 is a schematic diagram of a structure of a back plate during a manufacturing process according to an embodiment of the application.
Reference numerals illustrate:
1-substrate, 2-buffer layer, 3-metal shading layer, 4-gate insulating layer, 5-gate, 6-active layer, 7-second dielectric layer, 8-passivation layer, 9-flat layer, 10-drain electrode, 11-source electrode, 12-pixel electrode, 13-color film layer, 14-first electrode, 15-first dielectric layer, 16-third dielectric layer, 17-third electrode and 18-second electrode.
Detailed Description
Large-size, high-resolution display devices, such as, for example, 8k products, 88 inch/95 inch oversized products, typically employ top-gate thin film transistors (Thin Film Transistor, abbreviated TFT) for the display back-plane, which have higher on-state currents (Ion), higher aperture ratios, and better stability than bottom-gate TFTs.
The top gate type TFT comprises an active layer, a gate insulating layer, a gate, a source electrode, a drain electrode and an interlayer dielectric layer, wherein the source electrode and the drain electrode are connected with the active layer through a via hole on the interlayer dielectric layer. The top gate TFT generally adopts metal oxide to manufacture active layer, such as IGZO (indium gallium zinc oxide), and the interlayer dielectric layer adopts pure silicon oxide SiO for better stability of oxide characteristics 2 。
In order to avoid display non-uniformity caused by large-size display device IR Drop (a phenomenon of voltage Drop and rise on power and ground networks in integrated circuits), the gate layer and the source-drain layer are usually made to be higher than each otherThicker, e.g.Thus, an interlayer dielectric layer of greater thickness is required, e.g. thickness +.>Above, be used for covering the position that the metal slope angle of gate layer climbs better, avoid gate layer and source drain layer to form the wiring poor.
When the thicker interlayer dielectric layer is used for manufacturing the via hole in a dry etching mode, the SiO is used for manufacturing the via hole 2 The etching rate is slower at the dry etching time and is covered on SiO 2 The photoresist is thinner, the photoresist is continuously ashed and thinned in the dry etching process, meanwhile, the temperature of the substrate is increased after long-time ion bombardment, and finally, the photoresist on the surface is changed into denatured fluoride to be solidified around and on the surface of the via hole, more photoresist remains although the photoresist is stripped by etching liquid, the ohmic contact resistance is seriously increased, and the metal lap joint at the via hole is abnormal, so that the defect of uneven display is formed.
The current and the voltage generated by the contact resistor are in a linear relation, and the I-V curve of the TFT and the voltage are in a quadratic relation, so that the relation between the contact resistor and the I-V curve of the TFT and the voltage is different, the compensation effect is seriously disturbed during electric compensation, the problem of excessive compensation occurs, and the problem of bad dark spots can occur during serious compensation, and the problem cannot be repaired.
When the thick interlayer dielectric layer is etched by a wet etching method, fluoride which is not easy to peel off is not formed by the photoresist, but the uniformity of wet etching is difficult to control, and etching liquid has certain corrosion to IGZO, and poor lap joint of an ohmic contact position is also caused.
In view of the above, the embodiment of the application provides a method for manufacturing a display backboard, which utilizes SiO with different compactness 2 The etching speed is different, the existing process is adjusted, the interlayer dielectric layer is manufactured into a laminated structure with different compactness, the compactness is low, the thicker part is positioned at the outer side, and a wet etching mode is adopted to manufacture the via hole; high compactness, thinner dielectric layer on the inner side, and continuous manufacture by dry etching after wet etching on the outer sideThrough the via hole, the problem of photoresist denaturation can be avoided through wet etching, so that metal lap joint defect caused by photoresist dry etching denaturation is reduced, high uniformity of dry etching can be utilized, and the product yield of the actual backboard is improved.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Fig. 1 is a schematic structural diagram of a display back plate according to an embodiment of the present application, and as shown in fig. 1, the display back plate includes a substrate 1, a metal light shielding layer 3, a buffer layer 2, a thin film transistor (Thin Film Transistor, abbreviated as TFT), a passivation layer 8, a planarization layer 9, a color film layer 13 and a pixel electrode 12.
Wherein the substrate 1 has a plate-like structure, and can be a glass substrate or an organic material substrate, and the glass substrate can be selected from Corning or Xuesha glass, and other materials such as quartz glass; the organic material substrate may be Polyimide (abbreviated as PI), and the PI substrate may be bent and deformed, so that the flexible display device is suitable for manufacturing a display back plate.
A metal light shielding layer 3 is provided on one side of the substrate 1 for shielding the TFT from light, and is made of a metal material such as aluminum Al, molybdenum Mo, chromium Cr, titanium Ti, or the like. The buffer layer 2 is disposed on one side of the metal shielding layer 3, and a first via hole is disposed at the position of the metal shielding layer 3, the first via hole exposes a part of the metal shielding layer 3, and the buffer layer 2 can be made of silicon oxide SiO 2 Or silicon nitride. The first via hole is manufactured by adopting a dry etching method, and the buffer layer 2 is of a single-layer structure and is thinner, so that the etching over-etching degree can be well controlled, and the problem of incomplete denaturation and stripping of photoresist can be avoided.
The TFT is provided on a side of the buffer layer 2 remote from the substrate 1 and is disposed opposite to the metal light shielding layer 3. The top gate type TFT is selected in the display backboard, and compared with the bottom gate type TFT, the top gate type TFT has higher on-state current (Ion), higher aperture opening ratio and better stability.
The TFT includes an active layer 6, a gate insulating layer 4, a gate electrode 5, a drain electrode 10, a source electrode 11, and an interlayer dielectric layer. The active layer 6 includes a channel region, a source region, and a drain region, the source electrode 11 is connected to the source region of the active layer 6, and the drain electrode 10 is connected to the drain region of the active layer 6.
The active layer 6 is made of a metal oxide semiconductor material, such as at least one of indium gallium zinc oxide (indium gallium zinc oxide, IGZO for short) and indium tin zinc oxide (indium tin oxide zinc, ITZO for short). In one possible embodiment, the source and drain regions are conductive, which can improve ohmic contact between the source 11 and drain 10 and the active layer 6, and provide a top gate TFT with better switching characteristics.
A gate insulating layer 4 and a gate 5 are laminated on the side of the active layer 6 away from the substrate 1, and the gate insulating layer can be silicon oxide SiO 2 Or silicon nitride.
The interlayer dielectric layer covers the far side of the grid electrode 5 and comprises a third dielectric layer 16, a first dielectric layer 15 and a second dielectric layer 7, and the third dielectric layer 16, the first dielectric layer 15 and the second dielectric layer 7 are sequentially stacked on the far side of the grid electrode 5 from the substrate 1; the third dielectric layer 16 and the second dielectric layer 7 are less dense than the first dielectric layer 15. The thickness of the third dielectric layer 16 and the first dielectric layer 15 are both smaller than the thickness of the second dielectric layer 7.
The third dielectric layer 16 is a low-density thin dielectric layer, can prevent the grid 5 layer from being oxidized, the first dielectric layer 15 is a high-density thin dielectric layer, can block etching of the third dielectric layer 16 by etching liquid, and the second dielectric layer 7 is a low-density thick dielectric layer, and can allow a wet etching mode to manufacture a via hole.
As can be seen from the above description, the third dielectric layer 16 can function to prevent the gate electrode 5 from being oxidized, and thus, when the gate electrode adopts an easily oxidized structure such as MoNb/Cu or MoTi/Cu, it is necessary to deposit a three-layer dielectric. When the gate adopts a Mo/Al/Mo type oxidation-resistant metal structure, the interlayer dielectric layer may only remain the first dielectric layer 15 and the second dielectric layer 7 without considering oxidation problems, and the third dielectric layer 16 is not required. The three-layer structure is described herein as an example.
Each interlayer dielectric layer can adopt silicon oxide SiO 2 Or silicon nitride, in the embodiment of the top gate type TFT in which the active layer 6 is made of metal oxide, pure silicon oxide SiO is used for the interlayer dielectric layer and the buffer layer 2 to achieve better stability of oxide characteristics 2 。
And a second via hole and a third via hole are arranged on the interlayer dielectric layer, and the second via hole is communicated with the first via hole in an aligned manner. The drain electrode 10 is connected to the active layer 6 through a third via. The first via hole is provided with a metal protection layer covering and exposing the metal shading layer 3, and the source electrode 11 is connected with the metal protection layer through the second via hole and the first via hole.
The second via hole and the third via hole are wet etched structures at the second dielectric layer 7, and the second via hole and the third via hole are dry etched structures at the first dielectric layer 15 and the third dielectric layer 16, and it should be noted that the dry etched structures are via hole structures manufactured by a dry etching process, and the wet etched structures are via hole structures manufactured by a wet etching process.
The design is that the interlayer dielectric layers are manufactured into laminated structures with different compactness, the dielectric layers with low compactness and thicker thickness are positioned on the outer side, the wet etching is adopted to manufacture the via holes, the dielectric layers with high compactness and thinner are positioned on the inner side, and the via holes are continuously manufactured through dry etching after the wet etching on the outer side is finished, so that the via holes with wet etching structures and dry etching structures are obtained.
The metal protection layer can play a certain role in protecting the metal shading layer 3, and the metal shading layer 3 is prevented from being excessively carved in the process of manufacturing the via hole through the interlayer dielectric layer, so that lap joint is not influenced, and the product yield is ensured. The metal protection layer may be separately manufactured, and when the active layer 6 is manufactured by using a metal oxide semiconductor material, the metal protection layer may be formed by metal oxide conduction, for example, a semiconductor layer made of a metal oxide semiconductor material is disposed on a side of the buffer layer 2 away from the substrate 1, the semiconductor layer includes the active layer 6, and the metal protection layer is formed by semiconductor layer conduction. The metal protection layer may also be provided in the source region of the active layer 6.
With continued reference to fig. 1, the display back plate further includes a passivation layer 8 and a planarization layer 9 deposited. The passivation layer 8 may be any one or a composite film of any of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The planarization layer is specifically an organic material layer, typically PI (polyimide) or acryl material, for example, polymethyl methacrylate (PMMA) layer. The display back plate further comprises a fourth via hole exposing the source electrode 11 through the passivation layer 8 and the flat layer 9, and a pixel electrode 12, wherein the pixel electrode 12 is arranged outside the flat layer 9 and is connected with the source electrode 11 through the fourth via hole.
The display back plate shown in fig. 1 is a bottom emission type, the projection of the pixel electrode 12 and the thin film transistor on the substrate 1 are staggered, and the display back plate further comprises a color film layer 13 arranged between the pixel electrode 12 and the substrate 1. In other embodiments, the display back panel provided by the embodiments of the present application is a top emission display back panel. Practically, both top-emitting and bottom-emitting devices are suitable.
The display backplane further comprises electrodes stored in sandwich form, including a first electrode 14, a second electrode 18 and a third electrode 17. The first electrode 14, the second electrode 18, and the third electrode 17 are insulated from each other, which means that: the first electrode 14, the second electrode 18 and the third electrode 17 are insulated from each other. That is, the first electrode 14 is insulated from the second electrode 18, the first electrode 14 is insulated from the third electrode 17, and the second electrode 18 is insulated from the third electrode 17. The first electrode 14, the second electrode 18, and the third electrode 17 form a sandwich capacitor. Compared with a storage capacitor with two electrodes, the storage capacitor with the sandwich structure can reduce the projection area of the storage capacitor on the substrate 1 under the condition that the capacitance value of the storage capacitor with two electrodes is the same, so that the opening ratio of the display backboard is increased.
The embodiment of the application provides a manufacturing method of a display backboard, which comprises the following steps:
step S10: obtaining a substrate;
step S20: manufacturing an active layer, a gate insulating layer and a gate on one side of a substrate;
step S30: sequentially depositing a first dielectric layer and a second dielectric layer on one side of the grid electrode far away from the substrate, wherein the compactness of the second dielectric layer is lower than that of the first dielectric layer; the method comprises the steps of carrying out a first treatment on the surface of the
The compactness can be adjusted by the deposition temperature and the deposition power, for example, high-temperature deposition or high-power deposition can obtain a dielectric layer with high compactness, and low-temperature deposition or low-power deposition can obtain a dielectric layer with low compactness.
Step S40: wet etching the second dielectric layer, dry etching the first dielectric layer to form the via hole.
Referring to fig. 3 to 5, in the above method, the etching speed of dielectric layers with different compactness is used to adjust the existing process, the interlayer dielectric layers are manufactured into laminated structures with different compactness, the low-compactness dielectric layers are positioned on the outer side, and the wet etching mode is used to manufacture the via holes; the high-compactness dielectric layer is positioned on the inner side, and the via hole is continuously manufactured through dry etching after wet etching on the outer side, so that the problem of photoresist denaturation can be avoided through wet etching, and therefore metal lap joint defect caused by photoresist dry etching denaturation is relieved, high uniformity of dry etching can be utilized, and the product yield of the actual backboard is improved.
As can be seen from the foregoing description, when the gate electrode adopts an easily oxidized structure such as MoNb/Cu or MoTi/Cu, a third dielectric layer needs to be deposited on the side of the first dielectric layer close to the gate electrode, so as to protect the gate electrode from being oxidized. The third dielectric layer is a low-compactness and thinner dielectric layer.
When the grid adopts a Mo/Al/Mo antioxidant metal structure, the interlayer dielectric layer can only retain the first dielectric layer and the second dielectric layer without considering the oxidation problem, and a third dielectric layer is not needed. When the interlayer dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer, the steps S30 and S40 described above become:
sequentially depositing a first dielectric layer, a second dielectric layer and a third dielectric layer on one side of the grid electrode far away from the substrate, wherein the compactness of the first dielectric layer and the third dielectric layer is lower than that of the second dielectric layer;
and wet etching the third dielectric layer, and dry etching the first dielectric layer and the second dielectric layer to form the via hole.
Optionally, step S20 includes:
depositing a metal shading layer and a buffer layer covering the metal shading layer on one side of the substrate;
the metal shielding layer can be deposited on the substrate by adopting sputtering equipment, and the buffer layer can be deposited by adopting CVD (Chemical Vapor Deposition ) equipment.
Etching the buffer layer to form a first via hole exposing the metal shading layer;
the first via hole is etched on the buffer layer in a dry etching mode, the buffer layer is single-layer and thin, the etching over-etching degree can be well controlled, and the problem that photoresist is not completely denatured and stripped can be solved.
Manufacturing an active layer opposite to the metal shading layer on one side of the buffer layer away from the substrate, and manufacturing a metal protection layer covering the first via hole;
the active layer and the metal protection layer can be separately deposited, and can also be manufactured by the following ways:
depositing a semiconductor layer by adopting a metal oxide semiconductor material;
forming a channel region pattern and a first pattern corresponding to the first via hole through a patterning process;
"patterning process" refers to a step of forming a structure having a specific pattern, which may be a photolithography process including one or more of forming a material layer, coating photoresist, exposing, developing, etching, photoresist stripping, and the like; of course, the "patterning process" may also be an imprinting process, an inkjet printing process, or other processes.
And conducting treatment on the first pattern to form a metal protection layer.
The semiconductor thin film is subjected to a semiconductor processing by chemical vapor deposition (Chemical Vapor Deposition, CVD) using a gas containing H atoms, wherein the gas containing H atoms isHydrogen (H) 2 ) Or ammonia (NH) 3 ) The H atoms (or ions) can perform ion bombardment on the metal oxide to remove O ions in the metal oxide; alternatively, the semiconductor film may be subjected to a conductive treatment by dry etching (dry etching), and since the metal oxide is not etched by the dry etching, atoms contained in the gas during the dry etching may be used to bombard the metal oxide to break chemical bonds between the metal in the metal oxide and oxygen, thereby losing oxygen in the metal oxide, the gas used for the dry etching may be helium, and the atoms bombarding the metal oxide may be inert gas atoms such as helium or Ar.
Further, step S40 includes:
manufacturing a second via hole and a third via hole, wherein the second via hole is communicated with the first via hole;
the manufacturing method further comprises the following steps:
and manufacturing a source electrode and a drain electrode through a composition process, wherein the drain electrode is connected with the active layer through a third via hole, and the source electrode is connected with the first via hole and the metal protection layer through a second via hole.
The embodiment of the application also provides a display device which comprises the display backboard in the embodiment.
The display device may be an organic light emitting semiconductor (Organic Light Emitting Diode, abbreviated as OLED) display device, or may be used for a liquid crystal display device (Liquid Crystal Display, abbreviated as LCD).
When the display device is an OLED display device, the OLED display device further comprises an OLED light-emitting device, wherein the OLED light-emitting device comprises an anode, an organic material functional layer and a cathode which are sequentially stacked, and the anode is connected with a source electrode of the TFT.
When the display device is an LCD, the backlight is provided to a light source of the display device for display. The display device includes a display back plate, a pair of cell substrates, and a liquid crystal layer disposed therebetween.
In the description of the embodiments of the present application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of description and to simplify the description, and do not indicate or imply that the apparatus or elements to be referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In describing embodiments of the present application, it should be noted that, unless explicitly stated and limited otherwise, the terms "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in embodiments of the present application will be understood in detail by those of ordinary skill in the art.
Furthermore, the technical features mentioned in the different embodiments of the application described above can be combined with one another as long as they do not conflict with one another.
Thus far, the technical solution of the present application has been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of protection of the present application is not limited to these specific embodiments. Equivalent modifications and substitutions for related technical features may be made by those skilled in the art without departing from the principles of the present application, and such modifications and substitutions will fall within the scope of the present application.
Claims (16)
1. A display back panel, characterized in that: the thin film transistor comprises an active layer, a grid electrode, a source electrode, a drain electrode and an interlayer dielectric layer, wherein the grid electrode is arranged on one side, far away from the substrate, of the active layer, and the interlayer dielectric layer separates the grid electrode, the source electrode and the drain electrode;
the interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the second dielectric layer is far away from the substrate relative to the first dielectric layer; the compactness of the second medium layer is lower than that of the first medium layer; the interlayer dielectric layer is provided with a via hole, the part of the via hole on the second dielectric layer is of a wet etching structure, and the part of the via hole on the first dielectric layer is of a dry etching structure.
2. The display back panel of claim 1, wherein: the grid electrode is made of oxidation-resistant metal.
3. The display back panel of claim 1, wherein: the grid electrode is made of oxidizable metal, the interlayer dielectric layer further comprises a third dielectric layer, the third dielectric layer is close to the substrate relative to the first dielectric layer, and the compactness of the third dielectric layer is lower than that of the first dielectric layer; the via includes a dry etched structure in the third dielectric layer.
4. A display back plate according to claim 3, wherein: the thicknesses of the third dielectric layer and the first dielectric layer are smaller than the thickness of the second dielectric layer.
5. The display back panel of claim 1, wherein: the active layer is made of a metal oxide semiconductor material, and the interlayer dielectric layer is made of silicon oxide.
6. The display back panel of claim 1, wherein: the substrate is provided with a metal shading layer and a buffer layer, and the buffer layer is far away from the substrate relative to the metal shading layer and is close to the substrate relative to the active layer;
the buffer layer is provided with a first via hole formed by dry etching, a metal protection layer covering the metal shading layer is arranged in the first via hole, the interlayer dielectric layer is provided with a second via hole communicated with the first via hole, and the source electrode is connected to the metal protection layer through the second via hole and the first via hole.
7. The display back panel of claim 6, wherein: and a semiconductor layer is arranged on one side of the buffer layer far away from the substrate, the semiconductor layer comprises the active layer, and the metal protection layer is formed by conducting the semiconductor layer.
8. The display back panel of claim 6, wherein: the buffer layer is provided with a semiconductor layer on one side far away from the substrate, the semiconductor layer comprises an active layer, the active layer comprises a channel region, a conductive source region and a conductive drain region, and the metal protection layer is located in the source region.
9. The display back panel of claim 1, wherein: the display backboard comprises a storage capacitor, wherein the storage capacitor comprises a first electrode, a second electrode and a third electrode which are arranged in a stacked mode, and the first electrode, the second electrode and the third electrode are mutually insulated.
10. The display back panel of claim 1, wherein: the display backboard is of a bottom emission structure, the source electrode is connected with a pixel electrode, and a color film layer is arranged between the pixel electrode and the substrate.
11. A method for manufacturing a display back panel, comprising:
obtaining a substrate;
manufacturing an active layer, a gate insulating layer and a gate on one side of the substrate;
sequentially depositing a first dielectric layer and a second dielectric layer on one side of the grid electrode far away from the substrate, wherein the compactness of the second dielectric layer is lower than that of the first dielectric layer;
wet etching the second dielectric layer, dry etching the first dielectric layer to form a via hole.
12. The method of manufacturing according to claim 11, wherein: the manufacturing of the active layer, the gate insulating layer and the gate on one side of the substrate comprises the following steps:
depositing a metal shading layer and a buffer layer covering the metal shading layer on one side of the substrate;
etching the buffer layer to form a first via hole exposing the metal shading layer;
and manufacturing an active layer opposite to the metal shading layer on one side of the buffer layer far away from the substrate, and manufacturing a metal protection layer covering the first via hole.
13. The method of fabricating a metal protection layer covering the first via hole, as set forth in claim 12, wherein the fabricating an active layer opposite the metal light shielding layer, comprises:
depositing a semiconductor layer by adopting a metal oxide semiconductor material;
forming a channel region pattern and a first pattern corresponding to the first via hole through a patterning process;
and conducting the first pattern to form the metal protection layer.
14. The method of claim 13, wherein wet etching the second dielectric layer and dry etching the first dielectric layer to form a via hole comprises:
manufacturing a second via hole and a third via hole, wherein the second via hole is communicated with the first via hole;
the manufacturing method further comprises the following steps:
and manufacturing a source electrode and a drain electrode through a composition process, wherein the drain electrode is connected with the active layer through the third via hole, and the source electrode is connected with the first via hole and the metal protection layer through the second via hole.
15. A display device, characterized in that: a display back sheet comprising any one of claims 1-10.
16. The display device according to claim 15, wherein: the display device is an organic light-emitting semiconductor display device, and further comprises an organic light-emitting semiconductor light-emitting device, wherein the organic light-emitting semiconductor light-emitting device comprises an anode, an organic material functional layer and a cathode which are sequentially stacked; the anode is connected to the source.
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