CN112885851B - Array substrate and preparation method thereof - Google Patents
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- CN112885851B CN112885851B CN202110130697.4A CN202110130697A CN112885851B CN 112885851 B CN112885851 B CN 112885851B CN 202110130697 A CN202110130697 A CN 202110130697A CN 112885851 B CN112885851 B CN 112885851B
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- 239000000758 substrate Substances 0.000 title claims abstract description 108
- 238000002360 preparation method Methods 0.000 title abstract description 17
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 77
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 76
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 71
- 229920005591 polysilicon Polymers 0.000 claims abstract description 52
- 239000002131 composite material Substances 0.000 claims abstract description 40
- 239000010410 layer Substances 0.000 claims description 274
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 33
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 230000035515 penetration Effects 0.000 claims description 12
- 230000001678 irradiating effect Effects 0.000 claims description 5
- HGCGQDMQKGRJNO-UHFFFAOYSA-N xenon monochloride Chemical group [Xe]Cl HGCGQDMQKGRJNO-UHFFFAOYSA-N 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 230000008025 crystallization Effects 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- HKBLLJHFVVWMTK-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti] HKBLLJHFVVWMTK-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000005283 ground state Effects 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004984 smart glass Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention discloses an array substrate and a preparation method of the array substrate, wherein the array substrate comprises the following components: a substrate; the first transistor is arranged on one side of the substrate and comprises a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer which are stacked along the vertical direction of the array substrate, wherein the conductivity of the polycrystalline composite material layer is greater than that of the metal oxide layer and less than that of the first polycrystalline silicon layer; and the second transistor is arranged on the same side of the substrate, provided with the first transistor, and comprises a second polysilicon layer. The conductivity of the polycrystalline composite material layer is stronger than that of the metal oxide layer, in the first transistor, the conductivity of the polycrystalline composite material layer is between that of the first polycrystalline silicon layer and that of the metal oxide layer, so that the electrical uniformity of the first transistor is improved, the number of required transistors is reduced, the pixel density can be improved when the polycrystalline composite material layer is applied to a display panel, and the power consumption and the leakage risk of the transistors are reduced.
Description
Technical Field
The invention belongs to the technical field of electronic products, and particularly relates to an array substrate and a preparation method of the array substrate.
Background
For the conventional LTPO (Low Temperature Polycrystalline Oxide ) display panel, since it includes LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) transistors and IGZO (indium gallium zinc oxide ) transistors, the active layers constituting the low temperature polysilicon are polysilicon and IGZO, respectively, and the IGZO is limited by process materials, and has a risk of non-uniform electrical properties, and is prone to generate problems such as leakage.
Therefore, a new array substrate and a method for manufacturing the array substrate are needed.
Disclosure of Invention
The embodiment of the invention provides an array substrate and a preparation method of the array substrate, wherein in a first transistor, the conductivity of a polycrystalline composite material layer is between the conductivity of a first polycrystalline silicon layer and the conductivity of a metal oxide layer, so that the electrical uniformity of the first transistor is improved, the number of required transistors is reduced, the pixel density can be improved when the array substrate is applied to a display panel, and the power consumption and the leakage risk of the transistors are reduced.
In one aspect, an embodiment of the present invention provides an array substrate, including: a substrate; the first transistor is arranged on one side of the substrate and comprises a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer which are stacked along the vertical direction of the array substrate, wherein the conductivity of the polycrystalline composite material layer is greater than that of the metal oxide layer and less than that of the first polycrystalline silicon layer; and the second transistor is arranged on the same side of the substrate, on which the first transistor is arranged, and comprises a second polysilicon layer.
According to one aspect of the invention, the polycrystalline composite layer comprises a metal oxide and polycrystalline silicon.
The embodiment of the invention also provides a preparation method of the array substrate, which comprises the following steps: providing a substrate; forming a first active part and a second active part on the substrate, wherein the first active part comprises a metal oxide layer and a first amorphous silicon layer which are stacked, the metal oxide layer is arranged close to the substrate, and the second active part comprises a second amorphous silicon layer; and crystallizing the first amorphous silicon layer of the first active part to form a first polycrystalline silicon layer, and heating a contact interface of the first polycrystalline silicon layer and the metal oxide layer to form a polycrystalline composite material layer.
According to another aspect of the present invention, in the step of crystallizing the first amorphous silicon layer of the first active portion: and irradiating the first amorphous silicon layer with laser so as to crystallize the first amorphous silicon layer to form a first polysilicon layer.
According to another aspect of the present invention, in the step of irradiating the first amorphous silicon layer with laser light to crystallize the first amorphous silicon layer to form a first polysilicon layer: the energy penetration depth of the laser is larger than the minimum distance between the side surface of the first amorphous silicon layer, which is in contact with the metal oxide layer, and the side surface of the first amorphous silicon layer, which is away from the metal oxide layer.
According to another aspect of the invention, the minimum distance between the side surface of the first amorphous silicon layer, which is contacted with the metal oxide layer, and the side surface of the first amorphous silicon layer, which is away from the metal oxide layer, is 4.5-5.5 nm; the energy penetration depth of the laser is 5.6 nm-7.0 nm.
According to another aspect of the invention, the laser is of a wavelength of 157nm to 353nm; preferably, the laser is a xenon chloride excimer laser with a wavelength of 308 nm.
According to another aspect of the present invention, in the step of forming the first active portion and the second active portion on the substrate: the minimum distance between the surface of the side, which is contacted with the substrate, of the metal oxide layer and the surface of the side, which is away from the substrate, of the metal oxide layer is 40-50 nm.
According to another aspect of the present invention, after the step of crystallizing the first amorphous silicon layer of the first active portion to form a first polysilicon layer, the method further includes: forming an interlayer insulating layer on one side of the first polysilicon layer away from the metal oxide layer; and forming a grid electrode layer on one side of the interlayer insulating layer, which is away from the first polysilicon layer.
According to another aspect of the present invention, after the step of forming the gate layer on a side of the interlayer insulating layer away from the first polysilicon layer, the method further includes: and forming a source drain electrode layer on one side of the first polysilicon layer, which is away from the metal oxide layer.
Compared with the prior art, the array substrate provided by the embodiment of the invention comprises the substrate, the first transistor and the second transistor, wherein the first transistor comprises the metal oxide layer, the polycrystalline composite material layer and the first polysilicon layer which are stacked along the vertical direction of the array substrate, and the atomic arrangement structure of the polycrystalline composite material layer is more neat relative to the atomic arrangement structure of the metal oxide layer. Thus, the conductivity of the polycrystalline composite layer is stronger than that of the metal oxide layer, and in the first transistor, the conductivity of the polycrystalline composite layer is between that of the first polycrystalline silicon layer and that of the metal oxide layer, so that the electrical uniformity of the first transistor is improved, the number of transistors required is reduced, the pixel density can be improved when the polycrystalline composite layer is applied to a display panel, and the power consumption and the leakage risk of the transistors are reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a film layer structure diagram of an array substrate according to an embodiment of the present invention.
FIG. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention;
FIG. 3 is a diagram of a film layer structure of an array substrate in a preparation process of the preparation method of the array substrate provided by the embodiment of the invention;
FIG. 4 is a diagram illustrating a film structure of another array substrate in the preparation process of the preparation method of an array substrate according to the embodiment of the present invention;
FIG. 5 is a diagram of a film structure of another array substrate in the preparation process of the preparation method of the array substrate according to the embodiment of the invention;
fig. 6 is a film layer structure diagram of another array substrate in the preparation process of the preparation method of the array substrate provided by the embodiment of the invention;
FIG. 7 is a diagram illustrating a film structure of another array substrate in the preparation process of the preparation method of an array substrate according to the embodiment of the present invention;
in the accompanying drawings:
1-a substrate; 20-a first transistor; 2-a first active portion; a 21-metal oxide layer; 22-a first amorphous silicon layer; 23-a first polysilicon layer; 24-a layer of polycrystalline composite material; 25-an interlayer insulating layer; 26-gate layer; 27-a source drain layer; 30-a second transistor; 3-a second active portion; 31-a second amorphous silicon layer; 4-an inorganic insulating layer.
Detailed Description
Features and exemplary embodiments of various aspects of the invention are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the invention by showing examples of the invention.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
For better understanding of the present invention, the following describes in detail an array substrate and a method for manufacturing the array substrate according to an embodiment of the present invention with reference to fig. 1 to 7.
Referring to fig. 1, an embodiment of the present invention provides an array substrate, including: a substrate 1; the first transistor 20, the first transistor 20 is disposed on one side of the substrate 1, the first transistor 20 includes a metal oxide layer 21, a polycrystalline composite material layer 24 and a first polysilicon layer 23 stacked along a vertical direction of the array substrate, and the conductivity of the polycrystalline composite material layer 24 is greater than the conductivity of the metal oxide layer 21 and less than the conductivity of the first polysilicon layer 23; the second transistor 30, the second transistor 30 is disposed on the same side of the substrate 1 where the first transistor 20 is disposed, and the second transistor 30 includes a second polysilicon layer. Optionally, an inorganic insulating layer 44 is provided between the first transistor 20 and the second transistor 30.
The array substrate provided by the embodiment of the invention comprises a substrate 1, a first transistor 20 and a second transistor 30, wherein the first transistor 20 comprises a metal oxide layer 21, a polycrystalline composite material layer 24 and a first polysilicon layer 23 which are stacked along the vertical direction of the array substrate, and the atomic arrangement structure of the polycrystalline composite material layer 24 is more neat relative to the atomic arrangement structure of the metal oxide layer 21. Thus, the conductivity of the polycrystalline composite material layer 24 is stronger than that of the metal oxide layer 21, and in the first transistor 20, the conductivity of the polycrystalline composite material layer 24 is between that of the first polycrystalline silicon layer 23 and the metal oxide layer 21, so that the electrical uniformity of the first transistor 20 is improved, the number of transistors required is reduced, the pixel density can be improved when the polycrystalline composite material layer is applied to a display panel, and the power consumption and the leakage risk of the transistors are reduced.
In some alternative embodiments, the polycrystalline composite layer 24 includes a metal oxide and polysilicon, and in particular, the polycrystalline composite layer 2 may be formed by heating and re-atomically arranging the contact interface of the first polysilicon layer 23 and the metal oxide layer 21 when forming the first polysilicon layer 23.
Referring to fig. 2 to 5, an embodiment of the present invention further provides a method for preparing an array substrate, which is used for preparing the array substrate in any one of the above embodiments, where the method for preparing an array substrate includes:
s110: providing a substrate 1, as shown in fig. 3;
s120: forming a first active portion 2 and a second active portion 3 on a substrate 1, the first active portion 2 including a metal oxide layer 21 and a first amorphous silicon layer 22 which are stacked, the metal oxide layer 21 being disposed close to the substrate 1, the second active portion 3 including a second amorphous silicon layer 31, as shown in fig. 4;
s130: the first amorphous silicon layer 22 of the first active portion 2 is subjected to crystallization treatment to form a first polysilicon layer 23, and a contact interface of the first polysilicon layer 23 and the metal oxide layer 21 is heated to form a polycrystalline composite material layer 24, as shown in fig. 5.
According to the preparation method of the array substrate provided by the embodiment of the invention, the substrate 1 is provided firstly, the substrate 1 can be a flexible or rigid substrate 1, then the first active part 2 and the second active part 3 are formed on the substrate 1, the first active part 2 comprises the metal oxide layer 21 and the first amorphous silicon layer 22 which are arranged in a stacked manner, the metal oxide layer 21 and the substrate 1 are in contact, the first amorphous silicon layer 22 is arranged on one side of the metal oxide layer 21, which is far away from the substrate 1, and then the first amorphous silicon layer 22 is subjected to crystallization treatment so that the first amorphous silicon layer 22 absorbs energy and converts the energy into the first polysilicon layer 23, in the crystallization process of the first amorphous silicon layer 22, the contact interface of the formed first polysilicon layer 23 and the metal oxide layer 21 can be heated and subjected to atomic arrangement again, so that the polycrystalline composite material layer 24 is formed, and the atomic arrangement structure of the polycrystalline composite material layer 24 is more neat relative to the atomic arrangement structure of the metal oxide layer 21. Thus, the conductivity of the polycrystalline composite material layer 24 is stronger than that of the metal oxide layer 21, and in the first active part 2, the conductivity of the polycrystalline composite material layer 24 is between the first polycrystalline silicon layer 23 and the metal oxide layer 21, so that the electrical uniformity of the first active part 2 is improved, the number of transistors required is reduced, the pixel density can be improved when the polycrystalline composite material layer is applied to a display panel, and the power consumption and the leakage risk of the transistors are reduced.
The metal oxide layer 21 may be made of IGZO (indium gallium zinc oxide ) or the like. Specifically, IGZO is an amorphous oxide containing indium, gallium and zinc, and carrier mobility is 20-30 times that of amorphous silicon, so that the charge and discharge rate of a transistor to a pixel electrode can be greatly improved, the response speed of the pixel is improved, a faster refresh rate is realized, and meanwhile, the line scanning rate of the pixel is also greatly improved due to the faster response. While the first amorphous silicon layer 22 and the second amorphous silicon layer 31 specifically refer to a film formed of a-Si (amorphous silicon ), and the first polysilicon layer 23 specifically refers to a film formed of p-Si (polycrystalline silicon, polysilicon).
Optionally, the second amorphous silicon layer 31 is crystallized by a process such as laser irradiation to form a second polysilicon layer, the second amorphous silicon layer 31 and the first amorphous silicon layer 22 may be formed by the same process, or may be formed separately, and the first active portion 2 and the second active portion 3 may be disposed in the same layer, so as to be formed conveniently, or may be disposed in different layers. There is no particular limitation.
It can be understood that the array substrate formed by the embodiment of the present invention is an array substrate formed by LTPO (Low Temperature Polycrystalline Oxide, low temperature poly oxide) process, and includes two kinds of transistors, i.e., LTPS (Low Temperature Poly-Silicon, low temperature poly Silicon) transistor and IGZO transistor, whose active layers are the first active portion 2 and the second active portion 3, respectively.
The substrate 1 may be a rigid substrate 1 or a flexible substrate 1 to provide support for the remaining film layers on the array substrate; when the substrate 1 is a rigid substrate 1, the material of the substrate 1 may be glass, and when the substrate 1 is a flexible substrate 1, the material of the substrate 1 may be polyimide; in other embodiments, the substrate 1 may also be a transparent substrate 1, so that the array substrate may be applied in a bottom-emission display panel.
Optionally, in the step of performing crystallization treatment on the first amorphous silicon layer 22 of the first active portion 2: the first amorphous silicon layer 22 is irradiated with laser light to crystallize the first amorphous silicon layer 22 to form a first polysilicon layer 23. The first amorphous silicon layer 22 is energized by laser irradiation to cause crystallization of the first amorphous silicon layer 22 to form the first polysilicon layer 23.
In some alternative embodiments, in the step of irradiating the first amorphous silicon layer 22 with laser light to crystallize the first amorphous silicon layer 22 to form the first polysilicon layer 23: the energy penetration depth of the laser is larger than the minimum distance between the side surface of the first amorphous silicon layer 22, which is in contact with the metal oxide layer 21, and the side surface of the first amorphous silicon layer 22, which is away from the metal oxide layer 21.
It should be understood that the energy penetration depth of the laser refers to the depth that the energy of the laser can penetrate deeply through the thickness of the material, that is, the depth that the energy of the laser can reach, and the energy penetration depth of the laser is greater than the minimum distance between the surface of the side, which contacts the first amorphous silicon layer 22 and the metal oxide layer 21, to the surface of the side, which faces away from the metal oxide layer 21, of the first amorphous silicon layer 22, that is, the energy of the laser can act on not only the entire first amorphous silicon layer 22 to make the first amorphous silicon layer 22 be heated and crystallized to convert into the first polysilicon layer 23, but also can act on part of the metal oxide layer 21 through the first amorphous silicon layer 22 to make part of the metal oxide layer 21 be heated to be rearranged, and combine with the adjacent part of the first polysilicon layer 23 to form a more orderly and better-conductivity polycrystalline composite material layer 24 with atomic arrangement, so as to improve the carrier mobility of the polycrystalline composite material layer 24. It will be appreciated that the energy penetration depth of the laser may be adjusted accordingly by adjusting the intensity of the laser.
In some alternative embodiments, the minimum distance between the surface of the side of the first amorphous silicon layer 22 where the metal oxide layer 21 contacts and the surface of the side of the first amorphous silicon layer 22 where the metal oxide layer 21 is away is 4.5nm to 5.5nm; the energy penetration depth of the laser is 5.6 nm-7.0 nm.
In order to avoid the excessive thickness of the array substrate, the minimum distance from the surface of the side, where the first amorphous silicon layer 22 contacts with the metal oxide layer 21, to the surface of the side, where the first amorphous silicon layer 22 faces away from the metal oxide layer 21, is 4.5nm to 5.5nm, i.e. the thickness of the first amorphous silicon layer 22 is 4.5nm to 5.5nm, so that the energy of the laser can pass through the first amorphous silicon layer 22, and the metal oxide layer 21 can be heated to perform atomic arrangement again, and the energy penetration depth of the laser can be 5.6nm to 7.0nm, so long as the energy penetration depth is greater than the thickness of the first amorphous silicon layer 22.
To ensure the absorptivity of the first amorphous silicon layer 22 to the laser energy, in some alternative embodiments, the laser is at a wavelength of 157nm to 353nm; specifically, the laser is a xenon chloride excimer laser with a wavelength of 308 nm.
In order to crystallize and convert the first amorphous silicon layer 22 into the first polysilicon layer 23, ELA (Excimer Laser Annealing ) process is required, and excimer laser emits laser light generated when molecules formed by a mixed gas of an inert gas and a halogen gas excited by an electron beam are transferred to the ground state. The pulse laser with high directivity, high wavelength purity and high output power has photon energy in 157-353 nm and service life of tens of nanoseconds, and belongs to ultraviolet light. The most common wavelengths are 157nm, 193nm, 248nm, 308nm and 351-353 nm, and the practical test shows that when the first amorphous silicon layer 22 is irradiated by using xenon chloride excimer laser with the wavelength of 308nm, the absorption rate of the first amorphous silicon layer 22 to laser energy is the highest, and the conversion rate of the first amorphous silicon layer 23 is relatively higher.
In some alternative implementations, in the step of forming the first active portion 2 and the second active portion 3 on the substrate 1: the minimum distance between the surface of the side of the metal oxide layer 21 which is in contact with the substrate 1 and the surface of the side of the metal oxide layer 21 which is away from the substrate 1 is 40nm to 50nm. Specifically, the thickness of the metal oxide layer 21 is 40nm to 50nm, and in the above embodiment, the thickness of the first amorphous silicon layer 22 is 4.5nm to 5.5nm, and the energy penetration depth of the laser may be 5.6nm to 7.0nm. Thus, after penetrating the first amorphous silicon layer 22, the laser light only acts on a portion of the metal oxide layer 21 adjacent to the first amorphous silicon layer 22, and the heated portion of the metal oxide layer 21 and the portion of the first polysilicon layer 23 in contact combine to form the polycrystalline composite layer 24. Thus, the first polysilicon layer 23, the polycrystalline composite material layer 24, and the metal oxide layer 21, which are stacked, are finally formed.
Referring to fig. 6, in some alternative embodiments, after the step of crystallizing the first amorphous silicon layer 22 of the first active portion 2 to form the first polysilicon layer 23, the method further includes: forming an interlayer insulating layer 25 on a side of the first polysilicon layer 23 facing away from the metal oxide layer 21; a gate layer 26 is formed on the side of the interlayer insulating layer 25 facing away from the first polysilicon layer 23.
It will be appreciated that the interlayer insulating layer 25 may be made of inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride, and the gate layer 26 is formed on a side of the interlayer insulating layer 25 facing away from the first polysilicon layer 23, and the gate layer 26 may be made of materials such as molybdenum metal, where the molybdenum metal has stable properties and good corrosion resistance, is not easy to react with water vapor, and is not corroded and broken by water vapor. The interlayer insulating layer 25 and the gate layer 26 may be formed in a deposition or evaporation process. Alternatively, the thickness of the interlayer insulating layer 25 is 120nm to 150nm, and the thickness of the gate layer 26 is 200nm to 300nm.
Referring to fig. 7, in some alternative embodiments, after the step of forming the gate layer 26 on the side of the interlayer insulating layer 25 facing away from the first polysilicon layer 23, the method further includes: a source drain layer 27 is formed on the side of the first polysilicon layer 23 facing away from the metal oxide layer 21.
The source/drain layer 27 may be formed by a sputtering process, in which ions in the plasma are used to bombard the electrode of the sputtered material, so that particles of the sputtered material are in the gas phase plasma, and the particles are deposited on the surface of the metal oxide layer 21 to form the source/drain layer 27, and in particular, the source/drain layer 27 may be a titanium-aluminum-titanium composite metal layer, which has good corrosion resistance and good conductivity.
The array substrate provided by the embodiment of the invention can be applied to a mobile phone and also can be applied to any electronic product with a display function, including but not limited to the following categories: television, notebook computer, desktop display, tablet computer, digital camera, smart bracelet, smart glasses, vehicle-mounted display, medical equipment, industrial control equipment, touch interactive terminal, etc., which are not particularly limited in this embodiment of the invention.
In the foregoing, only the specific embodiments of the present invention are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present invention is not limited thereto, and any equivalent modifications or substitutions can be easily made by those skilled in the art within the technical scope of the present invention, and they should be included in the scope of the present invention.
It should also be noted that the exemplary embodiments mentioned in this disclosure describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, or may be performed in a different order from the order in the embodiments, or several steps may be performed simultaneously.
Claims (11)
1. An array substrate, characterized by comprising:
a substrate;
the first transistor is arranged on one side of the substrate and comprises a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer which are stacked along the vertical direction of the array substrate, wherein the conductivity of the polycrystalline composite material layer is greater than that of the metal oxide layer and less than that of the first polycrystalline silicon layer;
and the second transistor is arranged on the same side of the substrate, on which the first transistor is arranged, and comprises a second polysilicon layer.
2. The array substrate of claim 1, wherein the polycrystalline composite layer comprises a metal oxide and polysilicon.
3. A method for manufacturing an array substrate, for manufacturing the array substrate according to any one of claims 1 to 2, comprising:
providing a substrate;
forming a first active part and a second active part on the substrate, wherein the first active part comprises a metal oxide layer and a first amorphous silicon layer which are stacked, the metal oxide layer is arranged close to the substrate, and the second active part comprises a second amorphous silicon layer;
and crystallizing the first amorphous silicon layer of the first active part to form a first polycrystalline silicon layer, and heating a contact interface of the first polycrystalline silicon layer and the metal oxide layer to form a polycrystalline composite material layer.
4. The method of manufacturing an array substrate according to claim 3, wherein in the step of crystallizing the first amorphous silicon layer of the first active portion:
and irradiating the first amorphous silicon layer with laser so as to crystallize the first amorphous silicon layer to form a first polysilicon layer.
5. The method of manufacturing an array substrate according to claim 4, wherein in the step of irradiating the first amorphous silicon layer with laser light to crystallize the first amorphous silicon layer to form a first polysilicon layer:
the energy penetration depth of the laser is larger than the minimum distance between the side surface of the first amorphous silicon layer, which is in contact with the metal oxide layer, and the side surface of the first amorphous silicon layer, which is away from the metal oxide layer.
6. The method for manufacturing an array substrate according to claim 5, wherein a minimum distance between a side surface of the first amorphous silicon layer, which is in contact with the metal oxide layer, and a side surface of the first amorphous silicon layer, which is away from the metal oxide layer, is 4.5nm to 5.5nm;
the energy penetration depth of the laser is 5.6 nm-7.0 nm.
7. The method for manufacturing an array substrate according to claim 6, wherein the laser has a wavelength of 157nm to 353nm.
8. The method for manufacturing an array substrate according to claim 7, wherein the laser is a xenon chloride excimer laser having a wavelength of 308 nm.
9. The method of manufacturing an array substrate according to claim 3, wherein in the step of forming the first active portion and the second active portion on the base:
the minimum distance between the surface of the side, which is contacted with the substrate, of the metal oxide layer and the surface of the side, which is away from the substrate, of the metal oxide layer is 40-50 nm.
10. The method of manufacturing an array substrate according to claim 3, further comprising, after the step of crystallizing the first amorphous silicon layer of the first active portion to form a first polysilicon layer:
forming an interlayer insulating layer on one side of the first polysilicon layer away from the metal oxide layer;
and forming a grid electrode layer on one side of the interlayer insulating layer, which is away from the first polysilicon layer.
11. The method for manufacturing an array substrate according to claim 10, wherein after the step of forming the gate layer on the side of the interlayer insulating layer facing away from the first polysilicon layer, the method further comprises:
and forming a source drain electrode layer on one side of the first polysilicon layer, which is away from the metal oxide layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20080056955A (en) * | 2006-12-19 | 2008-06-24 | 삼성에스디아이 주식회사 | Thin film transistor and the fabricating method using the same |
| WO2014109830A1 (en) * | 2013-01-08 | 2014-07-17 | Applied Materials, Inc. | Metal oxynitride based heterojunction field effect transistor |
| CN110752235A (en) * | 2019-10-28 | 2020-02-04 | 合肥维信诺科技有限公司 | Manufacturing method of array substrate and array substrate |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080056955A (en) * | 2006-12-19 | 2008-06-24 | 삼성에스디아이 주식회사 | Thin film transistor and the fabricating method using the same |
| WO2014109830A1 (en) * | 2013-01-08 | 2014-07-17 | Applied Materials, Inc. | Metal oxynitride based heterojunction field effect transistor |
| CN110752235A (en) * | 2019-10-28 | 2020-02-04 | 合肥维信诺科技有限公司 | Manufacturing method of array substrate and array substrate |
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