CN112350695B - Phase interpolator system, chip and electronic device - Google Patents
Phase interpolator system, chip and electronic device Download PDFInfo
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- CN112350695B CN112350695B CN202011325227.5A CN202011325227A CN112350695B CN 112350695 B CN112350695 B CN 112350695B CN 202011325227 A CN202011325227 A CN 202011325227A CN 112350695 B CN112350695 B CN 112350695B
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Abstract
The application provides a phase interpolator system, chip and electronic equipment, wherein, this phase interpolator system includes: a phase locked loop, a voltage driver and a phase interpolator; the phase interpolator includes: a phase selector and phase interpolator core module; the phase selector is connected with the phase interpolator core module; the first output end of the phase-locked loop is connected with the voltage driver; the output end of the voltage driver is connected with the input end of the phase selector and the input end of the phase interpolator core module and used for supplying power to the phase selector and the phase interpolator core module; a second output of the phase locked loop is connected to the phase selector for providing the phase clock. By the method in the embodiment of the application, the interference between the voltage of the voltage source in the component in the phase-locked loop and the voltage of the phase interpolator is reduced through the isolation of the voltage driver, and the jitter of the phase-locked loop can also be reduced.
Description
Technical Field
The present application relates to the field of chip design technologies, and in particular, to a phase interpolator system, a chip, and an electronic device.
Background
In the field of customized port physical layer, a phase interpolator is generally used to adjust the delay of data or clock, and the linearity of the phase interpolator directly affects the operation speed of the port physical layer.
Further, in the clock and data recovery system as adjusting the clock delay, in order to reduce the jitter caused by the recovery of the clock and data recovery system, the phase difference device is required to have a relatively small step size and a high phase linearity.
Therefore, in the above scenario, there is a certain requirement on the linearity of the phase interpolator.
Disclosure of Invention
An object of the present application is to provide a phase interpolator system, a chip and an electronic device, which can solve the problem of insufficient linearity of a phase interpolator.
In a first aspect, an embodiment of the present invention provides a phase interpolator system, including: a phase locked loop, a voltage driver and a phase interpolator;
the phase interpolator includes: a phase selector and phase interpolator core module;
the phase selector is connected with the phase interpolator core module;
the first output end of the phase-locked loop is connected with the voltage driver;
the output end of the voltage driver is connected with the input end of the phase selector and the input end of the phase interpolator core module and used for supplying power to the phase selector and the phase interpolator core module, and the voltage difference between a first voltage provided by the voltage driver for the phase interpolator core module and a second voltage output by the first output end of the phase-locked loop is smaller than a preset value;
the second output end of the phase-locked loop is connected with the phase selector and used for providing a phase clock.
In an alternative embodiment, the voltage driver includes: a first operational amplifier;
the first output end of the phase-locked loop is connected with the non-inverting input end of the first operational amplifier of the voltage driver;
and the inverting input end of the first operational amplifier and the output end of the first operational amplifier are used as the output end of the voltage driver and are connected with the input end of the phase selector and the input end of the phase interpolator core module.
In the above-described embodiment, by using the first operational amplifier, the voltage value input to the voltage driver by the phase-locked loop and the voltage value output by the voltage driver can be made close to each other, so that the loss of voltage can be reduced also in the case where the phase-locked loop is isolated from the phase difference device.
In an alternative embodiment, the voltage driver includes: a second operational amplifier, a first capacitor and a first transistor;
the first output end of the phase-locked loop is connected with the non-inverting input end of the second operational amplifier;
the output end of the second operational amplifier is connected with the grid electrode of the first transistor;
one end of the first capacitor is connected between the output end of the second operational amplifier and the grid electrode of the first transistor;
the drain electrode of the first transistor is connected with a power supply, and the source electrode of the first transistor and the output end of the second operational amplifier are used as the output end of the voltage driver and are connected with the input end of the phase selector and the input end of the phase interpolator core module.
In the above-described embodiment, by using the second operational amplifier, the first capacitor, and the first transistor, the voltage value input into the voltage driver by the phase-locked loop and the voltage value output by the voltage driver can be made close to each other, so that the loss of voltage can be reduced also in the case where the phase-locked loop is isolated from the phase difference device.
In an alternative embodiment, the voltage driver includes: a first resistor, a second capacitor and a second transistor;
a first output end of the phase-locked loop is connected with a first end of the first resistor;
one end of the second capacitor is connected between the second end of the first resistor and the grid electrode of the second transistor;
a second end of the first resistor is connected with a grid electrode of the second transistor;
and the drain electrode of the second transistor is connected with a power supply, and the source electrode of the second transistor is used as the output end of the voltage driver and is connected with the input end of the phase selector and the input end of the phase interpolator core module.
In the above embodiment, by using the first resistor, the second capacitor and the second transistor, the voltage value input to the voltage driver by the phase-locked loop and the voltage value output by the voltage driver can be made close to each other, and thus the loss of voltage can be reduced even when the phase-locked loop is isolated from the phase difference device.
In an alternative embodiment, the voltage driver includes: a third operational amplifier and a miller compensation module;
the first output end of the phase-locked loop is connected with the non-inverting input end of a third operational amplifier of the voltage driver;
the miller compensation module is connected to an output end of the third operational amplifier, forms an output end of the voltage driver with an inverting input end of the third operational amplifier, and is connected to an input end of the phase selector and an input end of the phase interpolator core module.
In the above embodiment, the miller compensation module is added, so that the stability of the operational amplifier can be increased, the performance of the operational amplifier can be improved, and the loss of voltage can be reduced under the condition of realizing the isolation of the phase-locked loop and the phase difference device.
In an alternative embodiment, the third operational amplifier comprises: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
the grid electrode of the third transistor is used as the inverting input end of the third operational amplifier;
the grid electrode of the fourth transistor is used as the non-inverting input end of the third operational amplifier;
the drain electrode of the third transistor is connected with the drain electrode and the grid electrode of a fifth transistor, and the source electrode of the fifth transistor is grounded;
the drain electrode of the fourth transistor is connected with the drain electrode of the sixth transistor, and the source electrode of the sixth transistor is grounded;
the grid electrode of the fifth transistor is connected with the grid electrode of the sixth transistor;
a drain of the seventh transistor is connected to a source of the third transistor and a source of the fourth transistor, and a source of the seventh transistor is connected to a power supply;
a gate of the seventh transistor is connected to a gate and a drain of the tenth transistor;
a gate of the eighth transistor is connected to a gate of the seventh transistor;
a drain of the eighth transistor is connected to a drain of the ninth transistor;
the grid electrode of the ninth transistor is connected with the drain electrode of the fourth transistor;
a gate of the ninth transistor is connected to a drain of the sixth transistor;
a source of the ninth transistor is grounded;
one end of the Miller compensation module is connected with the grid electrode of the ninth transistor;
and the other end of the Miller compensation module is connected with the drain electrode of the ninth transistor.
In an alternative embodiment, the miller compensation module comprises: a second resistor and a third capacitor;
the second resistor is connected with the third capacitor in series;
one end of the second resistor is connected with the grid electrode of the ninth transistor; the other end of the second resistor is connected with one end of the third capacitor, and the other end of the third capacitor is connected with the drain electrode of the ninth transistor.
In an alternative embodiment, the phase locked loop comprises: the phase detector, the loop filter, the voltage-controlled oscillator and the frequency divider;
the output end of the phase discriminator is connected with the input end of the loop filter;
the output end of the loop filter is connected with the input end of the voltage-controlled oscillator;
the first output end of the voltage-controlled oscillator is connected with the input end of the frequency divider;
the output end of the frequency divider is connected with the input end of the phase discriminator;
and the voltage output end of the voltage-controlled oscillator is connected with the voltage driver.
In the above embodiment, the phase-locked loop structure can implement establishment of carrier synchronization or bit synchronization between the receiving and transmitting communication parties.
In a second aspect, an embodiment of the present invention provides a chip, including the phase interpolator system according to any one of the foregoing embodiments.
In a third aspect, an embodiment of the present invention provides an electronic device, including: the chip shown in the previous embodiment.
The beneficial effects of the embodiment of the application are that: under the action of the voltage driver, the voltage input into the voltage driver can be closer to the voltage output by the voltage driver, so that the voltage driver has less influence on the linearity of the phase interpolator. Furthermore, a voltage driver is additionally arranged between the phase-locked loop and the phase interpolator, so that the voltage source corresponding to the phase-locked loop is isolated from the phase interpolator, the voltage source voltage in the components in the phase-locked loop cannot be influenced when the phase interpolator works, and the interference between the voltage source voltage in the components in the phase-locked loop and the voltage of the phase interpolator is reduced. Further, when the phase interpolator works, current is not pumped from the power supply of the phase-locked loop, so that the jitter of the phase-locked loop caused by current pumping is reduced, but the current voltage provided by the voltage driver is close to the voltage provided by the power supply of the phase-locked loop, and better linearity of the phase interpolator can be realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a phase interpolator according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a phase interpolator core module of a phase interpolator according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram illustrating comparison of clock signals corresponding to a phase interpolator core module of a phase interpolator according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram illustrating another clock signal comparison corresponding to a phase interpolator core module of the phase interpolator according to the embodiment of the present disclosure;
fig. 5 is a schematic diagram of a first structure of a phase interpolator system according to an embodiment of the present application;
fig. 6 is a schematic diagram of a second structure of a phase interpolator system according to an embodiment of the present application;
fig. 7 is a third structural diagram of a phase interpolator system according to an embodiment of the present disclosure;
fig. 8 is a fourth structural diagram of a phase interpolator system according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a third operational amplifier in a voltage driver in a phase interpolator system according to an embodiment of the present disclosure;
fig. 10a is a schematic diagram of two clock signals processed by a phase interpolator system according to an embodiment of the present application;
FIG. 10b is a schematic diagram of another two-way clock signal processed by the phase interpolator system according to the embodiment of the present application;
FIG. 11a is a diagram illustrating a phase-locked loop jitter condition of a signal processed by a prior art phase interpolator;
fig. 11b is a diagram illustrating a jitter condition of a phase-locked loop using a phase interpolator system according to an embodiment of the present disclosure.
Description of the main element symbols: 100-a phase-locked loop; 200-voltage driver; 300-phase interpolator; 110-phase detector/charge pump; 120-a loop filter; 130-a voltage controlled oscillator; 140-a frequency divider; 310-a phase selector; 320-phase interpolator core module; u1 — first operational amplifier; u2 — second operational amplifier; c1 — first capacitance; m1 — first transistor; r1 — first resistance; c2 — second capacitance; m2 — second transistor; 150-a phase detector; 160-charge pump + loop filter; m3 — third transistor; m4 — fourth transistor; m5 — fifth transistor; m6 — sixth transistor; m7-seventh transistor; m8 — eighth transistor; m9 — ninth transistor; m10-tenth transistor; c3 — third capacitance; r2-second resistance.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined or explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
First, a general phase interpolator will be described, and as shown in fig. 1, the phase interpolator may include: the phase interpolator comprises an N-phase oscillator, a phase selector and a phase interpolator core module.
The phase interpolator core module is used as a core of the phase interpolator and is used for carrying out phase interpolation processing on the clock.
Illustratively, as shown in FIG. 1, the phase interpolator is controlled by a phase interpolator controller.
In which an N-phase oscillator generates multi-phase clocks, and then a phase selector selects a specified number of clocks from the multi-phase clocks. In the example shown in fig. 1, an N-phase oscillator generates N-phase clocks, respectively: ph <1>, Ph <2>, …, Ph < N-1>, Ph < N >.
In the example shown in FIG. 1, the phase selector is an N: 2phase selector.
For example, as shown in fig. 2, the phase interpolator core module includes two control circuits, and the phase selector can select two clocks from the multi-phase clocks. The phase selector transmits the selected two sets of clocks to a phase interpolator core block. The phase interpolator core module performs phase interpolation on the two groups of input clocks.
In the example shown in fig. 1, the clocks selected by the N: 2phase selector are: ph _ even and Ph _ odd.
Wherein the phase interpolator controller controls a specified number of driver drivers to adjust the delay of the output clock, respectively.
Illustratively, the number of driver drivers whose output is controlled by the phase interpolator controller is determined by the number of control circuits in the phase interpolator core module, and in the example shown in fig. 2, the phase interpolator core module includes two control circuits, so the number of driver drivers whose output is controlled by the phase interpolator controller may also be two.
As shown in fig. 2, the phase interpolator core block includes: a plurality of inverters, a capacitor, and a resistor. The resistor is connected in parallel with one of the inverters.
Illustratively, the two drives may be the Most Significant Bit (MSB) and the Least Significant Bit (LSB), respectively.
Illustratively, as the driver drive strength at the input of the phase interpolator controller increases, the delay (delay) of the output clock is controlled by this path. For example, as shown in FIG. 2, a increases, indicating that the output clock is more controlled by in0_ pi; a decreases and the more in1_ pi the output clock is controlled.
In this embodiment, if the linearity of the clock output by the phase interpolator is required to be good, the rising edge or the falling edge of the input clock is required to be relatively slow. As shown in fig. 3, the required clock in1_ pi edge (the edge shown in fig. 3 is a rising edge) occurs on the in0_ pi edge.
Illustratively, as shown in FIG. 4, when the input clock frequency is relatively slow, the edge of the clock in1_ pi occurs at a high level of in0_ pi. In this example, the linearity of the output clock is poor.
The fractional-n pll is used as a way to reduce quantization noise of an interpolation filter (sigma delta), and the step size (step) and linearity of a phase interpolator determine the quantization noise.
By studying the direct working relation between the phase interpolator and the phase-locked loop, a phase interpolator system is provided, which can ensure that the phase interpolator keeps better linearity under the condition of reducing the jitter of the phase-locked loop.
Example one
The embodiment of the application provides a phase interpolator 300 system. As shown in fig. 5, the phase interpolator 300 system in the present embodiment includes: a Phase Locked Loop (PLL) 100, a voltage driver (buffer) 200, and a Phase Interpolator (PI) 300.
In this embodiment, the voltage driver 200 is connected between the phase locked loop 100 and the phase interpolator 300.
Illustratively, the phase interpolator 300 may include: phase selector 310(phase selection MUX) and phase interpolator core block 320(PI core). Wherein MUX represents a digital selector (multiplexer).
In this embodiment, the phase selector 310 is connected to the phase interpolator core module 320.
A first output terminal of the phase locked loop 100 is connected to the voltage driver 200.
The output of the voltage driver 200 is connected to the input of the phase selector 310 and the input of the phase interpolator core block 320 for supplying power to the phase selector 310 and the phase interpolator core block 320.
In this embodiment, the voltage difference between the first voltage provided by the voltage driver 200 for the phase interpolator core module 320 and the second voltage output by the first output terminal of the phase locked loop 100 is smaller than a predetermined value.
Alternatively, the preset value may be an upper error limit set according to requirements.
In one example, the first voltage may also be equal to the second voltage.
A second output of the phase locked loop 100 is connected to the phase selector 310 for providing a phase clock.
Illustratively, a corresponding number of clocks may be provided according to the settings of the phase interpolator 300.
Illustratively, the second output of the phase locked loop 100 may output an N-phase clock, where N is a positive integer. The phase selector 310 can select the number of clock groups required from the N-phase clocks.
For example, the phase selector 310 may be an N:2MUX, i.e., an N:2 digital selector. The N:2MUX may select two sets of clocks from the N phase clocks. Illustratively, the selected two sets of clocks may be two adjacent sets of clocks.
Illustratively, referring again to fig. 5, the phase locked loop 100 includes: phase Detector 150 (see fig. 7) (PD for short), loop filter 120 (LPF for short), Voltage controlled oscillator 130 (VCO for short), and frequency divider 140 (feedback).
Illustratively, the output of the phase detector 150 is connected to the input of the loop filter 120. The output of the loop filter 120 is connected to the input of the vco 130. A first output of the vco 130 is connected to an input of the divider 140. The output of the frequency divider 140 is connected to the input of the phase detector 150. The voltage output terminal of the vco 130 is connected to the voltage driver 200.
The phase detector 150 may be, for example, a phase frequency detector 150 (PFD).
Illustratively, as shown in fig. 5, the phase-locked loop 100 may further include: a Charge Pump (CP). The phase frequency detector 150 and the phase locked loop 100 may be designed as a combined circuit to form the phase detector/charge pump 110 shown in fig. 5.
The charge pump may also form a module with the loop filter 120, for example. As shown in fig. 7, a charge pump + loop filter 160 is formed.
In this embodiment, the voltage controlled oscillator 130 may include an inverter array and a transistor, and in the example shown in fig. 5, the voltage controlled oscillator 130 includes an inverter array formed by seven inverters. The drain of the transistor is connected to the inverter array and the source of the transistor is connected to the power supply. Illustratively, the transistors in the voltage controlled oscillator 130 may be PMOS transistors.
Illustratively, the inverter array formed by the seven inverters may include fourteen oscillating units, which are: a vco [0], a vco [1], a vco [2], a vco [3], a vco [4], a vco [5], a vco [6], a vco [7], a vco [8], a vco [9], a vco [10], a vco [11], a vco [12], a vco [13 ].
Illustratively, the phase detector 150 may receive an incoming reference clock (refclk) and process the reference clock.
Illustratively, the frequency divider 140 may return a feedback clock signal (fbclk) to the phase detector 150 after processing the signal.
In this embodiment, the voltage-controlled oscillator 130 of the Phase-locked loop 100 may input an N-Phase Clock (N Phase Clock) to the Phase selector 310 of the Phase interpolator 300. The Phase selector 310 selects two clocks (2Phase Clock) from the N Phase clocks and transmits them to the Phase interpolator core block 320 for Phase interpolation.
In one embodiment, as shown in fig. 6, the voltage driver 200 includes: a first operational amplifier U1.
A first output terminal of the phase locked loop 100 is connected to a non-inverting input terminal of a first operational amplifier U1 of the voltage driver 200.
In this embodiment, the first output terminal is used for outputting the oscillator voltage (vro) to the voltage driver 200.
The inverting input of the first operational amplifier U1 and the output of the first operational amplifier U1 are used as the output of the voltage driver 200, and are connected to the input of the phase selector 310 and the input of the phase interpolator core block 320.
The operational amplifier may function to: the signal amplifier can amplify weak signals, can be used as an inverting and voltage follower, and can perform addition and subtraction operation on electric signals, so that the output signals can meet the requirements of actual scenes.
In the embodiment of the present application, the first operational amplifier U1 can make the voltage values of the input oscillator voltage (vro) and the output replica oscillator voltage (vro _ replica) close, thereby reducing the influence of the voltage driver 200 on the linearity of the phase interpolator 300.
In another embodiment, as shown in fig. 7, the voltage driver 200 includes: a second operational amplifier U2, a first capacitor C1, and a first transistor M1.
A first output of the phase locked loop 100 is connected to a non-inverting input of the second operational amplifier U2.
The output terminal of the second operational amplifier U2 is connected to the gate of the first transistor M1.
One end of the first capacitor C1 is connected between the output terminal of the second operational amplifier U2 and the gate of the first transistor M1.
The drain of the first transistor M1 is connected to a power supply, and the source of the first transistor M1 and the output of the second operational amplifier U2 are used as the output of the voltage driver 200, and are connected to the input of the phase selector 310 and the input of the phase interpolator core block 320.
In this embodiment, as shown in fig. 7, the other end of the first capacitor C1 is connected to a power supply.
In this embodiment, as shown in fig. 7, the first transistor M1 may be an NMOS transistor.
Illustratively, the voltage driver 200 may further include a constant current source having one end connected to the source of the first transistor M1. The other end of the constant current source is grounded.
In another embodiment, as shown in fig. 8, the voltage driver 200 includes: a first resistor R1, a second capacitor C2 and a second transistor M2.
A first output terminal of the phase locked loop 100 is connected to a first terminal of the first resistor R1.
One end of the second capacitor C2 is connected between the second end of the first resistor R1 and the gate of the second transistor M2.
The second terminal of the first resistor R1 is connected to the gate of the second transistor M2.
The drain of the second transistor M2 is connected to a power supply, and the source of the second transistor M2 is used as the output terminal of the voltage driver 200, and is connected to the input terminal of the phase selector 310 and the input terminal of the phase interpolator core block 320.
Illustratively, the second transistor M2 may be a PMOS transistor.
In one embodiment, the voltage driver 200 may include: a third operational amplifier and a miller compensation module.
The miller compensation module may be a miller compensation circuit. The Miller compensation capacitor in the Miller compensation circuit moves the dominant pole to low frequency and moves the non-dominant pole to high frequency to realize pole separation. And a compensation resistor is added to move the zero point to a high frequency, so that the influence of the zero point on the stability of the system can be reduced or counteracted.
A first output terminal of the phase locked loop 100 is connected to a non-inverting input terminal of a third operational amplifier of the voltage driver 200.
The miller compensation module is connected to the output of the third operational amplifier, forms the output of the voltage driver 200 with the inverting input of the third operational amplifier, and is connected to the input of the phase selector 310 and the input of the phase interpolator core module 320.
Specifically, as shown in fig. 9, the third operational amplifier includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, and a tenth transistor M10.
Wherein the gate of the third transistor M3 is used as the inverting input terminal of the third operational amplifier. The gate of the fourth transistor M4 serves as the non-inverting input of the third operational amplifier. The drain of the third transistor M3 is connected to the drain and gate of the fifth transistor M5, and the source of the fifth transistor M5 is grounded. The drain of the fourth transistor M4 is connected to the drain of the sixth transistor M6, and the source of the sixth transistor M6 is grounded. The gate of the fifth transistor M5 is connected to the gate of the sixth transistor M6. The drain of the seventh transistor M7 is connected to the source of the third transistor M3 and the source of the fourth transistor M4, and the source of the seventh transistor M7 is connected to a power source. The gate of the seventh transistor M7 is connected to the gate and the drain of the tenth transistor M10. The gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7. The drain of the eighth transistor M8 is connected to the drain of the ninth transistor M9. The gate of the ninth transistor M9 is connected to the drain of the fourth transistor M4. The gate of the ninth transistor M9 is connected to the drain of the sixth transistor M6. The source of the ninth transistor M9 is grounded.
One end of the miller compensation module is connected to the gate of the ninth transistor M9. The other end of the miller compensation module is connected to the drain of the ninth transistor M9.
In one embodiment, as shown in fig. 9, the miller compensation module comprises: a second resistor R2 and a third capacitor C3.
The second resistor R2 is connected in series with the third capacitor C3.
One end of the second resistor R2 is connected to the gate of the ninth transistor M9; the other end of the second resistor R2 is connected to one end of the third capacitor C3, and the other end of the third capacitor C3 is connected to the drain of the ninth transistor M9.
Further, the voltage driver 200 may further include a constant current source, one end of which is connected to the drain of the tenth transistor, and the other end of which is grounded.
In the phase interpolator 300 system of the embodiment of the present application, when the operating frequency of the pll 100 is relatively low, the voltage controlled oscillator of the pll 100 generates a relatively low oscillator voltage (vro), and the rising/falling edge of the N-phase input clock of the phase selector 310 of the phase interpolator 300 is relatively slow. The replica oscillator voltage (vro _ replica) that the voltage driver 200 controls to output varies with the oscillator voltage, resulting in a lower replica oscillator voltage, so that the edges of the two input clocks of the phase interpolator core block 320 are also slower, as shown in fig. 10a, and the in1_ pi clock edge occurs on the in0_ pi edge.
In the phase interpolator 300 system of the embodiment of the present application, when the operating frequency of the pll 100 is relatively high, the electronically controlled oscillator of the pll 100 generates a relatively high oscillator voltage (vro), and the rising/falling edge of the N-phase input clock of the phase selector 310 of the phase interpolator 300 is relatively fast. The replica oscillator voltage (vro _ replica) that the voltage driver 200 controls to output varies with the oscillator voltage, generating a relatively high replica oscillator voltage, and therefore, as shown in fig. 10b, the time interval of the two input clocks of the phase interpolator core block 320 is also relatively short, so that it is satisfied that the in1_ pi clock edge occurs on the in0_ pi edge.
As shown in fig. 11a, fig. 11a shows a schematic diagram of a resulting signal that is not processed by the phase interpolator 300 system in the embodiment of the present application. Wherein the abscissa in the diagram represents the Time variable (Time/us) and the ordinate represents the jitter per picosecond (PLL Period _ jitter/ps) of the phase locked loop 100.
In the operation of the phase interpolator 300 for inputting the clock (PI operations) and the operation of the phase interpolator 300 for inputting the clock (PI operations), a significant jitter phenomenon occurs.
As shown in fig. 11b, fig. 11b is a schematic diagram of a signal obtained after processing by the phase interpolator 300 system in the embodiment of the present application.
Where the abscissa in the diagram represents the Time variable (Time/us) and the ordinate represents the jitter per picosecond (PLL Period _ jitter/ps) of the phase locked loop 100.
Among them, in the operation (PI operations) in which the phase interpolator 300 inputs the clock and the operation (PI operations) in which the phase interpolator 300 inputs the clock, the jitter is not obvious as compared with the example shown in fig. 11 a.
In the embodiment of the present application, the voltage driver 200 is additionally disposed between the phase locked loop 100 and the phase interpolator 300, so that the low frequency to high frequency operation requirement can be satisfied. For example, the low frequency may be the lowest operating frequency of the phase locked loop 100. The output delay (delay) of the phase interpolator 300 can maintain good linearity and improve the performance of the port physical layer or the phase-locked loop 100 regardless of whether the phase-locked loop 100 is at a low operating frequency or a high operating frequency.
In the embodiment of the present application, the voltage driver 200 is used to isolate the phase interpolator 300 from the voltage source of the voltage controlled oscillator 130, so that the phase interpolator 300 does not interfere with the oscillator voltage of the voltage source of the voltage controlled oscillator 130 when operating, and the interference of the oscillator voltage is small, thereby improving the jitter (jitter) performance of the phase locked loop 100.
In this embodiment, the voltage output by the voltage driver 200 can better follow the conversion of the oscillator voltage power supply, so that the voltage driver 200 does not affect the linearity of the phase interpolator 300.
Further, the voltage driver 200 in the embodiment of the present application may be equivalent to a voltage-controlled voltage source, and may be implemented by an operational amplifier whose output stage is a source follower (source follower), and the connection of the operational amplifier may be a unity gain buffer, and the operational amplifier itself needs to have a higher gain and a certain bandwidth. The unity gain buffer as a negative feedback circuit can ensure stability by satisfying a certain phase margin (phase margin).
Further, by improving the linearity of the phase interpolator 300, jitter (jitter) introduced by Clock and Data Recovery (CDR) recovered Clock in a high speed interface circuit (SerDes) can be reduced.
Further, by improving the linearity of the phase interpolator 300, it is possible to improve the operating speed of the port physical layer in the field of customized port physical layers.
The embodiment of the present application further provides a chip, which includes the phase interpolator 300 system.
The phase interpolator 300 system in this embodiment is similar to the phase interpolator 300 system provided in the first embodiment, and other details of the phase interpolator 300 system in this embodiment may refer to the description in the first embodiment, and are not described herein again.
An embodiment of the present application further provides an electronic device, which may further include: and (3) a chip.
The chip may be a processor, and the electronic device may further include a memory, where some computer programs are stored in the memory, and the processor is configured to execute the computer programs to implement functions that the electronic device needs to execute.
The chip in this embodiment is similar to the chip provided in the first embodiment, and other details about the chip in this embodiment may refer to the description in the first embodiment, and are not described again here.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and all the changes or substitutions should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A phase interpolator system, comprising: a phase locked loop, a voltage driver and a phase interpolator;
the phase interpolator includes: a phase selector and phase interpolator core module;
the phase selector is connected with the phase interpolator core module;
the first output end of the phase-locked loop is connected with the voltage driver;
the output end of the voltage driver is connected with the input end of the phase selector and the input end of the phase interpolator core module and used for supplying power to the phase selector and the phase interpolator core module, and the voltage difference between a first voltage provided by the voltage driver for the phase interpolator core module and a second voltage output by the first output end of the phase-locked loop is smaller than a preset value;
the second output end of the phase-locked loop is connected with the phase selector and used for providing a phase clock.
2. The phase interpolator system of claim 1, wherein the voltage driver comprises: a first operational amplifier;
the first output end of the phase-locked loop is connected with the non-inverting input end of the first operational amplifier of the voltage driver;
and the inverting input end of the first operational amplifier and the output end of the first operational amplifier are used as the output end of the voltage driver and are connected with the input end of the phase selector and the input end of the phase interpolator core module.
3. The phase interpolator system of claim 1, wherein the voltage driver comprises: the second operational amplifier, the first capacitor and the first transistor;
the first output end of the phase-locked loop is connected with the non-inverting input end of the second operational amplifier;
the output end of the second operational amplifier is connected with the grid electrode of the first transistor;
one end of the first capacitor is connected between the output end of the second operational amplifier and the grid electrode of the first transistor;
the drain electrode of the first transistor is connected with a power supply, and the source electrode of the first transistor and the output end of the second operational amplifier are used as the output end of the voltage driver and are connected with the input end of the phase selector and the input end of the phase interpolator core module.
4. The phase interpolator system of claim 1, wherein the voltage driver comprises: a first resistor, a second capacitor and a second transistor;
a first output end of the phase-locked loop is connected with a first end of the first resistor;
one end of the second capacitor is connected between the second end of the first resistor and the grid electrode of the second transistor;
a second end of the first resistor is connected with a grid electrode of the second transistor;
and the drain electrode of the second transistor is connected with a power supply, and the source electrode of the second transistor is used as the output end of the voltage driver and is connected with the input end of the phase selector and the input end of the phase interpolator core module.
5. The phase interpolator system of claim 1, wherein the voltage driver comprises: a third operational amplifier and a miller compensation module;
the first output end of the phase-locked loop is connected with the non-inverting input end of a third operational amplifier of the voltage driver;
the miller compensation module is connected to an output end of the third operational amplifier, forms an output end of the voltage driver with an inverting input end of the third operational amplifier, and is connected to an input end of the phase selector and an input end of the phase interpolator core module.
6. The phase interpolator system of claim 5, wherein the third operational amplifier comprises: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;
a gate of the third transistor is used as an inverting input terminal of the third operational amplifier;
the grid electrode of the fourth transistor is used as the non-inverting input end of the third operational amplifier;
the drain electrode of the third transistor is connected with the drain electrode and the grid electrode of a fifth transistor, and the source electrode of the fifth transistor is grounded;
the drain electrode of the fourth transistor is connected with the drain electrode of the sixth transistor, and the source electrode of the sixth transistor is grounded;
the grid electrode of the fifth transistor is connected with the grid electrode of the sixth transistor;
the drain electrode of the seventh transistor is connected with the source electrode of the third transistor and the source electrode of the fourth transistor, and the source electrode of the seventh transistor is connected with a power supply;
a gate of the seventh transistor is connected to a gate and a drain of the tenth transistor;
a gate of the eighth transistor is connected to a gate of the seventh transistor;
a drain of the eighth transistor is connected to a drain of the ninth transistor;
the grid electrode of the ninth transistor is connected with the drain electrode of the fourth transistor;
a gate of the ninth transistor is connected to a drain of the sixth transistor;
a source of the ninth transistor is grounded;
one end of the Miller compensation module is connected with the grid electrode of the ninth transistor;
and the other end of the Miller compensation module is connected with the drain electrode of the ninth transistor.
7. The phase interpolator system of claim 6, wherein the Miller compensation module comprises: a second resistor and a third capacitor;
the second resistor is connected with the third capacitor in series;
one end of the second resistor is connected with the grid electrode of the ninth transistor; the other end of the second resistor is connected with one end of the third capacitor, and the other end of the third capacitor is connected with the drain electrode of the ninth transistor.
8. The phase interpolator system of any of claims 1-7, wherein the phase locked loop comprises: the phase detector, the loop filter, the voltage-controlled oscillator and the frequency divider;
the output end of the phase discriminator is connected with the input end of the loop filter;
the output end of the loop filter is connected with the input end of the voltage-controlled oscillator;
the first output end of the voltage-controlled oscillator is connected with the input end of the frequency divider;
the output end of the frequency divider is connected with the input end of the phase discriminator;
and the voltage output end of the voltage-controlled oscillator is connected with the voltage driver.
9. A chip comprising the phase interpolator system of any of claims 1-8.
10. An electronic device, comprising: the chip of claim 9.
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| CN1897583A (en) * | 2006-06-23 | 2007-01-17 | 西安邮电学院 | Multi-phase orthogonal clock generating circuit based on phase interpolation selection |
| CN107171779A (en) * | 2017-05-12 | 2017-09-15 | 无锡中微亿芯有限公司 | Binary code phase-interpolation circuit for CDR |
| CN111865272A (en) * | 2020-08-12 | 2020-10-30 | 灿芯半导体(苏州)有限公司 | Voltage type phase interpolator circuit |
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| US6642800B2 (en) * | 2002-04-04 | 2003-11-04 | Ati Technologies, Inc. | Spurious-free fractional-N frequency synthesizer with multi-phase network circuit |
| KR101727719B1 (en) * | 2010-10-11 | 2017-04-18 | 삼성전자주식회사 | Phase interpolator and semiconductor comprising the same and phase interpolating method thererof |
| KR102376738B1 (en) * | 2015-06-17 | 2022-03-23 | 한국전자통신연구원 | Phase locked loop for reducing fractional spur noise |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1897583A (en) * | 2006-06-23 | 2007-01-17 | 西安邮电学院 | Multi-phase orthogonal clock generating circuit based on phase interpolation selection |
| CN107171779A (en) * | 2017-05-12 | 2017-09-15 | 无锡中微亿芯有限公司 | Binary code phase-interpolation circuit for CDR |
| CN111865272A (en) * | 2020-08-12 | 2020-10-30 | 灿芯半导体(苏州)有限公司 | Voltage type phase interpolator circuit |
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