CN112331253B - Chip testing method, terminal and storage medium - Google Patents

Chip testing method, terminal and storage medium Download PDF

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Publication number
CN112331253B
CN112331253B CN202011188415.8A CN202011188415A CN112331253B CN 112331253 B CN112331253 B CN 112331253B CN 202011188415 A CN202011188415 A CN 202011188415A CN 112331253 B CN112331253 B CN 112331253B
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test
chip
address
read
data
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CN112331253A (en
Inventor
冯修圣
陈霖
刘敏
戴洋洋
陈宗廷
李斌
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Shenzhen Hongwang Microelectronics Co ltd
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Shenzhen Hongwang Microelectronics Co ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information

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Abstract

The application is applicable to the field of computers and provides a chip detection method, a terminal and a storage medium. The detection method of the chip comprises the following steps: acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested; writing the first test data into the chip to be tested according to the read-write mode and the test address; according to the read-write mode, reading first storage data pointed by the test address in the chip to be tested; comparing the first stored data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result. The embodiment of the application can improve the reliability of chip test.

Description

Chip testing method, terminal and storage medium
Technical Field
The present application relates to the field of computers, and in particular, to a method for testing a chip, a terminal, and a storage medium.
Background
The memory is a memory means for storing programs and various data information. While the testing algorithm for memory chips is the core of memory testing, the existing main testing method is March algorithm, which can detect multiple fault types, such as Stuck-at faults (SAF), transition faults (Transition faults, TF), coupling Faults (CF), and addressing faults (Adress decoder faults, AF).
However, the March algorithm has low reliability.
Disclosure of Invention
The embodiment of the application provides a chip testing method, a terminal and a storage medium, which can solve the problem of lower reliability of the conventional chip testing method.
An embodiment of the present application provides a method for detecting a chip, including:
acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested;
writing the first test data into the chip to be tested according to the read-write mode and the test address;
according to the read-write mode, reading first storage data pointed by the test address in the chip to be tested;
comparing the first stored data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result.
A device for detecting a chip provided in a second aspect of the embodiment of the present application includes:
the device comprises an acquisition unit, a data storage unit and a data storage unit, wherein the acquisition unit is used for acquiring first test data, a test address and a read-write mode, and the test address is a data storage address of a chip to be tested;
the writing unit is used for writing the first test data into the chip to be tested according to the read-write mode and the test address;
The reading unit is used for reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode;
and the test unit is used for comparing the first stored data with the first test data and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result.
A third aspect of the embodiments of the present application provides a terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the above method when executing the computer program.
A fourth aspect of the embodiments of the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the above method.
A fifth aspect of the embodiments of the present application provides a computer program product for enabling a terminal to carry out the steps of the method when the computer program product is run on the terminal.
In the embodiment of the application, firstly, a chip to be tested, first test data, a test address and a read-write mode are obtained. And then, according to the read-write mode, writing the first test data into the test address. And then, according to a read-write mode, reading the first storage data stored in the test address. Comparing the first stored data with the first test data, and determining whether the read-write of the chip is abnormal according to the comparison result. The embodiment of the application considers three different dimensions of test data, test addresses and read-write modes to test the read-write capability of the chip. Compared with the March algorithm, the method can test faults existing in the reading and writing process in the actual application process. Therefore, the embodiment of the application can detect faults which cannot be detected by the March algorithm, and improves the reliability of chip testing.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic implementation flow chart of a method for detecting a chip according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a first implementation flow for acquiring first test data according to an embodiment of the present application;
FIG. 3 is a schematic diagram of an implementation flow chart of testing using data of different capacities according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a second implementation flow for acquiring first test data according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a parallel read-write implementation flow provided in an embodiment of the present application;
FIG. 6 is a schematic diagram of a chip test flow according to an embodiment of the present application;
fig. 7 is a schematic structural diagram of a detection device for a chip according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a terminal according to an embodiment of the present application.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
The memory is a memory means for storing programs and various data information. The test algorithm of the memory chip is the core of the memory test, and the existing main test mode is the March algorithm. The basic principle of the algorithm is that a finite state machine is utilized to perform read-write operation on all addresses one by one, and an algorithm instruction is simpler and only comprises 0, 1 and a changed instruction. In general, the algorithm firstly writes "0" to each memory cell, then reads "0" to each memory cell and "1" to each memory cell, and finally reads "1" to determine whether the memory cells are all "1". Then, each memory cell can be read by "1" and written by "0", and finally "0" is read, so as to judge whether all the memory cells are stored as "0".
The March algorithm is capable of detecting multiple fault types, such as Stuck-at faults (SAF), transition faults (Transition faults, TF), coupling Faults (CF), and addressing faults (Adress decoder faults, AF).
The fixed fault means that the value of one memory cell is fixed at 0 or fixed at 1 and is not changed. A transition failure refers to a failure of one storage unit in a memory array to make a transition from 0 to 1 or from 1 to 0. A coupling failure refers to a short circuit and coupling between memory cells, causing a change to one memory cell necessarily causes a change in the state of the other memory cell. Addressing failure refers to the inability to correctly find the corresponding address. These faults are all the most common types of faults.
However, the March algorithm has low reliability. Therefore, the application provides a chip testing method, which can detect the fault type which is difficult to detect by the March algorithm and improve the reliability of chip detection.
In order to illustrate the technical scheme of the application, the following description is made by specific examples.
Fig. 1 shows a schematic implementation flow chart of a method for testing a chip according to an embodiment of the present application, where the method may be applied to a terminal, and may be applicable to a situation where reliability of chip detection needs to be improved.
Specifically, the method for detecting a chip may include the following steps S101 to S104.
Step S101, first test data, test addresses and read-write modes are obtained.
The test address is a data storage address of the chip to be tested. The chip to be tested refers to a memory chip which needs to be tested.
Generally, before the memory leaves the factory, the memory is provided for testing personnel to test, so that the memory flowing to the market is not easy to fail, and the rights and interests of consumers are guaranteed. In other scenarios, a user of the memory may also provide the memory to a tester for testing in order to know or confirm whether the memory's chip is functioning properly. Therefore, when the tester performs chip test on the memory, the memory chip in the memory is the chip to be tested.
In the embodiment of the application, before the test, the terminal can be connected with the chip to be tested, so that the terminal can perform read-write operation on the chip to be tested to complete the test of the chip to be tested. The connection establishment mode can be selected by a tester according to actual conditions. For example, the memory carrying the chip to be tested may be inserted by an administrator onto the printed circuit board (Printed Circuit Board, PCB) of the terminal.
The first test data refers to data written into the memory cells of the chip to be tested during the test process. The data can be provided directly by a tester with abundant test experience, or can be test data calculated by a certain random algorithm.
The test address refers to an address corresponding to a memory cell to which the first test data is to be written in a test process. Also, the address may be provided directly by a tester with a rich test experience, or may be test data calculated by a certain random algorithm.
The read/write method is a write method used for writing the first test data into the memory cell corresponding to the test address or a read method used for reading the data from the memory cell corresponding to the test address.
In the embodiment of the application, the terminal can test the chip to be tested by considering three aspects of the first test data, the test address and the read-write mode so as to detect the fault types caused by different test data, test address or read-write mode.
Step S102, according to the read-write mode and the test address, writing the first test data into the chip to be tested.
In the embodiment of the application, after the first test data, the test address and the read-write mode are acquired, the terminal can generate a plurality of commands for instructing the terminal to perform the write operation, and then execute the generated commands so as to write the first test data into the storage unit pointed by the test address according to the read-write mode.
Step S103, according to the read-write mode, reading the first storage data pointed by the test address in the chip to be tested.
The first storage data refers to data read out from a storage unit pointed to by the test address.
In an embodiment of the present application, normally, after the first test data is written to the test address, the first storage data stored in the storage unit corresponding to the test address is identical to the first test data. Therefore, the first storage data stored in the test address can be read according to the read-write mode so as to judge whether the read-write of the chip is abnormal or not.
In the same way, the terminal can generate a plurality of commands for indicating the terminal to perform data reading operation according to the test address and the read-write mode, and then execute the generated commands to read the first storage data stored in the storage unit pointed by the test address according to the read-write mode.
Step S104, comparing the first stored data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result.
In an embodiment of the present application, after the first storage data is read, the first storage data and the first test data may be compared. If the first storage data and the first test data are different, it is indicated that a certain abnormality exists in the storage chip during the read-write process, and the abnormality may be caused by at least one of the read-write mode, the first test data and the test address.
If the first storage data and the first test data are the same, the storage chip is indicated to have no abnormality in the read-write process. Therefore, it can be confirmed that the memory chip performs normally at least when the first test data is read from or written to the memory cell to which the test address is directed by using the read/write method.
In some embodiments of the present application, a plurality of first test data, a plurality of test addresses and a plurality of read-write modes are obtained, and according to different read-write modes, different first test data are used for performing read-write test on different test addresses, so as to ensure the reliability of chip test.
In the embodiment of the application, firstly, a chip to be tested, first test data, a test address and a read-write mode are obtained. And then, according to the read-write mode, writing the first test data into the test address. And then, according to a read-write mode, reading the first storage data stored in the test address. Comparing the first stored data with the first test data, and determining whether the read-write of the chip is abnormal according to the comparison result. The embodiment of the application considers three different dimensions of test data, test addresses and read-write modes to test the read-write capability of the chip. Compared with the March algorithm, the method can test faults existing in the reading and writing process in the actual application process. Therefore, the embodiment of the application can detect faults which cannot be detected by the March algorithm, such as faults in a read-write mode, faults of special test data and the like, and can improve the reliability of chip test.
In practical application, the March algorithm reads and writes all the memory cells, but the chip may only use part of the memory cells in the practical use process, so that the March algorithm only detects the states of all the memory cells in the practical use process, and the states of the chip in the practical use process cannot be completely simulated.
Based on this, in some embodiments of the present application, a plurality of different sizes of first test data may be determined according to the chip capacity and sequentially tested.
Specifically, in some embodiments of the present application, as shown in fig. 2, the acquiring the first test data may include: step S201 to step S203.
Step S201, obtaining the storage total capacity of the chip to be tested.
The total storage capacity refers to the total storage capacity of the chip to be tested, namely the maximum data amount which can be stored by the chip to be tested.
In some embodiments of the present application, the terminal may determine the total storage capacity according to the specification of the chip to be tested.
Specifically, in some embodiments of the present application, the terminal may read the specification of the chip after establishing a connection with the chip to be tested. In practical applications, the chip will be posted with an identification code or an instruction bar carrying chip information after the chip is produced, so in other embodiments of the present application, the terminal may also obtain the specification of the chip by reading the identification code or acquiring an image of the instruction bar.
After the specification of the chip is obtained, the terminal may determine the total storage capacity according to a standard provided by the solid state technology association (JEDEC), or may determine the total storage capacity according to a specification provided by a manufacturer that supplies the chip to be tested.
Among them, the solid state technology association is the leading standards body in the microelectronics industry. Typically, in a solid state technology association standard or vendor specification, a specification corresponds to a total storage capacity. Therefore, the terminal can determine the total storage capacity according to the specification of the chip.
Step S202, determining a plurality of test data volumes according to the total storage capacity.
The test data volume refers to the data size of the first test data.
In some embodiments of the present application, the total storage capacity may be multiplied by a plurality of preset ratios to yield a plurality of test data volumes. For example, 1/4, 1/2, 3/4 of the total storage capacity is determined as one test data volume, respectively.
In other embodiments of the present application, a plurality of preset capacities may be predetermined, and then a preset capacity less than or equal to the total storage capacity is selected from the plurality of preset capacities according to the total storage capacity, and each of the selected preset capacities is determined as a test data volume.
In step S203, a plurality of first test data are acquired, wherein the volumes of the first test data correspond to the volumes of the test data one by one.
In an embodiment of the present application, a plurality of first test data may be determined according to the test data volumes, and the volume (i.e., the data size) of each first test data is the same as one test data volume, respectively. The specific data content of the first test data can be directly provided by a tester with abundant test experience according to the volume of the test data, or can be the test data calculated by a certain random algorithm. The method can also be used for intercepting high-capacity test data according to the volume of the test data to obtain first test data.
For example, if the total memory capacity of one chip to be tested is 8Gb, 1/4, 1/2, and 3/4 of the total memory capacity may be determined as one test data volume, respectively, according to the total memory capacity, and thus, one first test data of 2Gb, one first test data of 4Gb, and one first test data of 6Gb may be acquired, respectively. On this basis, a predetermined preset capacity, which may be a smaller capacity such as a capacity of 4MB, may also be obtained. Thus, finally, one first test data of 4MB, one first test data of 2Gb, one first test data of 4Gb, and one first test data of 6Gb can be obtained. The chip may be tested at this time using these first test data.
Specifically, as shown in fig. 3, the above-mentioned test of the chip may include the following steps S301 to S307.
Step S301, screening a second test data from the plurality of first test data.
The second test data is the test data which needs to be written into the chip currently.
In some embodiments of the present application, the specific manner in which one second test data is screened from the first test data is not limited. For example, any one of the first test data may be selected as the second test data, or the plurality of first test data may be sequentially identified as the second test data according to the order of the capacity from the smaller to the larger.
Step S302, a test head address is obtained.
The test head address refers to a starting position of writing the second test data. The test head address can be selected according to actual needs. For example, the head address of the whole chip can be used as a test head address, and a test head address preset by an administrator can also be obtained.
Step S303, determining the test end address according to the volume of the second test data and the test head address.
The test end address refers to the end position where the writing of the second test data is completed. After the data size and the test head address of the second test data are obtained, according to the test head address, the address which is written after the writing operation of the second test data is performed can be calculated.
Specifically, in some embodiments of the present application, the storage capacity of each memory cell in the chip to be tested, the number of memory blocks (banks), the number of rows, and the number of columns of the chip to be tested may be obtained, and the test end address may be determined according to the volume of the second test data, the test head address, and the storage capacity.
In general, a chip to be tested may be divided into a plurality of memory blocks, each memory block containing a number of rows and a number of columns. In each memory block, one column of each row corresponds to one memory cell, and the memory capacity of each memory cell is generally the same.
The storage capacity, the number of storage blocks, the number of rows and the number of columns of the storage unit are generally already determined when leaving the factory, and the corresponding acquisition mode may refer to the acquisition mode of the chip specification in step S201.
For example, a 4MB second test data is currently required to be tested. If the row address line of the chip to be tested is 15, the column address line is 10, and the memory block address line is 3, i.e. the number of rows is 2 15 Bars, column number 2 10 Stripe, number of memory blocks is 2 3 And each. The capacity of each memory cell is 32 bits. If the calculation is performed with the column as a restriction, the second test data of 4MB requires 4 mb=4096 k= 4194304 byte=33554432 bit,33554432 bit/32 bit/1024 column=1024 rows. That is, the second test data of 4MB requires 1024 rows by 1024 columns of memory cells, and if the first address is memory block 0, row 0, and column 0, the last address is memory block 0, row 1023, and column 1023.
Step S304, writing the second test data into the chip to be tested according to the read-write mode, the test head address and the test end address.
In some embodiments of the present application, after the read-write mode, the test head address and the test end address are obtained, the terminal may generate a corresponding command line according to the read-write mode, the test head address and the test end address, and execute the command line by the terminal, so as to completely write the second test data from the storage unit pointed by the test head address to the storage unit pointed by the test end address according to the read-write mode.
Step S305, according to the read-write mode, the first storage data pointed by the test address in the chip to be tested is read.
Step S306, comparing the first stored data with the second test data, and determining whether the read-write of the chip is abnormal according to the comparison result.
The step S305 and the step S306 may refer to the descriptions of the step S103 and the step S104, which are not described in detail herein.
Step S307, if the read-write of the chip is not abnormal, the operation of screening one second test data from the plurality of first test data is returned to be executed until all the first test data are written into the chip to be tested.
The second test data screened should be the data which is not tested in the first test data.
It should be noted that, after the new second test data is screened out, the test head address may be adjusted according to the actual situation. That is, when each second test data is tested, the corresponding test head addresses may be different. For example, a predetermined test head address may be associated with each second test data. It is also possible that each test starts from the head address of the entire memory chip. Alternatively, the first address of each test may be identified as the next address of the last test.
According to the embodiment of the application, through repeated cyclic tests, the data volume corresponding to the data used in each test is equal to part or all of the total storage capacity, and the process that the chip is continuously started from part to all in the use process is simulated in practice, so that the actual situation of the chip in the actual use process is more attached. Compared with the March algorithm, the method for testing the memory cells directly writes and reads all the memory cells, and the method for testing the memory cells can test possible faults in the process of partial reading and writing.
In some embodiments of the present application, the memory address of the chip to be tested includes: a block address, a row address and a column address are stored. A common test mode, such as a March algorithm, is only applicable to writing and reading in a read-write mode, namely a conventional writing mode is to select a storage block, select one row again, write all columns in the row completely, and write the next column.
However, in the actual application process, the reading and writing of the chip are generally completed by executing the command, and the corresponding command timing is different in different reading and writing modes. For example, before a memory block is selected, an Active command needs to be executed to activate the memory block. Before switching rows, there will be a precharge command to close the current row and open the new row. Therefore, different writing modes change the command timing. In practical applications, various read-write modes can occur, so that in this case, various write modes are added for testing in the embodiment of the application.
Specifically, in some embodiments of the present application, the number of the read-write modes is greater than 1, and writing the first test data to the chip to be tested according to the read-write mode and the test address may include: and writing the first test data into the chip to be tested for multiple times according to each read-write mode and the test address.
The read-write modes adopted by the chip to be tested are different in each writing. That is, in some embodiments of the present application, multiple read/write modes may be used to perform multiple tests to test the performance of the chip in different read/write modes.
In some embodiments of the present application, the data storage address of the chip to be tested includes: the memory block address, the row address and the column address are stored, each read-write mode comprises a read-write sequence of the memory block address, the row address and the column address, and the read-write sequence of each read-write mode is different. Thus, in some embodiments of the present application, the first test data may be written to the test address in the chip to be tested according to the read-write sequence included in the single read-write mode.
Specifically, the plurality of read/write methods may include at least two of the following read/write methods.
The first read-write mode is memory block-row-column. The specific operation is that a memory block is selected, a row is selected, all columns of the row are written, and then, after the writing of all columns of the row is completed, the row is changed. Until all rows of this memory block have been written, the memory block is finally replaced until all address writes are completed. The read operation is the same as the write operation.
The second read-write mode is memory block-column-row. The specific operation is that a memory block is selected, a column is selected, all rows in the column are written in, then the column is replaced, and finally the memory block is replaced until all addresses are written in. The read operation is the same as the write operation.
The third read-write mode is row-memory block-column, one row is selected first (the row of all memory blocks), then one memory block is selected, all columns of the memory block are written in, the memory block is replaced after the column is written in, and the row is replaced until the memory block is written in. And looping until all address writes are completed. The read operation is the same as the write operation.
The fourth read-write mode is column-memory block-row. A column (the column of all memory blocks) is selected firstly, then a memory block is selected, all rows of the memory block are read and written, the memory block is replaced after the rows are written, and the column is replaced until the memory blocks are written. And looping until all address writes are completed. The read operation is the same as the write operation.
The fifth read-write mode is row-column-memory block. One row (row of all memory blocks) is selected, all columns (columns of all memory blocks) of the row are selected, and finally one memory block is selected for writing. And looping until all address writes are completed. The read operation is the same as the write operation.
The sixth read/write method is to select a column (columns of all memory blocks) from a column to a row, select all rows (rows of all memory blocks) from the row, and select one memory block to write. And looping until all address writes are completed. The read operation is the same as the write operation.
In order to ensure the comprehensiveness of the test, in some embodiments of the present application, six read-write modes are acquired simultaneously, and the six read modes are tested respectively.
In other embodiments of the present application, after a plurality of read-write modes are acquired, a plurality of write tests may be performed according to the plurality of read-write modes, where each read-write mode, the first test data, and the test address of each write test are different.
And by utilizing a plurality of read-write modes, one read operation can be performed after each write, and the storage data stored in the storage unit pointed by the corresponding test address is read. Then, comparing the stored data with the first test data, if the stored data is different from the first test data, determining that the read-write of the chip to be tested is abnormal, and indicating that the chip to be tested cannot apply the current read-write mode.
In the embodiment of the application, through testing different read-write modes, the read-write modes used in each test are different, so that different write modes possibly occurring in the use process of the chip are simulated, and the actual situation of the chip in the actual use process is more attached. Compared with a March algorithm or other testing algorithms, the method provided by the application is only applicable to one reading and writing mode, and can test faults caused by different command time sequences corresponding to different reading and writing modes in the process of reading and writing by using different reading and writing modes.
In order to more comprehensively simulate the running condition of the chip in the actual use process, in other embodiments of the present application, a preset first random algorithm may be further obtained, and a test address may be generated according to the first random algorithm. Then, a read-write test is performed according to the test address.
Since the detection method of the March algorithm is generally sequential reading and writing, failure in simulation of random address reading and writing cannot be detected. However, in practical applications, the chip may start reading from a specific location. Therefore, the embodiment of the application can read and write a plurality of random addresses by generating the plurality of random addresses, detect whether the chip fails in the application of the random addresses, and make up for the random address failure which cannot be detected in the conventional test.
The first random algorithm is used for generating a random address and can be selected by an administrator according to practical situations, for example, the first random algorithm can be used for generating three random numbers, and each random number corresponds to a storage block, a row and a column.
The test of the random address can test whether the chip has faults in the application of the random address, and the test of the random data can test whether the chip has faults when the chip reads and writes the random data. Thus, in some embodiments of the application, a test of random data may be performed. Specifically, as shown in fig. 4, it may include: step S401 to step S404.
Step S401, the storage capacity of each storage unit in the chip to be tested is obtained.
The storage capacity of the storage unit is generally determined at the time of shipment, and the corresponding acquisition mode may refer to the acquisition mode of the chip specification in step S201.
Step S402, a preset second random algorithm is obtained.
Step S403, generating a plurality of random data according to the storage capacity and the second random algorithm, wherein the size of each random data is equal to the storage capacity.
The second random algorithm is used for generating random data, and can be selected by the actual situation of an administrator.
In some embodiments of the present application, the terminal may directly generate a number of numbers corresponding to the storage capacity according to the storage capacity of a single storage unit by using the second random algorithm, and concatenate the numbers to obtain random data. For example, if the storage capacity of a single storage unit is 32Bit, the second random algorithm may generate 32 numbers, each number is one of 0 or 1, and splicing the 32 numbers may obtain random data.
In other embodiments of the present application, the terminal may directly generate data with a capacity greater than the storage capacity using a second random algorithm. Then, the terminal can intercept the data according to the storage capacity to obtain random data with the size equal to the storage capacity.
It should be noted that, the present application can generate a plurality of random data and test each random data to ensure the comprehensiveness of the test.
Step S404, determining first test data according to the plurality of random data.
Based on the above description, after a plurality of random data are obtained, each random data may be determined as one first test data. And then, respectively performing read-write test on each first test data, and determining whether the chip has abnormality on reading and writing of certain random data or not when reading and writing.
Since the detection mode of the March algorithm is generally direct reading and writing of 0 or 1, that is, "00000000000000000000000000000000" (32 0 s) or "11111111111111111111111111111111" (32 1 s) is read and written if one memory cell can store 32 bits of data. However, in practical application, if both 0 and 1 in the 32bit data exist, it is considered whether the proportion of 0 and 1 affects the working performance of the chip. In the embodiment of the present application, therefore, the random data is randomly composed to have the same size as the storage capacity by the read-write detection of the random data, and thus, the first test data may be one data including a plurality of 0 s and a plurality of 1 s. Through various arrangements of 0 and 1, more data presentation is added, which is not available for normal definition data, and faults which cannot be detected by a detection mode of a March algorithm and the like can be detected.
In normal operation of the chip, the chip may read data while storing the data. Thus, in some embodiments of the present application, the parallel read-write test is continued. Specifically, in some embodiments of the present application, the test addresses include a read test address and a write test address.
The writing test address refers to a position where the first test data is required to be written in the test process; the read test address refers to a position where data needs to be read in parallel during the test process.
Both the read test address and the write test address may be selected by an administrator. It should be noted that the read test address and the write test address are generally different, but may cross.
If the memory block, row, column corresponding to the write test address is (0, 0) through (2, 2), the read test address cannot be (0, 0) to (2, 2), but may be (1, 1) to (3, 3).
As shown in fig. 5, the writing of the first test data to the test address according to the read/write method further includes: step S501 to step S502.
Step S501, according to the read-write mode and the write test address, writing the first test data into the chip to be tested.
Step S502, in the process of writing the first test data into the chip to be tested, reading the second storage data pointed by the read test address in the chip to be tested according to the read-write mode.
The second storage data refers to data stored in a storage unit pointed by the read test address.
Correspondingly, the reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode may include: and reading the first storage data pointed by the write test address in the chip to be tested according to the read-write mode.
After the first test data is written into the write test address, the first storage data stored in the test address can be read according to a read-write mode, and the first storage data and the first test data are compared. If the first storage data is the same as the first test data, the chip can read and write in parallel, namely, the second storage data is read in the process of writing the first test data, and the result of the writing operation is not influenced.
For example, while writing to the memory cell corresponding to the test address of the portion a, reading to the memory cell corresponding to the test address of the portion B is performed. If the first storage data in the A part storage unit is the same as the first test data after the writing operation is completed, the chip can be used for simultaneously performing the reading and writing operation.
In the embodiment of the application, the data of the read test address is read according to the read-write mode in the process of writing the first test data into the write test address, so that the parallel read-write test is realized.
It should be noted that in some embodiments of the present application, multiple test modes may be combined.
In order to ensure the comprehensiveness and reliability of the chip test, as shown in fig. 6, in some embodiments of the present application, after the test is performed using the March algorithm, the test of different capacity data, the test of different read/write modes, the random address test, the random data test, and the parallel read/write test may be performed respectively. If any test fails, the abnormality of the reading and writing of the chip can be confirmed. If all tests are successful, it can be confirmed that the chip has no abnormality.
It should be noted that the sequence of the above test may be exchanged, that is, the parallel read-write test may be performed first, then the test of the March algorithm may be performed.
In the embodiment of the application, a plurality of test modes are used for combined test, so that the read-write capability of the chip can be more comprehensively known, and the chip can be conveniently marked, recovered and reworked by a tester.
It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present application is not limited by the order of acts described, as some steps may occur in other orders in accordance with the application.
Fig. 7 is a schematic structural diagram of a chip detection device 700 according to an embodiment of the present application, where the chip detection device 700 is configured on a terminal. The chip detection device 700 may include:
an obtaining unit 701, configured to obtain first test data, a test address, and a read-write manner, where the test address is a data storage address of a chip to be tested;
a writing unit 702, configured to write the first test data to the chip to be tested according to the read-write mode and the test address;
A reading unit 703, configured to read, according to the read-write manner, first storage data pointed by the test address in the chip to be tested;
and the test unit 704 is configured to compare the first stored data with the first test data, and determine whether the read-write of the chip to be tested is abnormal according to the comparison result.
In some embodiments of the present application, the above-mentioned obtaining unit 701 is further specifically configured to: acquiring the total storage capacity of the chip to be tested; determining a plurality of test data volumes based on the total storage capacity; and acquiring a plurality of first test data, wherein the volumes of the first test data are in one-to-one correspondence with the volumes of the test data.
In some embodiments of the present application, the writing unit 702 is further specifically configured to: screening a second test data from the plurality of first test data; acquiring a test head address; determining a test end address according to the volume of the second test data and the test head address; and writing the second test data into the chip to be tested according to the read-write mode, the test head address and the test tail address. Correspondingly, the detecting device 700 of the chip further includes a circulating unit, configured to: and if the reading and writing of the chip are not abnormal, returning to execute the operation of screening one second test data from the plurality of first test data until all the first test data are written into the chip to be tested.
In some embodiments of the present application, the writing unit 702 is further specifically configured to: acquiring the storage capacity of each storage unit in the chip to be tested, and the number of storage blocks, the number of rows and the number of columns of the chip to be tested; and determining a test end address according to the volume of the second test data, the test head address and the storage capacity.
In some embodiments of the present application, the number of the read/write modes is greater than 1, and the writing unit 702 further includes: and writing the first test data into the chip to be tested for multiple times according to the read-write modes and the test addresses, wherein the read-write modes adopted by the chip to be tested are different in each writing.
In some embodiments of the present application, the data storage address of the chip to be tested includes: storing a block address, a row address and a column address; each reading and writing mode comprises a reading and writing sequence of a storage block address, a row address and a column address, and the reading and writing sequences of each reading and writing mode are different; correspondingly, the writing unit 702 is further specifically configured to: and writing the first test data into the test address in the chip to be tested according to the read-write sequence contained in the read-write mode.
In some embodiments of the present application, the above-mentioned obtaining unit 701 is further specifically configured to: and acquiring a preset first random algorithm, and generating the test address according to the first random algorithm.
In some embodiments of the present application, the above-mentioned obtaining unit 701 is further specifically configured to: acquiring the storage capacity of each storage unit in the chip to be tested; acquiring a preset second random algorithm; generating a plurality of random data according to the storage capacity and the second random algorithm, wherein the size of each random data is equal to the storage capacity; and determining the first test data according to the random data.
In some embodiments of the present application, the test address includes a read test address and a write test address; the writing unit 702 is specifically further configured to: writing the first test data into the chip to be tested according to the read-write mode and the write test address; and in the process of writing the first test data into the chip to be tested, reading second storage data pointed by the read test address in the chip to be tested according to the read-write mode. Correspondingly, the reading unit 703 further includes: and reading the first storage data pointed by the writing test address in the chip to be tested according to the reading and writing mode.
It should be noted that, for convenience and brevity of description, the specific working process of the above-mentioned detection device 700 of the chip may refer to the corresponding process of the method described in fig. 1 to 6, and will not be described herein again.
Fig. 8 is a schematic diagram of a terminal according to an embodiment of the present application. The terminal 8 may include: a processor 80, a memory 81 and a computer program 82, e.g. a detection program of a chip, stored in the memory 81 and executable on the processor 80. The processor 80, when executing the computer program 82, implements the steps in the above-described detection method embodiments of the respective chips, such as steps S101 to S104 shown in fig. 1. Alternatively, the processor 80 may perform the functions of the modules/units of the apparatus embodiments described above, such as the units 701 to 704 shown in fig. 7, when executing the computer program 82.
The computer program may be divided into one or more modules/units which are stored in the memory 81 and executed by the processor 80 to complete the present application. The one or more modules/units may be a series of computer program instruction segments capable of performing the specified functions, which instruction segments describe the execution of the computer program in the terminal.
For example, the computer program may be divided into an acquisition unit, a writing unit, a reading unit and a testing unit. The specific functions of each unit are as follows:
the device comprises an acquisition unit, a data storage unit and a data storage unit, wherein the acquisition unit is used for acquiring first test data, a test address and a read-write mode, and the test address is a data storage address of a chip to be tested;
the writing unit is used for writing the first test data into the chip to be tested according to the read-write mode and the test address;
the reading unit is used for reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode;
and the test unit is used for comparing the first stored data with the first test data and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result.
The terminal may include, but is not limited to, a processor 80, a memory 81. It will be appreciated by those skilled in the art that fig. 8 is merely an example of a terminal and is not intended to be limiting, and that more or fewer components than shown may be included, or certain components may be combined, or different components may be included, for example, the terminal may also include input and output devices, network access devices, buses, etc.
The processor 80 may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 81 may be an internal storage unit of the terminal, such as a hard disk or a memory of the terminal. The memory 81 may also be an external storage device of the terminal, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the terminal. Further, the memory 81 may also include both an internal storage unit and an external storage device of the terminal. The memory 81 is used for storing the computer program and other programs and data required by the terminal. The memory 81 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus/terminal and method may be implemented in other manners. For example, the apparatus/terminal embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present application may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, where the computer program may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the computer program may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable medium contains content that can be appropriately scaled according to the requirements of jurisdictions in which such content is subject to legislation and patent practice, such as in certain jurisdictions in which such content is subject to legislation and patent practice, the computer readable medium does not include electrical carrier signals and telecommunication signals.
The above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application.

Claims (10)

1. A method for testing a chip, the method comprising:
acquiring first test data, a test address and a read-write mode, wherein the test address is a data storage address of a chip to be tested;
writing the first test data into the chip to be tested according to the read-write mode and the test address;
according to the read-write mode, reading first storage data pointed by the test address in the chip to be tested;
comparing the first stored data with the first test data, and determining whether the read-write of the chip to be tested is abnormal or not according to the comparison result;
The number of the read-write modes is greater than 1, and the data storage address of the chip to be tested comprises: storing a block address, a row address and a column address; each read-write mode comprises a read-write sequence of a storage block address, a row address and a column address, and the read-write sequence and the corresponding command sequence contained in each read-write mode are different;
the writing the first test data to the chip to be tested according to the read-write mode and the test address includes: and writing the first test data into the chip to be tested for multiple times according to the read-write modes and the test addresses, wherein the read-write modes adopted by the chip to be tested are different in each writing.
2. The method for testing a chip according to claim 1, wherein the acquiring the first test data includes:
acquiring the total storage capacity of the chip to be tested;
determining a plurality of test data volumes based on the total storage capacity;
and acquiring a plurality of first test data, wherein the volumes of the first test data are in one-to-one correspondence with the volumes of the test data.
3. The method for testing a chip according to claim 2, wherein writing the first test data to the chip to be tested according to the read-write method and the test address comprises:
Screening a second test data from the plurality of first test data;
acquiring a test head address;
determining a test end address according to the volume of the second test data and the test head address;
writing the second test data into the chip to be tested according to the read-write mode, the test head address and the test tail address;
correspondingly, the test method of the chip further comprises the following steps:
and if the reading and writing of the chip are not abnormal, returning to execute the operation of screening one second test data from the plurality of first test data until all the first test data are written into the chip to be tested.
4. The method of testing a chip of claim 3, wherein said determining a test end address based on a data size of said second test data and said test head address comprises:
acquiring the storage capacity of each storage unit in the chip to be tested, and the number of storage blocks, the number of rows and the number of columns of the chip to be tested;
and determining a test end address according to the volume of the second test data, the test head address and the storage capacity.
5. The method for testing a chip according to claim 1, wherein writing the first test data to the chip to be tested a plurality of times according to the single read-write manner and the test address, comprises:
and writing the first test data into the test address in the chip to be tested according to the read-write sequence contained in the read-write mode.
6. The method for testing a chip according to claim 1, wherein the acquiring the test address includes:
and acquiring a preset first random algorithm, and generating the test address according to the first random algorithm.
7. The method for testing a chip according to claim 1, wherein the acquiring the first test data includes:
acquiring the storage capacity of each storage unit in the chip to be tested;
acquiring a preset second random algorithm;
generating a plurality of random data according to the storage capacity and the second random algorithm, wherein the size of each random data is equal to the storage capacity;
and determining the first test data according to the random data.
8. The method of testing a chip of claim 1, wherein the test addresses comprise a read test address and a write test address;
The writing the first test data to the chip to be tested according to the read-write mode and the test address includes:
writing the first test data into the chip to be tested according to the read-write mode and the write test address;
in the process of writing the first test data into the chip to be tested, reading second storage data pointed by the read test address in the chip to be tested according to the read-write mode;
the reading the first storage data pointed by the test address in the chip to be tested according to the read-write mode includes:
and reading the first storage data pointed by the writing test address in the chip to be tested according to the reading and writing mode.
9. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of claims 1 to 8 when the computer program is executed.
10. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the method according to any one of claims 1 to 8.
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