CN112102875B - LPDDR test method, device, readable storage medium and electronic equipment - Google Patents
LPDDR test method, device, readable storage medium and electronic equipment Download PDFInfo
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Abstract
The invention discloses an LPDDR test method, a device, a readable storage medium and an electronic device, wherein the LPDDR to be tested is subjected to half-and-half read-write access operation based on a first preset read-write unit, and then is subjected to half-and-half read-write access operation based on a second preset read-write unit, the first preset read-write unit and the second preset read-write unit are different, because the half-and-half read-write access of the preset read-write unit is to simultaneously read and write from the middle position of the preset read-write unit to two ends, and the half-and-half read-write access of the different preset read-write units is carried out twice, a read-write environment suitable for the occurrence of proximity mode sensitive faults can be constructed, compared with the existing sequential read-write test mode, the proximity mode sensitive faults can be hit more easily, single-cell and multi-cell faults can be detected, the proximity mode sensitive faults can be easily detected, and the fault coverage rate during the LPDDR test is improved.
Description
Technical Field
The present disclosure relates to memory testing, and more particularly, to a method and apparatus for testing LPDDR, a readable storage medium, and an electronic device.
Background
The basic memory cell of LPDDR (Low Power Double Data Rate SDRAM, low Power consumption memory) is a cell, and a computer and an embedded system perform Data storage and read/write by writing a high level or a Low level in the cell. However, due to the influence of the manufacturing process, the memory cell may cause data storage failure during reading and writing.
The storage failures are divided into single-cell failures and multi-cell failures. The single cell Fault mainly includes a fixed Fault (SF) and a Transition Fault (TF). The detection of these two faults is generally performed by writing 1 to the unit under test, then writing 0 and then reading 0, and correspondingly, writing 0, then writing 1 and then reading 1. Typical failures of multiple cells are: bridging Fault (BF) and Coupling Fault (CF). For these two faults, the conventional detection method is to perform writing and reading in ascending order and then writing and reading in descending order on the storage unit in the address space to detect whether there is a data error.
In addition to conventional single-cell and multi-cell Faults, the neighbor mode Sensitive Faults (NPSFs) are a type of fault that is more concealed and difficult to directly fire. The fundamental reason is that a cell with a process defect is affected by the high/low level states of the surrounding cells, and the data recorded in the failed cell is changed when the surrounding cells are at a specific combination of high and low levels. The existing conventional test case belongs to sequential test, namely, addresses are read and written from high to low or from low to high in sequence, so that the faults are difficult to hit.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: an LPDDR test method, an apparatus, a readable storage medium and an electronic device are provided, which can improve fault coverage when testing LDPPR.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
an LPDDR test method comprising the steps of:
simultaneously writing data into the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
simultaneously writing data into the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
and obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an LPDDR test device comprising:
the first data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each first preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
the second data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each second preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
and the test module is used for obtaining the test result of the LPDDR to be tested according to the first comparison result and the second comparison result.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
a computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of the LPDDR test method described above.
In order to solve the technical problem, the invention adopts another technical scheme as follows:
an electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the LPDDR test method when executing the computer program.
The invention has the beneficial effects that: the method comprises the steps that half-and-half read-write access operation based on a first preset read-write unit is carried out on the LPDDR to be tested, then half-and-half read-write access operation based on a second preset read-write unit is carried out, the first preset read-write unit is different from the second preset read-write unit, the half-and-half read-write access of the preset read-write unit is simultaneously read from the middle position of the preset read-write unit, and the half-and-half read-write access of the different preset read-write units is carried out twice, so that a read-write environment suitable for the occurrence of proximity mode sensitive faults can be constructed, the proximity mode sensitive faults can be more easily hit compared with the existing sequential read-write test mode, single-cell and multi-cell faults can be detected, the proximity mode sensitive faults can be easily detected, and the fault coverage rate during LPDDR testing is improved.
Drawings
FIG. 1 is a flowchart illustrating steps of a LDPPR testing method according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of an LDPPR testing apparatus according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a data write operation of the first model in the LPDDR test method according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating data reading of a first model in an LPDDR test method according to an embodiment of the invention;
FIG. 6 is a diagram illustrating a data write operation of a second model of the LPDDR test method in accordance with an embodiment of the present invention;
FIG. 7 is a data read of a second model of the LPDDR test method of the present invention;
FIG. 8 is a schematic diagram illustrating another data write operation of the first model in the LPDDR test method according to the embodiment of the invention;
FIG. 9 is a schematic diagram of another data reading of the first model in the LPDDR test method of the embodiment of the invention;
FIG. 10 is a diagram illustrating another data write operation of the second model in the LPDDR test method according to the embodiment of the invention;
FIG. 11 is a schematic diagram illustrating another data reading of a second model of the LPDDR test method in accordance with an embodiment of the present invention;
fig. 12 is another schematic structural diagram of an LDPPR testing apparatus according to an embodiment of the present invention.
Detailed Description
In order to explain the technical contents, the objects and the effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
Referring to fig. 1, an embodiment of the invention provides a LPDDR testing method, including the steps of:
simultaneously writing data into the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
simultaneously writing data into the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
and obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result.
As can be seen from the above description, the beneficial effects of the present invention are: the method comprises the steps of firstly carrying out half-and-half read-write access operation based on a first preset read-write unit on the LPDDR to be tested, and then carrying out half-and-half read-write access operation based on a second preset read-write unit, wherein the first preset read-write unit is different from the second preset read-write unit, because the half-and-half read-write access of the preset read-write unit is simultaneously read from the middle position of the preset read-write unit to the two ends, and the half-and-half read-write access of the different preset read-write units is carried out twice, therefore, a read-write environment suitable for the occurrence of the proximity mode sensitive faults can be constructed, compared with the existing sequential read-write test mode, the proximity mode sensitive faults can be hit more easily, single-cell and multi-cell faults can be detected, the proximity mode sensitive faults can be detected easily, and the fault coverage rate during the LPDDR test is improved.
Further, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
and simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each row of the LPDDR to be tested until data is written into each column of the row.
According to the description, for each line of the LPDDR to be tested, half-and-half reading and writing are carried out by taking the line as a unit, data are written into two ends from the middle of each line at the same time until all the storage units write the data, so that the actual use environment of a user on the LPDDR chip can be well simulated, the comprehensiveness of the detection of the LPDDR chip is ensured, the fault coverage rate of the LPDDR chip can be improved, the test time is saved and the production cost is reduced through the data writing mode.
Further, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
data is written to two ends simultaneously by taking a preset length as a unit from the middle position of each column of the LPDDR to be tested until data is written to each row of the columns.
According to the description, for each column of the LPDDR to be tested, half-and-half reading and writing are carried out in a row unit, data are written into two ends from the middle of each column at the same time until all the storage units are written into the data, so that the actual use environment of a user on the LPDDR chip can be well simulated, the comprehensiveness of detection of the LPDDR chip is ensured, the fault coverage rate of the LPDDR chip can be improved, the time complexity is low through the data writing mode, and the production cost is reduced.
Further, the preset length is a burst length or a bit.
According to the description, the preset length is set to be one burst length or one bit, so that the flexibility is high, the real data reading and writing conditions can be simulated, and the test result is more accurate.
Further, the writing data to both ends simultaneously from the middle position of each first preset read-write unit/second preset read-write unit of the LPDDR to be tested includes:
judging the data length corresponding to the first preset read-write unit/the second preset read-write unit, if the data length is an odd number, determining a storage unit corresponding to the middle position of the first preset read-write unit/the second preset read-write unit, writing preset data into the storage unit corresponding to the middle position, and simultaneously writing data into two ends of the storage unit corresponding to the middle position;
and if the data length is an even number, determining the middle position of the first preset read-write unit/the second preset read-write unit, and simultaneously writing data into two ends of the middle position.
According to the above description, the corresponding read-write mode is determined according to the parity of the data length of the preset read-write unit, so that the method can adapt to the data writing and reading of the preset read-write unit with different types of data lengths, and the test universality is improved.
Further, data is written in sequence from small to large according to the serial numbers of the first preset read-write unit/the second preset read-write unit or data is written in sequence from the middle position to two ends according to the serial numbers of the first preset read-write unit/the second preset read-write unit.
As can be seen from the above description, when data is read and written, in addition to half-and-half read and write access operations in the preset read and write units, read and write operations are sequentially performed between the preset read and write units from the middle positions of all the preset read and write units from both ends, so that it can be further ensured that a read and write mode closer to an adjacent mode sensitive fault is simulated, and the fault coverage rate is further improved.
Further, during the data writing process, the data written to the two ends at the same time are opposite.
According to the description, in the data writing process, the data written into the two ends are opposite, so that the read-write mode closer to the sensitive fault of the adjacent mode can be further simulated, and the fault coverage rate is further improved.
Another embodiment of the present invention provides an LPDDR testing apparatus, including:
the first data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each first preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
the second data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each second preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
and the test module is used for obtaining the test result of the LPDDR to be tested according to the first comparison result and the second comparison result.
Another embodiment of the present invention provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, performs the steps of the LPDDR test method described above.
Another embodiment of the present invention provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the LPDDR test method.
The LPDDR test method, apparatus, computer readable storage medium and electronic device of the present invention can be applied to various LPDDR tests, including LPDDR3, LPDD4 and LPDD4X, and other different generation products, and will be described in detail below with reference to the following embodiments:
example one
Referring to fig. 1, a DRAM test method includes the steps of:
s1, simultaneously writing data to two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
s2, simultaneously writing data into the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result; the first preset read-write unit and the second preset read-write unit are different;
s3, obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result;
specifically, the read data and the corresponding written expected data are sequentially compared through a comparison link in the reading operation, if the data are inconsistent, the data can be judged to be FAIL, and if all address space data are compared without errors, the data are judged to be PASS;
the first preset read-write unit and the second preset read-write unit can be combined differently and are realized through different models:
in an optional embodiment, the first preset read-write units are rows, and the second preset read-write units are columns;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each row of the LPDDR to be tested until data is written in each column of the row;
wherein, the preset length is a burst length or one bit;
wherein, burst Length (BL) is determined by JEDEC standard, and can also be freely set, that is, a plurality of bits (for example, 8 bits or 16 bits) are operated at a time to perform corresponding reading and writing, for example, when performing row-based data writing, if the located address is 0 row and the Burst Length is 8 bits, the first 8-bit numerical value of the data to be written is written at the position of 0 row and 0 column, then 9-16 bits of the data to be written are written in the second Burst Length, and the writing is continued until all the storage positions of 0 row are written, then the address of the next row is relocated, and the operation of the previous row is continued until the data is written in the entire disk, and the reading of the data is also similar operation;
in this embodiment, the preset length is one bit, specifically, as shown in fig. 4, first, half-and-half reading and writing are performed on a row:
firstly, determining the middle position of a first row, and simultaneously writing data in the N/2 th column and the (N/2) -1 st column;
then writing data in the (N/2) +1 st column and the (N/2) -2 nd column of the row simultaneously;
then, data is written simultaneously in the (N/2) +2 nd column and the (N/2) -3 rd column of the row;
in this way, the two ends write data simultaneously until all the memory cells in the first row write data, then switch to the next row, and repeat the same operation until all the memory cells of the LPDDR to be tested write data;
after the data writing is completed, as shown in fig. 5, half-and-half reading of the rows is performed, and the corresponding reading is performed in order according to the writing order:
determining the middle position of a first row, simultaneously reading data in an N/2 th column and an (N/2) -1 st column, and respectively comparing the data with written corresponding preset data;
then reading data simultaneously at the (N/2) +1 column and the (N/2) -2 column of the row, and respectively comparing the data with the written corresponding preset data;
then reading data simultaneously at the (N/2) +2 th column and the (N/2) -3 rd column of the row, and comparing the data with the written corresponding preset data in a distribution manner;
and in this way, the data are read at the two ends simultaneously until the data of all the storage units in the first row are read and compared, then the next row is switched, the same operation is repeated until all the storage units of the LPDDR to be tested are read and compared, and finally the first comparison result is obtained.
The step of simultaneously writing data to the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each column of the LPDDR to be tested until data is written into each row of the column;
in this embodiment, the preset length is one bit, specifically, as shown in fig. 6, first, half-and-half reading and writing are performed on the rows:
firstly, determining the middle position of a first column, and simultaneously writing data in the N/2 th row and the (N/2) -1 st row;
then writing data in the (N/2) +1 th row and the (N/2) -2 nd row of the column simultaneously;
then writing data in the (N/2) +2 th row and the (N/2) -3 rd row of the column simultaneously;
by analogy, the two ends write data simultaneously until all the storage units in the first column write data, then switch to the next column, and repeat the same operation until all the storage units of the LDPPR to be tested write data;
after the data writing is completed, as shown in fig. 7, row-to-half reading is performed, and the corresponding reading is performed in sequence according to the writing order:
determining the middle position of a first column, simultaneously reading data in the Nth/2 th row and the (N/2) -1 st row, and respectively comparing the data with written corresponding preset data;
then reading data simultaneously on the (N/2) +1 row and the (N/2) -2 row of the column, and respectively comparing the data with the written corresponding preset data;
then, simultaneously reading data in the (N/2) +2 th row and the (N/2) -2 nd row of the column, and respectively comparing the data with the written corresponding preset data;
and by analogy, the two ends write data into all the storage units in the first column at the same time until the data are read, compare the data with the written corresponding data, then switch to the next column, repeat the same operation until all the storage units of the LDPPR to be tested read the data, compare the data with the written corresponding data, and finally obtain a second comparison result.
Obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result;
specifically, if the data does not match, the comparison result is determined as FAIL, and if all the address space data are compared without error, the comparison result is determined as PASS.
In another optional implementation, the first preset read-write units are columns, and the second preset read-write units are rows;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each column of the LPDDR to be tested until data is written in each row of the rows;
specifically, as shown in fig. 6, first, half-and-half reading and writing is performed on a column;
after the data writing is completed, as shown in fig. 7, row-half reading is performed, and corresponding reading and comparison are sequentially performed according to the writing sequence to obtain a first comparison result;
the step of simultaneously writing data to the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each row of the LPDDR to be tested until data is written in each column of the row;
specifically, as shown in fig. 4, first, half-and-half reading and writing is performed on a row;
after the data writing is completed, as shown in fig. 5, half-and-half reading of the rows is performed, and corresponding reading and comparison are sequentially performed according to the writing order, so that a second comparison result is obtained.
Example two
The difference between this embodiment and the first embodiment is that it is limited to perform corresponding reading and writing according to the parity of the number of storage units in the preset reading and writing unit:
when data is written, judging the data length corresponding to the first preset read-write unit/the second preset read-write unit, if the data length is an odd number, determining a storage unit corresponding to the middle position of the first preset read-write unit/the second preset read-write unit, writing preset data into the storage unit corresponding to the middle position, and simultaneously writing data into two ends of the storage unit corresponding to the middle position;
if the data length is an even number, determining the middle position of the first preset read-write unit/the second preset read-write unit, and simultaneously writing data into two ends of the middle position;
when data reading is carried out, corresponding data reading is carried out based on the same judging mode;
as shown in fig. 4-7, the read/write mode is the case where the data length is even;
if the data length is odd, specifically, as shown in fig. 8, the rows are read and written in half first:
firstly, determining a read-write unit corresponding to the middle position of a first row as an (N-1)/2 th column, and writing preset data in the (N-1)/2 th column, wherein the preset data can be 0 or 1;
then, data is written simultaneously in the ((N-1)/2) +1 th column and ((N-1)/2) -1 st column of the row;
then, data is written simultaneously in the ((N-1)/2) +2 th column and ((N-1)/2) -2 nd column of this row;
then, data are written simultaneously in the ((N-1)/2) +3 rd column and ((N-1)/2) -3 rd column of the row;
in this way, the data are written into the storage units at the two ends at the same time until all the storage units in the first row write the data, then the next row is switched, and the same operation is repeated until all the storage units of the LPDDR to be tested write the data;
after the data writing is completed, as shown in fig. 9, half-and-half reading of the rows is performed, and the corresponding reading is performed in order according to the writing order:
firstly, determining a read-write unit corresponding to the middle position of a first row as an (N-1)/2 th column, reading data in the (N-1)/2 th column, and comparing the data with written corresponding preset data;
then reading data simultaneously at the ((N-1)/2) +1 th column and ((N-1)/2) -1 th column of the row and comparing the data with the written corresponding preset data respectively;
then reading data simultaneously at ((N-1)/2) +2 th column and ((N-1)/2) -2 nd column of the row and comparing them with the written corresponding data respectively;
then reading data simultaneously at ((n-1)/2) +3 th column and ((n-1)/2) -3 rd column of the row, and comparing the data with the written corresponding preset data respectively;
in this way, the two ends are written in simultaneously until all the memory cells in the first row are read, and after the comparison with the written corresponding data, the next row is switched, the same operation is repeated until all the memory cells of the LPDDR to be tested are read and compared, and finally a first comparison result is obtained;
after the first predetermined read-write unit finishes reading and writing, reading and writing of the second predetermined read-write unit is performed, similarly to the above, corresponding operations are performed based on the parity of the data length of the second predetermined read-write unit, and when the number is an odd number, fig. 10 shows a corresponding column-based half-and-half writing process, and fig. 11 shows a corresponding column-based half-and-half reading process.
EXAMPLE III
The difference between this embodiment and the first or second embodiment is that how to select the first predetermined read/write unit/the second predetermined read/write unit is specifically defined:
except that each first preset read-write unit in the LPDDR to be tested is sequentially selected according to the serial numbers of the first preset read-write unit/the second preset read-write unit from small to large as in the embodiment, for example, for the case that the first preset read-write unit is a row, the serial numbers of the rows can be selected from line 1, line 2 and line 3 \8230, and the serial numbers of the rows are sequentially selected to the last line 1; for the condition that the first preset read-write unit is a column, the number of the column can be 1 st column, 2 nd column and 3 rd column \8230, and the number of the column can be selected to the last 1 column in sequence;
the following modes can also be adopted:
randomly selecting a first preset read-write unit/a second preset read-write unit in the LPDDR to be tested until all the first preset read-write units/the second preset read-write units in the LPDDR to be tested are traversed;
or selecting the first preset read-write unit/the second preset read-write unit in the LPDDR to be tested from the middle to both ends until all the first preset read-write units/the second preset read-write units in the DRAM to be tested are traversed, for example, if the first preset read-write unit is a row, if a total of N rows is assumed, and N is an even number, data can be written in the following row sequence: n/2, N/2-1, N/2+1, N/2-2, N/2+2 \8230, and 8230, until all rows are traversed, or similar to half-and-half read-write operation in a preset read-write unit, namely, writing into two rows at two ends simultaneously from the middle two rows, namely writing N/2 and N/2-1 simultaneously, then writing N/2+1 and N/2-2 simultaneously, and then writing N/2+2, N/2-3, 8230, and 8230until all rows are traversed.
Example four
The difference between this embodiment and the first or second or third embodiment is that, in the data writing process, the data written to both ends at the same time is opposite, for example, if the data written from the middle position to the back of the first preset unit is 0, the data written from the middle position to the front is 1, or the data written from the middle position to the back of the first preset unit is 1, the data written from the middle position to the front is 0;
specifically, for the first model, the data content to be written is 010101 \8230 \/8230010 \/2 column is written with 0 and (n/2) -1 column is written with 1 when n is an even number during data writing; column (n/2) +1 is written with 1, and columns (n/2) -2 are written with 0; columns (n/2) +2 write 0, columns (n/2) -3 write 1, and so on;
correspondingly, when data reading is carried out, the data is read and compared with 0 in the n/2 th column, and the data is read and compared with 1 in the (n/2) -1 th column; column (n/2) +1 reads and compares with 1, column (n/2) -2 reads and compares with 0; columns (n/2) +2 read and compare with 0, columns (n/2) -3 read and compare with 1, and so on.
In FIGS. 4-11, D and/D are inverted data.
For the embodiment with the preset length of one bit, for example, D is 0, then/D is 1, and for the embodiment with the preset length of one burst length, for example, D is 01010101, then/D is 10101010.
EXAMPLE five
Referring to fig. 2, an LPDDR test apparatus includes:
the first data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each first preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
the second data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each second preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
the test module is used for obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result;
further, as shown in fig. 12, the first data reading and writing module may be subdivided into:
the first data writing module is used for simultaneously writing data to two ends from the middle position of each first preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data;
the first data reading module is used for reading corresponding data according to the data writing process of the first data writing module;
the first comparison module is used for comparing the data written in by the first data writing module with the data read by the first data reading module to obtain a first comparison result;
the second data read-write module is subdivided into:
the second data writing module is used for simultaneously writing data to the two ends from the middle position of each second preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data;
the second data reading module is used for reading corresponding data according to the data writing process of the second data writing module;
and the second comparison module is used for comparing the data written in by the second data writing module with the data read by the second data reading module to obtain a second comparison result.
EXAMPLE six
A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of a LPDDR test method according to any one of the first to fourth embodiments.
EXAMPLE seven
Referring to fig. 3, an electronic device includes a memory, a processor, and a computer program stored in the memory and running on the processor, wherein the processor executes the computer program to implement the steps of the LPDDR test method according to any one of the first to fourth embodiments.
In summary, according to the LPDDR test method, the apparatus, the readable storage medium and the electronic device provided by the present invention, a half-and-half read-write access operation based on a first preset read-write unit is performed on an LPDDR to be tested, and then a half-and-half read-write access operation based on a second preset read-write unit is performed on the LPDDR, where the first preset read-write unit and the second preset read-write unit are different and can be listed first and listed second or listed first and listed second, and the flexibility is high, and since the half-and-half read-write access of the preset read-write unit starts to read from the middle position of the preset read-write unit to both ends at the same time, the preset read-write unit can also start to read from both ends from the middle position, a read-write environment suitable for the occurrence of an adjacent mode sensitive fault can be constructed, compared with the existing sequential read-write test method, the adjacent mode sensitive fault can be hit more easily, not only single-cell and multi-cell faults can be detected, but also the adjacent mode sensitive faults can be detected easily, and the fault coverage rate when the LPDDR test is increased; chip defects which are difficult to find before can be detected, and the yield can be improved; and has low time complexity, and is suitable for mass production test.
In the above embodiments provided in the present application, it should be understood that the disclosed method, apparatus, computer-readable storage medium, and electronic device may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of components or modules may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or components or modules, and may be in an electrical, mechanical or other form.
The components described as separate parts may or may not be physically separate, and parts displayed as components may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network modules. Some or all of the components can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing module, or each component may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.
The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that for simplicity and convenience of description, the above-described method embodiments are shown as a series of combinations of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred and that no acts or modules are necessarily required of the invention.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The above description is only an embodiment of the present invention, and is not intended to limit the scope of the present invention, and all equivalent modifications made by the present invention and the contents of the accompanying drawings, which are directly or indirectly applied to the related technical fields, are included in the scope of the present invention.
Claims (8)
1. A method for testing LPDDR, comprising the steps of:
simultaneously writing data into the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
simultaneously writing data into the two ends from the middle position of each second preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result;
the first preset read-write units are rows, and the second preset read-write units are columns;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each row of the LPDDR to be tested until data is written into each column of the row;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit/second preset read-write unit of the LPDDR to be tested comprises the following steps:
judging the data length corresponding to the first preset read-write unit/the second preset read-write unit, if the data length is an odd number, determining a storage unit corresponding to the middle position of the first preset read-write unit/the second preset read-write unit, writing preset data into the storage unit corresponding to the middle position, and simultaneously writing data into two ends of the storage unit corresponding to the middle position;
and if the data length is an even number, determining the middle position of the first preset read-write unit/the second preset read-write unit, and simultaneously writing data into two ends of the middle position.
2. The LPDDR test method of claim 1, wherein the first predetermined read/write units are columns and the second predetermined read/write units are rows;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
data is written to both ends simultaneously in units of a preset length from the middle position of each column of the LPDDR to be tested until each row of the columns is written with data.
3. The method of claim 2 wherein the predetermined length is a burst length or a bit.
4. The LPDDR test method of claim 1, wherein the data is written sequentially from the small to the large number according to the first predetermined reader/writer/the second predetermined reader/writer or from the middle to both ends according to the number of the first predetermined reader/writer/the second predetermined reader/writer.
5. The LPDDR test method of any one of claims 1 to 2 to 4, wherein during the data writing process, the data written to both ends simultaneously is reversed.
6. An LPDDR test apparatus, comprising:
the first data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each first preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a first comparison result;
the second data reading and writing module is used for simultaneously writing data into the two ends from the middle position of each second preset reading and writing unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write the data, reading the data corresponding to the data writing process, and comparing the read data with the corresponding written data to obtain a second comparison result;
the first preset read-write unit and the second preset read-write unit are different;
the test module is used for obtaining a test result of the LPDDR to be tested according to the first comparison result and the second comparison result;
the first preset read-write units are rows, and the second preset read-write units are columns;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit of the LPDDR to be tested until all the storage units of the LPDDR to be tested write data comprises the following steps:
simultaneously writing data to two ends by taking a preset length as a unit from the middle position of each row of the LPDDR to be tested until data is written into each column of the row;
the step of simultaneously writing data to the two ends from the middle position of each first preset read-write unit/second preset read-write unit of the LPDDR to be tested comprises the following steps:
judging the data length corresponding to the first preset read-write unit/the second preset read-write unit, if the data length is an odd number, determining a storage unit corresponding to the middle position of the first preset read-write unit/the second preset read-write unit, writing preset data into the storage unit corresponding to the middle position, and simultaneously writing data into two ends of the storage unit corresponding to the middle position;
and if the data length is an even number, determining the middle position of the first preset read-write unit/the second preset read-write unit, and simultaneously writing data into two ends of the middle position.
7. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of a method for LPDDR testing as claimed in any one of the claims 1 to 5.
8. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of a LPDDR test method according to any one of claims 1 to 5 when executing the computer program.
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