CN112164718A - 具有控制栅保护层的分离栅器件及其制造方法 - Google Patents

具有控制栅保护层的分离栅器件及其制造方法 Download PDF

Info

Publication number
CN112164718A
CN112164718A CN202010888222.7A CN202010888222A CN112164718A CN 112164718 A CN112164718 A CN 112164718A CN 202010888222 A CN202010888222 A CN 202010888222A CN 112164718 A CN112164718 A CN 112164718A
Authority
CN
China
Prior art keywords
region
conductive type
oxide layer
control gate
dielectric oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202010888222.7A
Other languages
English (en)
Inventor
章文通
祖健
朱旭晗
方冬
乔明
李肇基
张波
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
Original Assignee
University of Electronic Science and Technology of China
Guangdong Electronic Information Engineering Research Institute of UESTC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Electronic Science and Technology of China, Guangdong Electronic Information Engineering Research Institute of UESTC filed Critical University of Electronic Science and Technology of China
Priority to CN202010888222.7A priority Critical patent/CN112164718A/zh
Publication of CN112164718A publication Critical patent/CN112164718A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)

Abstract

本发明提供一种具有控制栅保护层的分离栅器件及其制造方法，包括第一导电类型衬底，第一导电类型漂移区，第二导电类型阱区，重掺杂第一导电类型区，重掺杂第二导电类型区，第二导电类型区，第一介质氧化层，第二介质氧化层，第三介质氧化层，第四介质氧化层，第五介质氧化层，控制栅多晶电极，分离栅多晶电极，源极金属接触；所述第二导电类型区位于重掺杂第二导电类型区下方作为控制栅保护层，在关态耐压时将原本指向控制栅的电场线转移至该第二导电类型区的电离负电荷，成功降低了控制栅靠近漂移区位置的电场峰值，消除了该处可能存在的提前击穿。

Description

具有控制栅保护层的分离栅器件及其制造方法
技术领域
本发明属于半导体工艺制造技术领域，具体涉及一种具有控制栅保护层的分离栅器件。
背景技术
功率器件由于其优越的特性被广泛应用于移动通信、汽车电子、移动终端等各个领域中， 槽型垂直沟道VDMOS作为最广泛应用的功率器件之一，对其结构的改进一直源源不断。其 中分离栅VDMOS器件(Split-Gate VDMOS)由于分离栅电极起纵向场板辅助耗尽的作用， 提高了漂移区掺杂浓度降低器件导通电阻，同时屏蔽了栅极与漏极之间的电容，带来了优异 的开关特性，因此受到了广泛的关注。在传统分离栅器件中，控制栅长度过短容易带来断沟 和导通电阻增加，控制栅长度较长时，指向控制栅的电场线将带来靠近控制栅的硅层电场峰 值，可能导致提前击穿甚至控制栅拐角处栅氧击穿，在栅氧化层较薄和漂移区掺杂浓度增加 时将更为明显。
发明内容
本发明针对背景技术存在的缺陷，提出一种具有控制栅保护层的分离栅器件，在关态耐 压时减少指向控制栅的电场线，降低靠近栅极处的硅层电场，消除提前击穿，同时也有降低 漂移区表面场的作用。
为实现上述发明目的，本发明技术方案如下：
重掺杂第一导电类型衬底11、第一导电类型漂移区12、第一介质氧化层31、分离栅多晶 电极41、第二介质氧化层32、第三介质氧化层33、控制栅多晶电极42、第四介质氧化层34、 第二导电类型阱区21、重掺杂第一导电类型区13、第五介质氧化层35、第二导电类型区22、 重掺杂第二导电类型区23、源极金属接触51；
其中，第一导电类型漂移区12位于重掺杂第一导电类型衬底11上方，由第一介质氧化 层31、第二介质氧化层32、第三介质氧化层33、第四介质氧化层34以及控制栅多晶电极41 和分离栅多晶电极42组成的槽型结构位于第一导电类型漂移区12两侧，第五介质氧化层35 和重掺杂第一导电类型区13都位于器件表面源极金属接触51左右两侧，重掺杂第二导电类 型区23位于第二导电类型阱区21内源极金属接触51下方并与重掺杂第一导电类型区13短 接，第二导电类型区22位于重掺杂第二导电类型区23下方并与第二导电类型阱区21相连。
所述第二导电类型区22位于重掺杂第二导电类型区23下方与第二导电类型阱区21相连 作为控制栅保护层，起降低控制栅拐角处电场峰值的作用。
作为优选方式，重掺杂第二导电类型区23与第二导电类型阱区21相连，重掺杂第二导 电类型区23与第二导电类型区22相连或不相连。
作为优选方式，第二导电类型区22通过一次或多次注入得到。
作为优选方式，源极金属接触51进一步延长至第二导电类型阱区21内靠近第一导电类 型漂移区12的位置或第一导电类型漂移区12内。
作为优选方式，第二导电类型区22的下边界高于或低于控制栅多晶电极41下沿，或连 续延伸到漂移区内任一位置。
作为优选方式，所使用的半导体材料是Si或SiC材料，相同的控制栅保护层结构所应用 的半导体器件为槽栅VDMOS。
作为优选方式，所述第一导电类型为N型，第二导电类型为P型；或第一导电类型为P 型，第二导电类型为N型。
本发明还提供上述具有控制栅保护层的分离栅器件的制造方法，包括如下步骤：
步骤1：在衬底上通过外延或注入推结的方式得到漂移区；
步骤2：深槽刻蚀漂移区并热氧化得到第一介质氧化层；
步骤3：淀积刻蚀得到分离栅多晶电极；
步骤4：第二介质氧化层填充深槽，刻蚀后栅氧化得到第三介质氧化层；
步骤5：淀积刻蚀得到控制栅多晶电极，并淀积第四介质氧化层；
步骤6：注入推结第二导电类型阱区和重掺杂第一导电类型区；
步骤7：热氧化得到第五介质氧化层做注入保护，并刻蚀源极接触孔；
步骤8：通过源极接触孔注入重掺杂第二导电类型区和位于其下方的第二导电类型区；
步骤9：金属淀积形成源极金属接触。
作为优选方式，制作步骤4中先通过热氧化加淀积的方式得到栅氧化层。
本发明的有益效果为：采用源极接触孔注入第二导电类型区的方式引入控制栅保护层， 成功抑制了器件表面场随漂移区浓度增加，屏蔽了靠近控制栅的漂移区电场峰值，消除了该 处可能存在的提前击穿，进一步提高了器件掺杂浓度降低比导通电阻。
附图说明
图1为传统分离栅VDMOS器件结构示意图；
图2为本发明实施例1的具有控制栅保护层的分离栅器件结构示意图；
图3为本发明实施例2的具有控制栅保护层的分离栅器件结构示意图；
图4为本发明实施例3的具有控制栅保护层的分离栅器件结构示意图；
图5为本发明实施例4的具有控制栅保护层的分离栅器件结构示意图
图6(a)-图6(l)为实施例1的具有控制栅保护层的分离栅器件工艺制作示意图；
图6为传统分离栅器件和实施例1中具有控制栅保护层的分离栅器件在栅氧厚度15nm 和0.09Ω·cm漂移区电阻率条件下的仿真结果图；
图7为传统分离栅器件和实施例1中具有控制栅保护层的分离栅器件击穿曲线仿真示意 图；
图8为传统分离栅器件和实施例1中具有控制栅保护层的分离栅器件仿真耐压曲线；
图9所示为为传统分离栅器件和实施例1中具有控制栅保护层的分离栅器件沿图7中AA’ 线的电场分布；
11为重掺杂第一导电类型衬底，12为第一导电类型漂移区，13为重掺杂第一导电类型区， 14为第一导电类型区，21为第二导电类型阱区，22为第二导电类型区，23为重掺杂第二导 电类型区，24为第四介质氧化层，31为第一介质氧化层，32为第二介质氧化层，33为第三 介质氧化层，34为第四介质氧化层，35为第五介质氧化层，41为分离栅多晶电极，42为控 制栅多晶电极，51为源极金属接触。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露 的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加 以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精 神下进行各种修饰或改变。
如图1所示，为传统分离栅器件结构示意图，其特点在于存在通过源极接触孔注入位于 第二导电类型阱区21内的重掺杂第二导电类型区23做欧姆接触，无下方第二导电类型区22； 漂移区表面电场随漂移区浓度提高而快速增加，关态耐压时在靠近控制栅的第一导电类型漂 移区12中存在电场峰值，有可能导致提前击穿甚至栅氧击穿。
如图7所示为传统分离栅器件和实施例1中具有控制栅保护层的分离栅器件仿真结果图， 图8所示为二者仿真耐压曲线，图9所示为二者沿图7中AA’线的电场分布，可见通过引入 控制栅保护层，实施实例1中的具有控制栅保护层的分离栅器件成功降低了控制栅处A’点电 场峰值，提高了器件耐压。
实施例1
如图2为本发明实施例1的具有控制栅保护层的分离栅器件，具体包括：
重掺杂第一导电类型衬底11、第一导电类型漂移区12、第一介质氧化层31、分离栅多晶 电极41、第二介质氧化层32、第三介质氧化层33、控制栅多晶电极42、第四介质氧化层34、 第二导电类型阱区21、重掺杂第一导电类型区13、第五介质氧化层35、第二导电类型区22、 重掺杂第二导电类型区23、源极金属接触51；
其中，第一导电类型漂移区12位于重掺杂第一导电类型衬底11上方，由第一介质氧化 层31、第二介质氧化层32、第三介质氧化层33、第四介质氧化层34以及控制栅多晶电极41 和分离栅多晶电极42组成的槽型结构位于第一导电类型漂移区12两侧，第五介质氧化层35 和重掺杂第一导电类型区13都位于器件表面源极金属接触51左右两侧，重掺杂第二导电类 型区23位于第二导电类型阱区21内源极金属接触51下方并与重掺杂第一导电类型区13短 接，第二导电类型区22位于重掺杂第二导电类型区23下方并与第二导电类型阱区21相连。
所述第二导电类型区22位于重掺杂第二导电类型区23下方与第二导电类型阱区21相连 作为控制栅保护层，起降低控制栅拐角处电场峰值的作用。
本实施例还提供一种具有超结结构的分离栅VDMOS器件制作方法，具体包括如下步骤， 如图6(a)-6(l)所示：
步骤1：在衬底上通过外延或注入的方式得到漂移区，如图6(a)所示；
步骤2：深槽刻蚀漂移区并热氧化得到第一介质氧化层，如图6(b)和图6(c)；
步骤3：淀积刻蚀得到分离栅多晶电极，如图6(d)所示；
步骤4：第二介质氧化层填充深槽，如图6(e)所示，刻蚀后栅氧化得到第三介质氧化层， 如图图6(f)和图6(g)；
步骤5：淀积刻蚀得到控制栅多晶电极，并淀积第四介质氧化层，如图6(h)所示；
步骤6：注入推结第二导电类型阱区和重掺杂第一导电类型区，如图6(i)所示；
步骤7：热氧化得到第五介质氧化层做注入保护，并刻蚀源极接触孔，如图6(j)所示；
步骤8：通过源极接触孔注入重掺杂第二导电类型区和位于其下方的第二导电类型区，如 图6(k)所示；
步骤9：金属淀积形成源极金属接触，如图6(l)所示。
进一步地，重掺杂第二导电类型区23与第二导电类型阱区21相连，重掺杂第二导电类 型区23与第二导电类型区22可相连或不相连；
进一步地，第二导电类型区22通过一次或多次注入得到，其掺杂浓度随第一导电类型漂 移区12掺杂浓度变化；
进一步地，源极金属接触51进一步延长至第二导电类型阱区21内靠近第一导电类型区 12处，或第一导电类型漂移区12内。
进一步地，制作步骤4中先通过热氧化加淀积的方式得到栅氧化层。
进一步地，相同的超结结构和制作方法可用于其他同类槽型垂直沟道器件中，所使用的 半导体材料可以是Si或SiC等新一代半导体材料；相同的控制栅保护层结构所应用的半导体 器件为槽栅VDMOS。
实施例2
图3为本发明实施例2的具有控制栅保护层的分离栅器件结构示意图，与实施例1不同 之处在于：第二导电类型区域22分多次不同剂量和能量注入形成，其中能量越大注入剂量越 小，形成从上至下宽度递减的梯形第二导电类型区22。通过降低深处第二导电类型区22的 宽度，减小该处的JFET效应，进一步降低器件比导通电阻。
实施例3
图4(a)为本发明实施例3的具有控制栅保护层的分离栅器件结构示意图，在实施例1和 2的基础上将源极金属接触51延伸至第二导电类型阱区21内靠近漂移区12处，配合更高能 量的注入将第二导电类型区22引入漂移区深处进一步优化器件漂移区内部电场；
图4(b)为本发明实施例3的另一变形，将源极金属接触51延伸至第一导电类型漂移区 12内，形成肖特基接触，降低器件反向恢复时间，重掺杂第二导电类型区23和第二导电类 型区22起屏蔽肖特基结处电场峰值和优化器件体内场的作用，其余制作方法和工作原理和实 施例1相同。
实施例4
图5(b)为本发明实施例4的具有控制栅保护层的分离栅器件结构示意图，与实施例1不 同之处在于在图6(f)所示的制作步骤4中增加一次如图5(a)所示的倾斜的第一导电类型注入， 在第二导电类型区22两侧的漂移区中形成局部第一导电类型掺杂，抑制该处JFET效应带来 的导通电阻增加，其余制作方法和工作原理与实施实例1基本一致。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技 术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所 属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效 修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (9)

1.一种具有控制栅保护层的分离栅器件，其特征在于包括：重掺杂第一导电类型衬底(11)、第一导电类型漂移区(12)、第一介质氧化层(31)、分离栅多晶电极(41)、第二介质氧化层(32)、第三介质氧化层(33)、控制栅多晶电极(42)、第四介质氧化层(34)、第二导电类型阱区(21)、重掺杂第一导电类型区(13)、第五介质氧化层(35)、第二导电类型区(22)、重掺杂第二导电类型区(23)、源极金属接触(51)；
其中，第一导电类型漂移区(12)位于重掺杂第一导电类型衬底(11)上方，由第一介质氧化层(31)、第二介质氧化层(32)、第三介质氧化层(33)、第四介质氧化层(34)以及控制栅多晶电极(41)和分离栅多晶电极(42)组成的槽型结构位于第一导电类型漂移区(12)两侧，第五介质氧化层(35)和重掺杂第一导电类型区(13)都位于器件表面源极金属接触(51)左右两侧，重掺杂第二导电类型区(23)位于第二导电类型阱区(21)内源极金属接触(51)下方并与重掺杂第一导电类型区(13)短接，第二导电类型区(22)位于重掺杂第二导电类型区(23)下方并与第二导电类型阱区(21)相连。
2.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：重掺杂第二导电类型区(23)与第二导电类型阱区(21)相连，重掺杂第二导电类型区(23)与第二导电类型区(22)相连或不相连。
3.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：第二导电类型区(22)通过一次或多次注入得到。
4.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：源极金属接触(51)进一步延长至第二导电类型阱区(21)内靠近第一导电类型漂移区(12)的位置，或第一导电类型漂移区(12)内。
5.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：第二导电类型区(22)的下边界高于或低于控制栅多晶电极(42)下沿，或连续延伸到第一导电类型漂移区(12)内任一位置。
6.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：所使用的半导体材料是Si或SiC材料，相同的控制栅保护层结构所应用的半导体器件为槽栅VDMOS。
7.根据权利要求1所述的具有控制栅保护层的分离栅器件，其特征在于：所述第一导电类型为N型，第二导电类型为P型；或第一导电类型为P型，第二导电类型为N型。
8.权利要求1至7任意一项所述的具有控制栅保护层的分离栅器件的制造方法，其特征在于包括如下步骤：
步骤1：在衬底上通过外延或注入推结的方式得到漂移区；
步骤2：深槽刻蚀漂移区并热氧化得到第一介质氧化层；
步骤3：淀积刻蚀得到分离栅多晶电极；
步骤4：第二介质氧化层填充深槽，刻蚀后栅氧化得到第三介质氧化层；
步骤5：淀积刻蚀得到控制栅多晶电极，并淀积第四介质氧化层；
步骤6：注入推结第二导电类型阱区和重掺杂第一导电类型区；
步骤7：热氧化得到第五介质氧化层做注入保护，并刻蚀源极接触孔；
步骤8：通过源极接触孔注入重掺杂第二导电类型区和位于其下方的第二导电类型区；
步骤9：金属淀积形成源极金属接触。
9.根据权利要求8所述的具有控制栅保护层的分离栅器件的制造方法，其特征在于：制作步骤4中通过热氧化加淀积的方式得到栅氧化层。
CN202010888222.7A 2020-08-28 2020-08-28 具有控制栅保护层的分离栅器件及其制造方法 Pending CN112164718A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010888222.7A CN112164718A (zh) 2020-08-28 2020-08-28 具有控制栅保护层的分离栅器件及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010888222.7A CN112164718A (zh) 2020-08-28 2020-08-28 具有控制栅保护层的分离栅器件及其制造方法

Publications (1)

Publication Number Publication Date
CN112164718A true CN112164718A (zh) 2021-01-01

Family

ID=73859387

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010888222.7A Pending CN112164718A (zh) 2020-08-28 2020-08-28 具有控制栅保护层的分离栅器件及其制造方法

Country Status (1)

Country Link
CN (1) CN112164718A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990929A (zh) * 2021-10-28 2022-01-28 电子科技大学 一种半导体纵向器件及制备方法
CN114628524A (zh) * 2022-02-09 2022-06-14 湖南大学 一种具有低比导通电阻的深槽分裂栅mosfet

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057757A1 (en) * 2007-08-31 2009-03-05 Kabushiki Kaisha Toshiba Trench gate semiconductor device and method of manufacturing the same
US20090146209A1 (en) * 2007-12-10 2009-06-11 Kabushiki Kaisha Toshiba Semiconductor device
CN102403315A (zh) * 2010-09-07 2012-04-04 株式会社东芝 半导体装置
CN102549753A (zh) * 2009-08-27 2012-07-04 威世硅尼克斯 超结型沟槽功率mosfet器件
US20120175699A1 (en) * 2011-01-06 2012-07-12 Force Mos Technology Co., Ltd. Trench mosfet with super pinch-off regions and self-aligned trenched contact
CN103872133A (zh) * 2012-12-12 2014-06-18 力士科技股份有限公司 短沟道沟槽式金属氧化物半导体场效应管
CN105280714A (zh) * 2014-07-21 2016-01-27 半导体元件工业有限责任公司 具有屏蔽电极结构的绝缘栅半导体装置和方法
CN110071169A (zh) * 2018-01-23 2019-07-30 英飞凌科技奥地利有限公司 具有体接触与介电间隔部的半导体器件及对应的制造方法
CN110676305A (zh) * 2019-08-31 2020-01-10 电子科技大学 具有低栅电荷特性的垂直沟道器件及制造方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090057757A1 (en) * 2007-08-31 2009-03-05 Kabushiki Kaisha Toshiba Trench gate semiconductor device and method of manufacturing the same
US20090146209A1 (en) * 2007-12-10 2009-06-11 Kabushiki Kaisha Toshiba Semiconductor device
CN102549753A (zh) * 2009-08-27 2012-07-04 威世硅尼克斯 超结型沟槽功率mosfet器件
CN102403315A (zh) * 2010-09-07 2012-04-04 株式会社东芝 半导体装置
US20120175699A1 (en) * 2011-01-06 2012-07-12 Force Mos Technology Co., Ltd. Trench mosfet with super pinch-off regions and self-aligned trenched contact
CN103872133A (zh) * 2012-12-12 2014-06-18 力士科技股份有限公司 短沟道沟槽式金属氧化物半导体场效应管
CN105280714A (zh) * 2014-07-21 2016-01-27 半导体元件工业有限责任公司 具有屏蔽电极结构的绝缘栅半导体装置和方法
CN110071169A (zh) * 2018-01-23 2019-07-30 英飞凌科技奥地利有限公司 具有体接触与介电间隔部的半导体器件及对应的制造方法
CN110676305A (zh) * 2019-08-31 2020-01-10 电子科技大学 具有低栅电荷特性的垂直沟道器件及制造方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
何俊卿 等: "一种具有Buffer层的分离栅VDMOS研究", 《电子与封装》 *

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113990929A (zh) * 2021-10-28 2022-01-28 电子科技大学 一种半导体纵向器件及制备方法
CN113990929B (zh) * 2021-10-28 2023-05-26 电子科技大学 一种半导体纵向器件及制备方法
CN114628524A (zh) * 2022-02-09 2022-06-14 湖南大学 一种具有低比导通电阻的深槽分裂栅mosfet

Similar Documents

Publication Publication Date Title
US8659076B2 (en) Semiconductor device structures and related processes
KR101735230B1 (ko) 게이트 산화물 층에 감소된 전기장을 갖는 반도체 디바이스들
CN109065621B (zh) 一种绝缘栅双极晶体管及其制备方法
CN114122123B (zh) 集成高速续流二极管的碳化硅分离栅mosfet及制备方法
CN116666425B (zh) 一种SiC沟槽型MOSFET器件
CN109065627A (zh) 一种具有多晶硅岛的ldmos器件
CN111969043A (zh) 高压三维耗尽超结ldmos器件及其制造方法
CN103515443B (zh) 一种超结功率器件及其制造方法
CN108538909A (zh) 具有电荷补偿块的异质结垂直双扩散金属氧化物半导体场效应管及其制作方法
CN113658999B (zh) 具有无结终端技术功率半导体器件及制造方法和应用
CN105047716B (zh) 射频ldmos器件及其制造方法
CN108054202B (zh) 一种半导体结构及其形成方法
CN113659009A (zh) 体内异性掺杂的功率半导体器件及其制造方法
CN113823694A (zh) 集成亚微米超结的横向功率半导体器件及其制造方法
CN112164718A (zh) 具有控制栅保护层的分离栅器件及其制造方法
CN113066865A (zh) 降低开关损耗的半导体器件及其制作方法
CN108172618B (zh) 高k介质沟槽横向双扩散金属氧化物宽带隙半导体场效应管及其制作方法
CN116469924A (zh) 漂移区电场优化的屏蔽栅mosfet
CN115763562A (zh) 一种高迁移率碳化硅n型ldmos器件
CN113410299B (zh) 一种高耐压的n沟道LDMOS器件及其制备方法
CN104701368B (zh) 射频ldmos器件及其制造方法
CN113659008A (zh) 具有电场钳位层的匀场器件及其制造方法和应用
CN113078204A (zh) 一种氮化镓3d-resurf场效应晶体管及其制造方法
CN1146969C (zh) 碳化硅横向场效应晶体管和制造方法及其使用
CN117352557B (zh) 一种集成式sgt mosfet及其制备工艺

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20210101