CN112018025A - Preparation method of III-V group compound semiconductor heterojunction structure - Google Patents
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- 150000001875 compounds Chemical class 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 94
- 238000002360 preparation method Methods 0.000 title abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 81
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 37
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims abstract description 36
- 239000000463 material Substances 0.000 claims abstract description 25
- 239000013078 crystal Substances 0.000 claims description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 16
- 239000010703 silicon Substances 0.000 claims description 16
- 230000007547 defect Effects 0.000 claims description 15
- 238000004519 manufacturing process Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 238000000231 atomic layer deposition Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 12
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910000673 Indium arsenide Inorganic materials 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- VTGARNNDLOTBET-UHFFFAOYSA-N gallium antimonide Chemical compound [Sb]#[Ga] VTGARNNDLOTBET-UHFFFAOYSA-N 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 8
- 230000035699 permeability Effects 0.000 abstract description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 4
- 230000003287 optical effect Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 3
- 238000000227 grinding Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000010884 ion-beam technique Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
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Abstract
The invention provides a preparation method of a III-V group compound semiconductor heterojunction structure, which comprises the following steps: providing a monocrystalline group III-V compound semiconductor base and a heterogeneous support substrate, wherein the monocrystalline group III-V compound semiconductor base is provided with a first bonding surface, and the heterogeneous support substrate is provided with a second bonding surface; forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface; and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer. The alumina film has high surface energy, can obtain high bonding quality under the condition of low-temperature bonding, is an amorphous material, has good absorptivity and permeability to water molecules, and can effectively remove gas generated at a bonding interface in the bonding process, so that the III-V compound semiconductor heterogeneous bonding is realized by adopting the alumina dielectric layer, and a high-quality bonding interface with high bonding strength and no bubbles at the bonding interface can be obtained.
Description
Technical Field
The invention belongs to the technical field of preparation of heterogeneous substrates, and particularly relates to a preparation method of a III-V group compound semiconductor heterogeneous bonding structure.
Background
In recent years, the field of silicon optical has important breakthrough progress, and various silicon-based optical devices are emerging continuously, so that the silicon-based optical system plays an important role in future information processing and communication, particularly in data centers and supercomputers.
However, since silicon is an indirect bandgap semiconductor, it cannot be an effective light emitting material, while most iii-v compound semiconductor materials are direct bandgap semiconductor materials and are good materials for fabricating optical devices. In order to realize the silicon-based photosystem, two main methods are provided, one is to directly epitaxially grow a III-V group compound semiconductor material on a silicon substrate to prepare an optical device, the other is to directly combine the prepared III-V group optical device with the silicon substrate, and the other method needs to realize the heterogeneous integration of the III-V group compound semiconductor material and the silicon substrate, which is also the biggest challenge of the current silicon-based photosystem. Due to the fact that large lattice mismatch and thermal mismatch exist between the III-V group compound semiconductor and silicon, when the III-V group compound semiconductor is grown on a silicon substrate in a heteroepitaxial mode, more dislocations appear, and the high-quality III-V group compound semiconductor and the silicon substrate are difficult to achieve heterointegration, so that the performance and the reliability of devices in the later period are reduced. The advent of bonding technology has made it possible to combine group iii-v compound semiconductor materials with heterogeneous materials such as silicon. The bonding technique is that the surfaces of two substrate sheets with atomically flat surfaces are contacted to form chemical bonds at the whole interface, and then the bonding strength is enhanced by high-temperature annealing. After the two heterogeneous material substrates are bonded together, the integration of the film heterogeneous materials can be realized through grinding and thinning, chemical mechanical polishing or ion beam stripping technology. And then, a chip-to-wafer bonding technology is developed, namely, the prepared device is bonded with a heterogeneous substrate to realize integration.
However, there are problems with thermal mismatch and bonding interface bubbles whether the heterogeneous material is integrated directly by bonding or the device is integrated by chip-to-wafer bonding. The large thermal mismatch may cause wafer chipping or debonding, and bubbles generated at the interface during bonding may also affect the bonding strength and quality of the bonding interface, thereby reducing the performance and reliability of the integrated device.
Accordingly, it is desirable to provide a method for fabricating a iii-v compound semiconductor heterojunction structure that solves the above-mentioned problems of the prior art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a iii-v compound semiconductor heterojunction structure, which is used to solve the problems of the prior art, such as low bonding strength of the iii-v compound semiconductor to the foreign substrate, poor quality of the bonding interface, etc.
To achieve the above and other related objects, the present invention provides a method for fabricating a group iii-v compound semiconductor heterojunction structure, the method comprising at least the steps of:
providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face;
forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;
and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.
Optionally, the material of the single-crystalline iii-v compound semiconductor base comprises one of the group consisting of indium phosphide, gallium arsenide, gallium antimonide, indium arsenide, and gallium nitride.
Optionally, the material of the heterogeneous support substrate comprises one of the group consisting of silicon, silicon oxide, germanium, silicon carbide, gallium arsenide.
Optionally, the first aluminum oxide dielectric layer is formed by using an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method, and the second aluminum oxide dielectric layer is formed by using an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method.
Optionally, the thickness of the first alumina dielectric layer is between 2nm and 100nm, and the thickness of the second alumina dielectric layer is between 2nm and 100 nm.
Optionally, bonding the first alumina dielectric layer and the second alumina dielectric layer further comprises thinning the single-crystal iii-v compound semiconductor base and/or the heterogeneous support substrate.
Optionally, the foreign support substrate comprises a single crystal foreign support substrate.
Optionally, before forming the first alumina dielectric layer on the first bonding surface, performing ion implantation on the single-crystal iii-v compound semiconductor substrate from the first bonding surface to form a defect layer at a predetermined depth in the single-crystal iii-v compound semiconductor substrate; and after the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer are bonded, stripping a part of the single crystal III-V group compound semiconductor base along the defect layer so as to form a thin layer structure on the heterogeneous support substrate.
Further, the method of peeling a portion of the single-crystalline group iii-v compound semiconductor substrate along the defect layer includes subjecting the single-crystalline group iii-v compound semiconductor substrate formed with the defect layer to an annealing treatment.
Optionally, a device structure is formed in the single-crystal group iii-v compound semiconductor substrate, and the material of the first bonding interface is a single-crystal group iii-v compound.
As described above, the method for manufacturing a group iii-v compound semiconductor heterojunction structure of the present invention comprises: providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face; forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface; and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer. Because the surface energy of the alumina film is very high, very high bonding quality can be obtained under the condition of low-temperature bonding, and the alumina film is an amorphous material, has very good absorptivity and permeability to water molecules, and can effectively eliminate gas generated at a bonding interface in the bonding process, therefore, the invention realizes the bonding of the monocrystalline III-V group compound semiconductor and a heterogeneous substrate by forming an alumina dielectric layer on the monocrystalline III-V group compound semiconductor substrate and the heterogeneous support substrate, and can realize a high-quality bonding interface with high bonding strength and no bubbles at the bonding interface.
Drawings
FIG. 1 is a schematic flow chart illustrating a method for fabricating a group III-V compound semiconductor heterojunction structure according to the present invention.
Fig. 2 to 5 are schematic structural views corresponding to steps in a method for fabricating a iii-v compound semiconductor heterojunction structure according to a first embodiment.
Fig. 6 to 9 are schematic structural views corresponding to respective steps in a method of manufacturing a group iii-v compound semiconductor heterojunction structure according to the second embodiment.
Fig. 10 to 13 are schematic structural views corresponding to respective steps in a method of manufacturing a group iii-v compound semiconductor heterojunction structure according to the third embodiment.
Description of the element reference numerals
11 single crystal group III-V compound semiconductor substrate
110-part single-crystal group III-V compound semiconductor substrate
111 residual single crystal group III-V compound semiconductor substrate
12 heterogeneous support substrate
13 first bonding surface
14 second bonding surface
15 first alumina dielectric layer
16 second aluminum oxide dielectric layer
17 defective layer
18 device structure
Thickness of D1 first alumina dielectric layer
Thickness of D2 second alumina dielectric layer
S1-S3
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1, the present invention provides a method for fabricating a group iii-v compound semiconductor heterojunction structure, the method at least comprising the steps of:
step S1: providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face;
step S2: forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;
step S3: and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.
Because the surface energy of the alumina film is very high, very high bonding quality can be obtained under the condition of low-temperature bonding, and the alumina film is an amorphous material, has very good absorptivity and permeability to water molecules, and can effectively eliminate gas generated at a bonding interface in the bonding process, therefore, the invention realizes the bonding of the monocrystalline III-V group compound semiconductor and a heterogeneous substrate by forming an alumina dielectric layer on the monocrystalline III-V group compound semiconductor substrate and the heterogeneous support substrate, and can realize a high-quality bonding interface with high bonding strength and no bubbles at the bonding interface.
As an example, the material of the single-crystalline iii-v group compound semiconductor base may be any one of conventionally known single-crystalline iii-v group compound semiconductors, such as indium phosphide, gallium arsenide, gallium antimonide, indium arsenide, gallium nitride, or the like.
As an example, the heterogeneous support substrate serves as a support substrate for the single-crystal group iii-v compound semiconductor base after subsequent bonding, and the material of the heterogeneous support substrate may be any material known in the art to be suitable for use as a support substrate, such as silicon, silicon oxide, germanium, silicon carbide, gallium arsenide, or the like. The foreign support substrate may also be a single crystal foreign support substrate.
As an example, the first aluminum oxide dielectric layer may be formed by a deposition method such as atomic layer deposition, magnetron sputtering deposition, or chemical vapor deposition; the second aluminum oxide dielectric layer can be formed by adopting deposition methods such as atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition.
By way of example, the thickness of the first alumina dielectric layer is between 2nm and 100nm, and may be, for example, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, or 90 nm. The thickness of the second alumina dielectric layer is between 2nm and 100nm, and for example, the thickness can be 10nm, 20nm, 30nm, 40nm, 50nm, 60nm, 70nm, 80nm or 90 nm.
It should be noted that bonding the first alumina dielectric layer and the second alumina dielectric layer may require subsequent processes on the formed structure, for example, according to different product requirements, the single-crystal iii-v group compound semiconductor substrate or the heterogeneous support substrate may be thinned, or both the single-crystal iii-v group compound semiconductor substrate and the heterogeneous support substrate may be thinned.
The following will further illustrate the fabrication method of the group iii-v compound semiconductor heterojunction structure of the present invention with reference to specific examples.
Example one
As shown in fig. 1 and 2, step S1 is performed to provide a single-crystal iii-v group compound semiconductor base 11 and a heterogeneous support substrate 12, wherein the single-crystal iii-v group compound semiconductor base 11 has a first bonding surface 13, and the heterogeneous support substrate 12 has a second bonding surface 14.
Here, the single-crystal iii-v group compound semiconductor base 11 is a single-crystal substrate piece in which other device structures are not formed.
As shown in fig. 1 and fig. 3, step S2 is performed to form a first aluminum oxide dielectric layer 15 on the first bonding surface 13 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method, and form a second aluminum oxide dielectric layer 16 on the second bonding surface 14 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method.
By way of example, the thickness D1 of the first aluminum oxide dielectric layer is between 20nm and 40nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 20nm and 40 nm.
It should be noted that the formation of the first alumina dielectric layer 15 and the second alumina dielectric layer 16 is not limited by the order, and may be formed simultaneously or sequentially, and is selected according to the actual process conditions.
As shown in fig. 1 and 4, step S3 is performed to bond the first alumina dielectric layer 15 and the second alumina dielectric layer 16.
As shown in fig. 5, after the first alumina dielectric layer 15 and the second alumina dielectric layer 16 are bonded, the single-crystal iii-v group compound semiconductor base 11 and the heterogeneous support substrate 12 need to be thinned by grinding, polishing, and other processes.
Example two
As shown in fig. 1 and 2, step S1 is performed to provide a single-crystal iii-v group compound semiconductor base 11 and a heterogeneous support substrate 12, wherein the single-crystal iii-v group compound semiconductor base 11 has a first bonding surface 13, and the heterogeneous support substrate 12 has a second bonding surface 14.
As shown in fig. 6, ion implantation is performed in the single-crystalline group iii-v compound semiconductor substrate 11 with the first bonding face 13 as an implantation face and an arrow indicating an ion implantation direction, to form a defect layer 17 at a predetermined depth of the single-crystalline group iii-v compound semiconductor substrate 11, the defect layer 17 separating the single-crystalline group iii-v compound semiconductor substrate 11 into a remaining single-crystalline group iii-v compound semiconductor substrate 111 and a part of the single-crystalline group iii-v compound semiconductor substrate 110 on upper and lower sides thereof.
As shown in fig. 1 and fig. 7, step S2 is performed to form a first aluminum oxide dielectric layer 15 on the first bonding surface 13 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method, and form a second aluminum oxide dielectric layer 16 on the second bonding surface 14 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method.
By way of example, the thickness D1 of the first aluminum oxide dielectric layer is between 50nm and 70nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 50nm and 70 nm.
As shown in fig. 1 and 8, step S3 is performed to bond the first alumina dielectric layer 15 and the second alumina dielectric layer 16.
As shown in fig. 9, a portion of the single-crystal group iii-v compound semiconductor base 110 is peeled along the defect layer 17 to leave the single-crystal group iii-v compound semiconductor base 111 remaining on the hetero-support substrate, thereby forming a thin-layer structure, enabling the single-crystal group iii-v compound semiconductor thin-layer structure to be transferred onto the hetero-support substrate 12 using an ion beam peeling technique.
As an example, the method of peeling the portion of the single-crystalline iii-v group compound semiconductor substrate 110 along the defect layer 17 is: annealing the single-crystal group iii-v compound semiconductor substrate 11 on which the defect layer 17 is formed to effect peeling of the portion of the single-crystal group iii-v compound semiconductor substrate 110 along the defect layer 17.
EXAMPLE III
As shown in fig. 1 and 10, step S1 is performed to provide a single-crystal iii-v group compound semiconductor base 11 and a heterogeneous support substrate 12, wherein the single-crystal iii-v group compound semiconductor base 11 has a first bonding surface 13, and the heterogeneous support substrate 12 has a second bonding surface 14. Here, the single-crystal iii-v compound semiconductor substrate 11 has a device structure 18 formed therein, and the material of the first bonding interface 13 is a single-crystal iii-v compound.
As shown in fig. 1 and fig. 11, step S2 is performed to form a first aluminum oxide dielectric layer 15 on the first bonding surface 13 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method, and form a second aluminum oxide dielectric layer 16 on the second bonding surface 14 by using an atomic layer deposition, a magnetron sputtering deposition or a chemical vapor deposition method.
By way of example, the thickness D1 of the first aluminum oxide dielectric layer is between 80nm and 100nm, and the thickness D2 of the second aluminum oxide dielectric layer is between 80nm and 100 nm.
As shown in fig. 1 and 12, step S3 is performed to bond the first alumina dielectric layer 15 and the second alumina dielectric layer 16.
As shown in fig. 13, after the first alumina dielectric layer 15 and the second alumina dielectric layer 16 are bonded, the single-crystal iii-v group compound semiconductor base 11 and the heterogeneous support substrate 12 need to be thinned by grinding, polishing, and other processes.
In summary, the present invention provides a method for fabricating a iii-v compound semiconductor heterojunction structure, comprising: providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face; forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface; and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer. Because the surface energy of the alumina film is very high, very high bonding quality can be obtained under the condition of low-temperature bonding, and the alumina film is an amorphous material, has very good absorptivity and permeability to water molecules, and can effectively eliminate gas generated at a bonding interface in the bonding process, therefore, the invention realizes the bonding of the monocrystalline III-V group compound semiconductor and a heterogeneous substrate by forming an alumina dielectric layer on the monocrystalline III-V group compound semiconductor substrate and the heterogeneous support substrate, and can realize a high-quality bonding interface with high bonding strength and no bubbles at the bonding interface. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method of fabricating a group iii-v compound semiconductor heterojunction structure, the method comprising at least the steps of:
providing a single crystalline group iii-v compound semiconductor base having a first bonding face and a foreign support substrate having a second bonding face;
forming a first aluminum oxide dielectric layer on the first bonding surface, and forming a second aluminum oxide dielectric layer on the second bonding surface;
and bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.
2. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the material of the single-crystal group iii-v compound semiconductor substrate includes one of the group consisting of indium phosphide, gallium arsenide, gallium antimonide, indium arsenide, and gallium nitride.
3. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the material of the heterogeneous support substrate comprises one of the group consisting of silicon, silicon oxide, germanium, silicon carbide, gallium arsenide.
4. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: and the first aluminum oxide dielectric layer is formed by adopting an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method, and the second aluminum oxide dielectric layer is formed by adopting an atomic layer deposition, magnetron sputtering deposition or chemical vapor deposition method.
5. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the thickness of the first aluminum oxide dielectric layer is between 2nm and 100nm, and the thickness of the second aluminum oxide dielectric layer is between 2nm and 100 nm.
6. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: and thinning the monocrystalline III-V group compound semiconductor base and/or the heterogeneous support substrate after bonding the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer.
7. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: the heterogeneous support substrate comprises a single crystal heterogeneous support substrate.
8. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: before forming the first alumina dielectric layer on the first bonding surface, performing ion implantation on the monocrystalline III-V group compound semiconductor substrate from the first bonding surface to form a defect layer at a preset depth in the monocrystalline III-V group compound semiconductor substrate; and after the first aluminum oxide dielectric layer and the second aluminum oxide dielectric layer are bonded, stripping a part of the single crystal III-V group compound semiconductor base along the defect layer so as to form a thin layer structure on the heterogeneous support substrate.
9. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 8, wherein: the method of peeling a portion of the single-crystalline group iii-v compound semiconductor substrate along the defect layer includes annealing the single-crystalline group iii-v compound semiconductor substrate on which the defect layer is formed.
10. The method of fabricating a group iii-v compound semiconductor heterojunction structure of claim 1, wherein: a device structure is formed in the single-crystal iii-v group compound semiconductor substrate, and the material of the first bonding interface is a single-crystal iii-v group compound.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113284839A (en) * | 2021-05-21 | 2021-08-20 | 中国科学院上海微系统与信息技术研究所 | Heterogeneous bonding method and heterogeneous structure of diamond crystals |
| CN113380639A (en) * | 2021-05-26 | 2021-09-10 | 西安交通大学 | Atomic-level ion cleaning activation low-temperature bonding device and method |
| CN115881622A (en) * | 2023-01-29 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Wafer bonding method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060076559A1 (en) * | 2003-07-24 | 2006-04-13 | Bruce Faure | Method of fabricating an epitaxially grown layer |
| CN101005110A (en) * | 2007-01-12 | 2007-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for realizing gallium nitride ELD vertical structure using metal bounding process |
| CN101295753A (en) * | 2007-04-24 | 2008-10-29 | 中国科学院上海微系统与信息技术研究所 | Low temperature Au-In-Au bonding method for III-V family compounds |
| CN102623299A (en) * | 2011-01-31 | 2012-08-01 | 洲磊科技股份有限公司 | Grain process method of wafer bonding |
| CN105895576A (en) * | 2016-07-06 | 2016-08-24 | 中国科学院上海微系统与信息技术研究所 | Method for preparing semiconductor material thick film by ion injection stripping |
-
2019
- 2019-05-31 CN CN201910471852.1A patent/CN112018025A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060076559A1 (en) * | 2003-07-24 | 2006-04-13 | Bruce Faure | Method of fabricating an epitaxially grown layer |
| CN101005110A (en) * | 2007-01-12 | 2007-07-25 | 中国科学院上海微系统与信息技术研究所 | Method for realizing gallium nitride ELD vertical structure using metal bounding process |
| CN101295753A (en) * | 2007-04-24 | 2008-10-29 | 中国科学院上海微系统与信息技术研究所 | Low temperature Au-In-Au bonding method for III-V family compounds |
| CN102623299A (en) * | 2011-01-31 | 2012-08-01 | 洲磊科技股份有限公司 | Grain process method of wafer bonding |
| CN105895576A (en) * | 2016-07-06 | 2016-08-24 | 中国科学院上海微系统与信息技术研究所 | Method for preparing semiconductor material thick film by ion injection stripping |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113284839A (en) * | 2021-05-21 | 2021-08-20 | 中国科学院上海微系统与信息技术研究所 | Heterogeneous bonding method and heterogeneous structure of diamond crystals |
| CN113284839B (en) * | 2021-05-21 | 2024-07-02 | 中国科学院上海微系统与信息技术研究所 | Heterogeneous bonding method and heterostructure of diamond crystal |
| CN113380639A (en) * | 2021-05-26 | 2021-09-10 | 西安交通大学 | Atomic-level ion cleaning activation low-temperature bonding device and method |
| CN115881622A (en) * | 2023-01-29 | 2023-03-31 | 合肥晶合集成电路股份有限公司 | Wafer bonding method |
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