CN111968973B

CN111968973B - BCD semiconductor device

Info

Publication number: CN111968973B
Application number: CN202010884171.0A
Authority: CN
Inventors: 乔明; 张书豪; 李怡; 袁章亦安; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-08-28
Filing date: 2020-08-28
Publication date: 2023-09-22
Anticipated expiration: 2040-08-28
Also published as: CN111968973A

Abstract

The invention provides a BCD semiconductor device integrated with SG-VDMOS, which can integrate twenty kinds of semiconductor devices such as two kinds of JFETs, two kinds of VDMOS, LIGBT, seven kinds of LDMOS, low-voltage NMOS, low-voltage PMOS, low-voltage NPN, low-voltage PNP, four kinds of diodes and the like on one chip at the same time, integrate various transverse and longitudinal devices such as a Bipolar device applied to an analog circuit, a power device in a switch circuit, a CMOS device in a logic circuit and the like together, and greatly improve the chip integration level while saving the cost. Different from the traditional device structure, the integrated device comprises a groove-type JFET, a groove-type LIGBT, a groove-type VDMOS and a fast recovery diode, compared with the conventional VDMOS, the integrated SG-VDMOS can effectively reduce the grid-drain capacitance, reduce the switching loss, improve the switching speed, completely isolate each device through a groove-shaped isolation structure formed by the super junction through the whole drift region, and simultaneously achieve high turn-off voltage resistance and low turn-on resistance.

Description

BCD semiconductor device

Technical Field

The invention belongs to the technical field of semiconductor power devices, and particularly relates to a BCD semiconductor device.

Background

Power integrated ICs are widely used in power management, motor driving, automotive electronics, industrial control, and other fields. BCD refers to a process technology of integrating a Bipolar, CMOS, DMOS high-voltage power device, various resistors, capacitors and diodes into a same chip, and has the characteristics of low cost, easy packaging, easy design, simpler peripheral chips and the like, and is rapidly developed into a mainstream technology in the field of power ICs. Bipolar transistors in BCD technology have high analog precision mainly used in analog circuits, CMOS has high integration mainly used in logic circuits, and DMOS has high power (high voltage) characteristics commonly used as switching. The DMOS mainly used as a switch is a core device of a BCD process, the function of the DMOS requires that the device has high voltage resistance and simultaneously has small specific on-resistance as much as possible, and the driving capability and the area of a chip are directly determined by the performance of the DMOS, so that the design of the DMOS is one of the keys; in addition, the BCD technology integrates devices with different functions on one chip, and the required working environments are different due to the different functions of the devices, so how to isolate the different devices is another key in BCD design. The prior art method is that a polysilicon gate of the DMOS is divided into a control gate and an isolation gate to be respectively introduced, and the isolation gate is utilized to effectively reduce gate-drain capacitance, thereby reducing switching loss and improving switching speed, and each device is completely isolated by penetrating through the whole drift region through a groove-shaped isolation structure formed by a super junction naturally, so that high turn-off voltage resistance and low on resistance can be simultaneously considered.

Disclosure of Invention

The invention aims to provide a BCD semiconductor device and a manufacturing method thereof, which can integrate twenty types of semiconductor devices such as two types of JFETs, two types of VDMOS, LIGBT, seven types of LDMOS, low-voltage NMOS, low-voltage PMOS, low-voltage NPN, low-voltage PNP, four types of diodes and the like on one chip. Different from the traditional device structure, the integrated device comprises a groove type JFET, a groove grid LIGBT, a groove grid VDMOS and a fast recovery diode, compared with the conventional VDMOS, the integrated SG-VDMOS can effectively reduce grid drain capacitance, reduce switching loss, improve switching speed, completely isolate each device through a groove-shaped isolation structure formed by a super junction naturally penetrating through the whole drift region, and can simultaneously achieve high turn-off voltage resistance and low turn-on resistance.

In order to achieve the above purpose, the technical scheme of the invention is as follows:

the BCD semiconductor device comprises a first JFET device 1, a first isolation structure 204, a first VDMOS device 2, a second isolation structure 203, a second VDMOS device 3, a LIGBT device 4, a first LDMOS device 5, a second LDMOS device 6, a third LDMOS device 7, a fourth LDMOS device 8, a fifth LDMOS device 9, a sixth LDMOS device 10, a seventh JFET device 11, a second LDMOS device 12, a low-voltage NMOS device 13, a low-voltage PMOS device 14, a low-voltage PNP device 15, a low-voltage NPN device 16, a first diode 17, a second diode 18, a third diode 19 and a fourth diode 20 which are integrated on the same chip;

The first JFET device 1 includes a plurality of cells with the same structure and sequentially connected, the cells are directly formed on the first doping type substrate 85, the high-voltage drain metal 100 is disposed below the first doping type substrate 85, the drift region includes a first doping type Buffer region 18 at the bottom, the superjunction stripe is located on the upper surface of the first doping type Buffer region 18, the superjunction stripe includes a first doping type stripe 51 and a second doping type stripe 31 which are periodically and alternately arranged, and a third doping type stripe 511 and a second doping type epitaxial layer 311, the first doping type epitaxial layer 512 and the second doping type epitaxial layer 312 are located on the upper surfaces of the third doping type stripe 511 and the second doping type epitaxial layer 311, the upper surface of the first doping type epitaxial layer 512 is provided with a first heavy doping type source region 52, the second doping type epitaxial layer 312 is provided with a fourteenth oxidation layer 623, the upper surface of the trench medium 61 is in contact with the first electrode 101, and the rest surfaces are surrounded by the fourteenth oxidation layer 623, and the first electrode 101 covers the upper surface of the first JFET device 1;

the first type VDMOS device 2 includes a plurality of cells with the same structure and sequentially connected, the cells are directly formed on the first doping type substrate 85, the high-voltage drain metal 100 is disposed below the first doping type substrate 85, the drift region includes a bottom first doping type Buffer region 18 and a superjunction stripe, the superjunction stripe includes a first doping type stripe 51 and a second doping type stripe 31 which are periodically arranged alternately, and a third doping type stripe 511 and a second doping type epitaxial layer 311 which are periodically arranged, the second doping type body region 312 is located on the upper surface of the third doping type stripe 511 and the second doping type epitaxial layer 311, the second doping type body region 312 is embedded with the second doping type contact region 32 and the first heavily doping type contact region 52, the dielectric layer 62 covers the first type gate oxide layer 610 and a part of the first heavily doping type contact region 52, the first metal layer 102 covers the upper surface of the dielectric layer 62 and the exposed first heavily doping type contact region 52, the first doping type contact region 32 is located on the upper surface of the trench gate oxide layer 62 and the second doping type epitaxial layer 311, the second doping type body region 312 is located on the upper surface of the first type gate oxide layer 610 and is located on the lower surface of the first type gate oxide layer 610, and the first doping type contact layer 610 is surrounded by the first type gate oxide layer 610; the upper surface of the first type polysilicon control gate 701 extends into the first heavily doped type contact region 52, the lower surface extends into the third doped type strip 511, the cell 2 (n) at the rightmost side of the first type VDMOS is of a terminal structure, the second type metal layer 103 covers the dielectric layer 62 and part of the upper surface of the second type polysilicon separation gate 703, and the periphery of the second type polysilicon separation gate 703 is surrounded by the first type gate oxide layer 610;

The first isolation structure 204 is located between the last cell 1 (n) of the first JFET device 1 and the first cell 2 (1) of the first VDMOS device, and is directly formed on the first doping type substrate 85, the high-voltage drain metal 100 is located under the first doping type substrate 85, the drift region includes a first doping type Buffer region 18 at the bottom and a superjunction stripe located on the upper surface of the first doping type Buffer region 18, wherein the superjunction stripe includes a first doping type stripe 51 and a second doping type stripe 31 that are periodically arranged, and a third doping type stripe 511 and a second doping type epitaxial layer 311 that are periodically arranged on the upper surfaces of the first doping type stripe 51 and the second doping type stripe 31, the first doping type epitaxial layer 512 and the second doping type body region 312 are located on the upper surfaces of the third doping type stripe 511 and the second doping type epitaxial layer 311, the stripe structure formed by the second doping type stripe 31 and the second doping type epitaxial layer 311 penetrates through the whole drift region, the second doping type body region 312 belonging to the first isolation structure 204 is covered with the second doping type body region 86, and the whole field isolation structure is covered with the field isolation layer 86;

The second-type VDMOS device 3 includes a plurality of cells with the same structure and sequentially connected, the cells are directly formed on the first doping type substrate 85, the high-voltage drain metal 100 is disposed below the first doping type substrate 85, the drift region includes a bottom first doping type Buffer region 18 and a superjunction stripe, the superjunction stripe includes a first doping type stripe 51 and a second doping type stripe 31 which are periodically arranged alternately, and a third doping type stripe 511 and a second doping type epitaxial layer 311 which are periodically arranged, the second doping type body region 312 is located on the upper surface of the third doping type stripe 511 and the second doping type epitaxial layer 311, the second doping type body region 312 is embedded with the second doping type contact region 32 and the first heavily doping type contact region 52, the dielectric layer 62 covers the first-type gate oxide layer 610 and a part of the first heavily doping type contact region 52, the third-type metal layer 104 covers the upper surfaces of the dielectric layer 62 and the exposed first heavily doping type contact region 52 and the first heavily doping type contact region 32, the first-type gate oxide layer 62 and the first-type contact region 610 are located on the upper surface of the third doping type stripe 511 and the second doping type epitaxial layer 311, the second doping type body region 312 is located on the upper surface of the first-type gate oxide layer 610 and is located on the lower surface of the first-type gate layer 610, and the first-type gate oxide layer 610 is surrounded by the first-type gate oxide layer 610; the upper surface of the first type polysilicon control gate 701 extends into the first heavy doping type contact region 52, and the lower surface extends into the third doping type strip 511; the depletion type channels 543 are distributed on two sides of the first type gate oxide layer 610 and are longitudinally communicated with the first heavily doped type contact region 52 and the third doped type strip 511;

The second isolation structure 203 is located between the last terminal cell 2 (n) of the first type VDMOS device 2 and the first cell 3 (1) of the second type VDMOS device 3, and is directly formed on the first doping type substrate 85, the high-voltage drain metal 100 is located under the first doping type substrate 85, the drift region includes a first doping type Buffer region 18 and a superjunction strip at the bottom, the superjunction strip includes a first doping type strip 51 and a second doping type strip 31 that are periodically and alternately arranged, the first doping type strip 51 and the second doping type strip 31 are located on the upper surface of the first doping type Buffer region 18 in parallel, the third doping type strip 511 and the second doping type epitaxial layer 311 that are periodically arranged are located on the upper surfaces of the first doping type strip 51 and the second doping type strip 31, the first doping type epitaxial layer 512 and the second doping type epitaxial layer 312 are located on the upper surfaces of the third doping type strip 511 and the second doping type epitaxial layer 311, the strip structure formed by the second doping type strip 31 and the second doping type epitaxial layer 311 penetrates through the whole drift region 203, the second doping type strip structure 86 and the second doping type epitaxial layer 86 is covered with the surface of the second doping type epitaxial layer 86, and the surface of the second doping type epitaxial layer 86 is covered with the second doping type epitaxial layer 86 and the surface of the isolation structure;

The right side of the last cell 3 (n) of the second-type VDMOS device 3 is sequentially provided with a LIGBT device 4, a first-type LDMOS device 5, a second-type LDMOS device 6, a third-type LDMOS device 7, a fourth-type LDMOS device 8, a fifth-type LDMOS device 9, a sixth-type LDMOS device 10, a seventh-type LDMOS device 11, a second-type JFET device 12, a low-voltage NMOS device 13, a low-voltage PMOS device 14, a low-voltage PNP15, a low-voltage NPN device 16 and a diode 17; the devices on the right side of the last cell 3 (n) of the second-type VDMOS device 3 are all located in a second doping type epitaxial layer 311, the second doping type epitaxial layer 311 is located on the upper surface of a first doping type strip 51 and a second doping type strip 31 which are alternately arranged periodically, a field oxide layer 86 on the upper surface of the isolation strip 21 and a dielectric layer 62 covering the upper surface of the field oxide layer 86 form an isolation strip structure, and the isolation strip structure separates a LIGBT device 4, a first-type LDMOS device 5, a second-type LDMOS device 6, a third-type LDMOS device 7, a fourth-type LDMOS device 8, a fifth-type LDMOS device 9, a sixth-type LDMOS device 10, a seventh-type LDMOS device 11, a second-type JFET device 12, a low-voltage NMOS device 13, a low-voltage PMOS device 14, a low-voltage PNP15, a low-voltage NPN device 16, a first-type diode 17, a second-type diode 18, a third-type diode 19 and a fourth-type diode 20 from each other;

The LIGBT device 4 is located between two adjacent spacer structures on the right side of the last cell 3 (n) of the second VDMOS device 3, the first doping type buried layer 500 is located on the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type buried layer 500 between two adjacent spacers 21, and the second doping type well region 320 is disposed on the left side of the first doping type epitaxial layer 512; the second doping type well region 320 is provided with a tangential first heavy doping type contact region 52 and a tangential second heavy doping type contact region 32 near the upper surface; the right side of the first doping type epitaxial layer 512 is provided with a first doping type first well region 520; a second heavily doped contact region 32 is disposed near the upper surface in the middle of the first doped first well region 520; a field oxide layer 86 is provided on a portion of the upper surface of the first doping type epitaxial layer 512; the third gate oxide layer 612 is located between the spacer structure and the second doping type well region 320 and tangential to the left boundary of the second doping type well region 320; the third type of polysilicon 72 is located within the third type of gate oxide 612, which is surrounded by the third type of gate oxide 612; the upper surfaces of the third type gate oxide layer 612 and the upper surface of the field oxide layer 86 are covered with the dielectric layer 62, the first type emitter metal 105 covers the upper surfaces of part of the first heavy doping type contact region 52 and part of the second heavy doping type contact region 32, and the upper surface of the second heavy doping type contact region 32 near the upper surface in the middle of the first doping type first well region 520 is covered with the first type collector metal 106;

The first LDMOS device 5 is positioned on the right side of the LIGBT device 4 and is separated from the adjacent LIGBT device 4 by a spacer structure; the first LDMOS device 5 is located in the second doping type epitaxial layer 311, a first doping type first buried layer 501 is disposed at a portion of the upper surface of the second doping type epitaxial layer 311, a first doping type epitaxial layer 512 is disposed above the first doping type first buried layer 501 between two adjacent isolation bars 21, a second doping type first deep well region 301 is disposed at the upper surface of the first doping type epitaxial layer 512, a first doping type second well region 521 is disposed at the left side of the second doping type first deep well region 301, a first doping type field-reducing layer 550 is tangential to the first doping type second well region 521 and is located under the first doping type second well region 521, a first heavy doping type contact region 52 is disposed near the upper surface of the first doping type second well region 521, and a second heavy doping type contact region 32 is tangential to the first heavy doping type contact region 52; a second heavily doped type contact region 32 is arranged at the right upper surface of the second doped type first deep well region 301, a part of field oxide layer 86 is arranged at the upper surface of the second doped type first deep well region 301, a space is reserved between the field oxide layer 86 at the upper surface of the second doped type first deep well region 301 and the first doped type second well region 521, a fourth type gate oxide layer 613 is connected with the left boundary of the second heavily doped type contact region 32 and the field oxide layer 86 at the upper surface of the first doped type second well region 521, the fourth type gate oxide layer 613 is tangential to the right boundary of the second heavily doped type contact region 32, a fourth type polysilicon layer 73 is covered at the upper surface of the fourth type gate oxide layer 613, the left end of the fourth type polysilicon layer 73 is tangential to the fourth type gate oxide layer 613 or does not extend to the left boundary of the fourth type gate oxide layer 613, the left end of the fourth type polysilicon layer 73 covers or is tangential to the right boundary of the second doped type contact region 86, and the right side of the fourth type polysilicon layer 73 covers part of the field oxide layer 86; the exposed parts of the fourth type gate oxide layer 613, the upper surface of the fourth type polysilicon layer 73 and the exposed upper surface of the field oxide layer 86 are covered with the dielectric layer 62, the upper surfaces of the first heavy doping type contact region 52 and part of the second heavy doping type contact region 32 which are positioned on the upper surface of the first doping type second well region 521 are covered with the second type source metal 107, and the upper surface of the second heavy doping type source region 32 which is positioned on the right side of the second doping type first deep well region 301 and is close to the upper surface is covered with the second type drain metal 108;

The second type LDMOS device 6 is separated from the adjacent first type LDMOS device 5 by a spacer structure; the second LDMOS device 6 is provided with a first doping type second buried layer 502 at a part of the upper surface of the second doping type epitaxial layer 311, a first doping type epitaxial layer 512 is positioned above the first doping type second buried layer 502, a second doping type first buried layer 401 is positioned right above the first doping type second buried layer 502, a second doping type first well region 321 is arranged at the first doping type epitaxial layer 512, a second doping type first field lowering layer 42 is positioned right below the second doping type first well region 321 and is tangential to the second doping type first well region 321, a first doping type third well region 522 is arranged at the first doping type epitaxial layer 512 and is provided with a first heavily doping type contact region 52 at the position close to the upper surface, a field oxidation layer 86 is arranged at the position right above the first doping type epitaxial layer 512, a space is arranged between the field oxide layer 86 and the second doping type first well region 321 right above the first doping type epitaxial layer 512, a fifth type gate oxide layer 614 connects the first heavy doping type source region 52 and the left boundary of the field oxide layer 86 at the upper surface of the second doping type first well region 321, the thickness of the fifth type gate oxide layer 614 is larger than that of the fourth type gate oxide layer 613 of the first type LDMOS device 5, the left end part of the fifth type gate oxide layer 614 covers or is tangent to the right boundary of the first heavy doping type contact region 52, the upper surface of the fifth type gate oxide layer 614 is covered with the fifth type polysilicon layer 74, the left side of the fifth type polysilicon layer 74 is tangent or does not extend to the left boundary of the fifth type gate oxide layer 614, and covers or is tangent to the right boundary of the first heavy doping type contact region 52, the right end part of the fifth type polysilicon layer 74 covers the field oxide layer 86, the dielectric layer 62 covers the exposed part of the fifth type gate oxide layer 614, the upper surface of the fifth polysilicon layer 74 and the exposed upper surface of the field oxide 86, the third source metal 109 covers part of the upper surface of the first heavily doped contact region 52 in the second doped first well region 321, the upper surface of the second heavily doped contact region 32 tangential to the left side of the first heavily doped contact region 52, the third drain metal 111 covers the first heavily doped contact region 52 on the right side, and the first field plate metal 110 partially covers the upper surface of the fifth polysilicon layer 74 on the right side;

The third type LDMOS device 7 is separated from the adjacent second type LDMOS device 6 by a spacer structure, the third type N-channel LDMOS device 7 is provided with a first doping type third buried layer 503 on a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type third buried layer 503, a field oxide layer 86 is disposed directly above the first doping type epitaxial layer 512, a second doping type second well region 322 is disposed at the left side of the first doping type epitaxial layer 512, a second doping type third field-lowering layer 43 is located directly below the second doping type second well region 322 and tangential to the second doping type second well region 322, a first doping type fourth well region 523 is disposed at the right side of the first doping type epitaxial layer 512, and a first heavy doping type contact region 52 is disposed inside the first doping type fourth well region 523 near the upper surface; a space is arranged between the field oxide layer 86 above the first doping type epitaxial layer 512 and the second doping type second well region 322, a sixth type gate oxide layer 615 connects the first heavily doping type contact region 52 located at the upper surface of the second doping type second well region 322 with the left boundary of the field oxide layer 86, the left end part of the sixth type gate oxide layer 615 covers or is tangential to the right boundary of the first heavily doping type contact region 52, the upper surface of the sixth type gate oxide layer 615 is covered with a sixth type polysilicon layer 75, the left end of the sixth type polysilicon layer 75 is tangential or does not extend to the left boundary of the sixth type gate oxide layer 615, and covers or is tangential to the right boundary of the first heavily doping type contact region 52, and the right side of the sixth type polysilicon layer 75 covers part of the field oxide layer 86; dielectric layer 62 covers the exposed portion of sixth-type gate oxide layer 615, the upper surface of sixth-type polysilicon layer 75, and the exposed upper surface of field oxide layer 86, fourth-type source metal 112 covers the upper surfaces of left-side portions of first heavily doped type contact region 52 and heavily doped type contact region 32, fourth-type drain metal 114 covers right-side portions of first heavily doped type contact region 52, and second-type field plate electrode metal 113 covers right-side portions of the upper surface of sixth-type polysilicon layer 75;

The fourth LDMOS device 8 is separated from the adjacent third LDMOS device 7 by a spacer structure, the fourth LDMOS device 8 is provided with a first doping type fourth buried layer 504 at a portion of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type fourth buried layer 504, a second doping type top layer 402 is provided directly above the first doping type epitaxial layer 512, a field oxide layer 86 is provided above the second doping type top layer 402, a second doping type third well region 323 is provided at the left side of the first doping type epitaxial layer 512, the second doping type fourth field-down layer 44 is located directly below the second doping type third well region 323 and tangent to the second doping type third well region 323, a first doping type fifth well region 524 is provided at the right side of the first doping type epitaxial layer 512 and a first heavy doping type contact region 52 is provided inside the first doping type fifth well region close to the upper surface; a space is arranged between the field oxide layer 86 above the second doping type top layer 402 and the second doping type third well region 323, a seventh type gate oxide layer 616 connects the first heavy doping type contact region 52 located at the upper surface of the second doping type third well region 323 with the left boundary of the field oxide layer 86, the left end part of the seventh type gate oxide layer 616 covers or is tangential to the right boundary of the first heavy doping type contact region 52, the upper surface of the seventh type gate oxide layer 616 is covered with a seventh type polysilicon layer 76, the left end of the seventh type polysilicon layer 76 is tangential or does not extend to the left boundary of the seventh type gate oxide layer 616, and covers or is tangential to the right boundary of the first heavy doping type contact region 52, and the seventh type polysilicon layer 76 covers part of the field oxide layer 86; dielectric layer 62 covers the exposed portion of seventh gate-like oxide layer 616, the upper surface of seventh polysilicon layer 76, and the exposed upper surface of field oxide layer 86, fifth source-like metal 115 covers the upper surfaces of portions of first and second heavily doped contact regions 52 and 32, fifth drain-like metal 117 covers first heavily doped contact region 52 on the right side, and third field plate electrode metal 116 covers the upper surface of portion of seventh polysilicon layer field plate 76 on the right side;

The fifth type LDMOS device 9 is separated from the adjacent fourth type LDMOS device 8 by a spacer structure; the fifth LDMOS device 9 is provided with a first doping type fifth buried layer 505 at a part of the upper surface of the second doping type epitaxial layer 311, the second doping type buried layer 403 is located above the first doping type fifth buried layer 505, a field oxide layer 86 is located above the second doping type buried layer 403, a second doping type fourth well region 324 is located at the left side of the first doping type epitaxial layer 512, a second doping type fifth field-down layer 45 is located right below the second doping type fourth well region 324 and tangential to the second doping type fourth well region 324, a first doping type sixth well region 525 is located at the right side of the first doping type epitaxial layer 512 and a first heavy doping type contact region 52 is located near the upper surface in the first doping type sixth well region 525; a space is arranged between the field oxide layer 86 and the second doping type fourth well region 324, an eighth type gate oxide layer 617 is connected with the left boundary between the first heavy doping type contact region 52 and the field oxide layer 86 at the upper surface of the second doping type fourth well region 324, the left end part of the eighth type gate oxide layer 617 covers or is tangential to the right boundary of the first heavy doping type contact region 52, the upper surface of the eighth type gate oxide layer 617 is covered with an eighth type polysilicon layer 77, the left end of the eighth type polysilicon layer 77 is tangential or does not extend to the left boundary of the eighth type gate oxide layer 617, and covers or is tangential to the right boundary of the first heavy doping type contact region 52, and the right side of the eighth type polysilicon layer 77 covers part of the eighth type field oxide layer 86; dielectric layer 62 covers the exposed portion of eighth type gate oxide layer 617, the upper surface of eighth type polysilicon layer 77, and the exposed upper surface of field oxide layer 86, sixth type source metal 118 covers a portion of first heavily doped type contact region 52 and second heavily doped type contact region 32, sixth type drain metal 120 covers a portion of first heavily doped type contact region 52 on the right side of first doped type epitaxial layer 512, and fourth type field plate electrode metal 119 covers a portion of polysilicon 77 on the right side;

The sixth type LDMOS device 10 is separated from the adjacent fifth type LDMOS device 9 by a spacer structure; the sixth LDMOS device 10 is provided with a first doping type sixth buried layer 506 at the upper surface of a portion of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type sixth buried layer 506, a field oxide layer 86 is disposed above the first doping type epitaxial layer 512, a second doping type fifth well region 325 is disposed at the left side of the first doping type epitaxial layer 512, the second doping type sixth reduced field layer 46 is tangential to the second doping type fifth well region 325 and is located right below the second doping type fifth well region 325, a first doping type seventh well region 526 is disposed at the right side of the first doping type epitaxial layer 512 and is provided with a first heavily doping type contact region 52 near the upper surface thereof, a gap is disposed between the field oxide layer 86 above the first doping type epitaxial layer 512 and the second doping type fifth well region 325, a ninth gate oxide layer 618 is connected with the left boundary between the first heavily doping type contact region 52 and the field oxide layer 86 located right side of the upper surface of the second doping type fifth well region 325, the ninth gate oxide layer 618 covers the left boundary or the ninth gate oxide layer 618 covers the first polysilicon layer 78 or the right side boundary 78, and the ninth polysilicon layer 78 is tangential to the ninth polysilicon layer boundary or the ninth polysilicon boundary 78; the dielectric layer 62 covers the exposed part of the ninth type gate oxide layer 618, the upper surface of the ninth type polysilicon layer 78 and the exposed upper surface of the field oxide layer 86, the seventh type source metal 121 covers the upper surfaces of the first heavily doped type contact region 52 and the second heavily doped type contact region 32 on the left side of the first doped type epitaxial layer 512, and the seventh type drain metal 122 covers the first heavily doped type contact region 52 on the right side of the first doped type epitaxial layer 512;

The seventh type of LDMOS device 11 is separated from the adjacent sixth type of LDMOS device 10 by a spacer structure; the seventh LDMOS device 11 is provided with a first doping type seventh buried layer 507 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type seventh buried layer 507, the left side of the first doping type epitaxial layer 512 is provided with a second doping type sixth well region 326, the second doping type seventh field-down layer 47 is located right below the second doping type sixth well region 326 and is tangential to the second doping type sixth well region 326, the right side of the first doping type epitaxial layer 512 is provided with a first heavy doping type contact region 52, the tenth gate oxide 619 covers the right boundary of the first heavy doping type contact region 52, the upper surface of the tenth gate oxide 619 is covered with a tenth polysilicon layer 79, the left end of the tenth polysilicon layer 79 is tangential or does not extend to the left boundary of the tenth gate oxide 619, and covers or is tangential to the right boundary of the first heavy doping type contact region 52; the dielectric layer 62 covers the exposed part of the tenth type gate oxide layer 619, the upper surface of the tenth type polysilicon layer 79, and the exposed upper surface of the field oxide layer 86, the eighth type source metal 123 covers the upper surfaces of the second heavily doped type contact region 32 and the first heavily doped type contact region 52 on the left side of the first doped type epitaxial layer 512, and the eighth type drain metal 124 covers the first heavily doped type contact region 52 on the right side of the first doped type epitaxial layer 512;

The second JFET device 12 is separated from the adjacent seventh LDMOS device 11 by a spacer structure; the second JFET device 12 is provided with a first doping type epitaxial layer 512 on a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is provided with a second heavily doping type contact region 32 near the middle of the upper surface, the left and right sides of the second heavily doping type contact region 32 are symmetrically provided with first heavily doping type contact regions 52, the first heavily doping type contact region 52 and the second heavily doping type contact region 32 are separated in the horizontal direction by a field oxide layer 86, a dielectric layer 62 is covered above the field oxide layer 86, a fourth metal layer 125 covers the first heavily doping type contact region 52 on the left side of the second heavily doping type contact region 32, a fifth metal layer 126 covers the second heavily doping type contact region 32, and a sixth metal layer 127 covers the first heavily doping type contact region 52 on the right side of the second heavily doping type contact region 32;

the low-voltage NMOS device 13 is separated from the adjacent JFET devices 12 of the second type by a spacer structure; the low-voltage NMOS device 13 is provided with a first buried layer 508 of a first doping type at the upper surface of a portion of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first buried layer 508 of the first doping type, the second deep well region 302 of the second doping type is located above the first doping type epitaxial layer 512, the first heavy doping type contact region 52 and the second heavy doping type contact region 32 are provided at the left side of the second deep well region 302 of the second doping type, the first heavy doping type contact region 52 is provided at the right side of the second deep well region 302 of the second doping type, the upper surfaces of two adjacent first heavy doping type contact regions 52 are connected through an eleventh type gate oxide layer 620, the two ends of the tenth type gate oxide layer 620 are tangent to or cover a portion of the first heavy doping type contact region 52, the eleventh type polysilicon layer 80 covers the upper surface of the tenth type gate oxide layer 620, the dielectric layer 62 covers the eleventh type polysilicon layer 80, the first body region metal layer 128 covers the second heavy doping type contact region 32, the ninth type metal layer 129 covers the second heavy doping type contact region 52 of the second heavy doping type contact region 302 of the second heavy doping type contact region 52 of the second doping type, and the ninth type polysilicon layer 80 covers the second heavy doping type contact region 52 of the second heavy doping type contact region of the left side;

The low-voltage PMOS device 14 is separated from the adjacent low-voltage NMOS device 13 by a spacer structure; the low-voltage PMOS device 14 is provided with a first doping type ninth buried layer 509 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type ninth buried layer 509, the first doping type deep well region 5102 is located above the first doping type epitaxial layer 512, the left side of the first doping type deep well region 5102 is provided with a first heavy doping type contact region 52 and a second heavy doping type contact region 32, the right side of the first doping type deep well region 5102 is provided with a second heavy doping type contact region 32, the upper surfaces of two adjacent second heavy doping type contact regions 32 are connected through a twelfth type gate oxide layer 621, two ends of the tenth type gate oxide layer 621 are tangent or cover part of the second heavy doping type contact region 32, the twelfth type polysilicon layer 81 covers the upper surface of the twelfth type gate oxide layer 621, the medium layer 62 covers the upper surface of the twelfth type polysilicon layer 81, the second body region metal layer 131 covers the first heavy doping type contact region 52, the tenth type metal 132 covers the second heavy doping type deep well region 2, and the tenth type metal layer 132 covers the left side of the second heavy doping type contact region 51032;

The PNP device 15 is separated from the adjacent low-voltage PMOS device 14 by a spacer structure; the PNP device 15 is provided with a first doping type tenth buried layer 510 at the upper surface of a portion of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type tenth buried layer 510, two first heavily doping type contact regions 52 and two second heavily doping type contact regions 32 are arranged above the first doping type epitaxial layer 512, the first heavily doping type contact regions 52 and the second heavily doping type contact regions 32 are alternately distributed and have equal intervals, the leftmost side of the first doping type epitaxial layer 512 is the first heavily doping type contact region 52, the surfaces of the adjacent first heavily doping type contact region 52 and the adjacent second heavily doping type contact region 32 are isolated by the field oxide layer 86, the two second heavily doping type contact regions 32 are surrounded by the second doping type third deep well region 303, the seventh metal layer 134 covers the upper surface of the leftmost first heavily doping type contact region 52, the eighth metal layer 135 covers the middle second doping type contact region 32, the ninth metal layer 136 covers the middle first heavily doping type contact region 52, and the tenth metal layer 137 covers the rightmost doping type contact region 32;

The NPN device 16 is separated from the adjacent PNP device 15 through a spacer structure; the NPN device 16 is provided with a first doping type eleventh buried layer 5101 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the first doping type eleventh buried layer 5101, a second doping type fourth deep well region 304 is disposed at the upper left side of the first doping type epitaxial layer 512, a first heavy doping type contact region 52 and a second heavy doping type contact region 32 isolated by a field oxide layer 86 are disposed at the upper surface of the second doping type fourth deep well region 304, a dielectric layer 62 is covered on the upper surface of the field oxide layer 86, a first heavy doping type contact region 52 is disposed at the upper surface of the first doping type epitaxial layer 512 on the right side outside the second doping type fourth deep well region 304, a second heavy doping type contact region 52 and a second doping type fourth deep well region 304 are isolated by the field oxide layer 86, a first heavy doping type contact region 52 inside the fourth well region 304 is covered by the dielectric layer 62, a thirteenth metal layer 139 covers the first heavy doping type contact region 52 inside the fourth doping type deep well region 304, and a thirteenth metal layer 138 covers the fourth doping type contact region 140 outside the fourth doping type deep well region 304;

The first type diode device 17 is separated from the adjacent PNP device 16 by a spacer structure; the first diode device 17 is provided with a second doping type third buried layer 313 at the upper surface of a portion of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the second doping type third buried layer 313, two sides of the first doping type epitaxial layer 512 are respectively provided with a second doping type fifth deep well region 305, the lower surface of the second doping type fifth well region 305 is deep into the second doping type third buried layer 313, the upper surface of the second doping type fifth well region 305 is provided with a second heavily doping type contact region 32, two second heavily doping type contact regions 32 and a first heavily doping type contact region 52 arranged at the middle of the second heavily doping type contact region 32 are located on the upper surface of the first doping type epitaxial layer 512, the first heavily doping type contact region 52 and the surfaces of two second heavily doping type contact regions 32 adjacent to the first heavily doping type epitaxial layer are separated by a field oxide layer 86, the upper surface of the field oxide layer 86 is covered with a dielectric layer 62, a fourteenth metal layer 141 covers the second heavily doping type contact region 32 on the left side, a fifteenth metal 142 covers the first heavily doping type contact region 52 on the right side, and a sixteenth metal layer covers the second doping type contact region 32 on the right side;

The second type diode device 18 is separated from the adjacent first type diode device 17 by a spacer structure; the second diode device 18 is provided with a second doping type fourth buried layer 314 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the second doping type fourth buried layer 314, two first heavily doped type contact regions 52 are provided at the upper surface of the first doping type epitaxial layer 512, the upper surface of the field oxide layer 86 is covered with a dielectric layer 62, a seventeenth metal layer 144 covers the first heavily doped type contact region 52 on the left side, an eighteenth metal layer 145 covers a part of the upper surface of the first doping type epitaxial layer 512, and a nineteenth metal layer 146 covers the first heavily doped type contact region 52 on the right side;

the third type diode device 19 is separated from the adjacent second type diode device 18 by a spacer structure; the third diode device 19 is provided with a second doping type fifth buried layer 315 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the second doping type fifth buried layer 315, two first heavily doping type contact regions 52 and two second heavily doping type contact regions 32 are provided at the upper surface of the first doping type epitaxial layer 512, a space is provided between the two second heavily doping type contact regions 32 and between the adjacent field oxide layers 86, the upper surface of the field oxide layer 86 is covered with a dielectric layer 62, the twenty-second metal layer 147 covers a part of the upper surface of the first doping type epitaxial layer 512, the twenty-second metal layer 149 covers the first heavily doping type contact region 52 on the right side;

The fourth type of diode device 20 is separated from the adjacent third type of diode device 19 by a spacer structure; the fourth diode device 20 is provided with a second doping type sixth buried layer 316 at a part of the upper surface of the second doping type epitaxial layer 311, the first doping type epitaxial layer 512 is located above the second doping type sixth buried layer 316, two first heavy doping type contact regions 52, two thirteenth oxide layers 622 and two sixth polysilicon 709 are provided at the upper surface of the first doping type epitaxial layer 512, two thirteenth oxide layers 622 are located between the two first heavy doping type contact regions 52, a space is provided between the two thirteenth oxide layers 622, a field oxide layer 86 is provided between the first heavy doping type contact regions 52 and the thirteenth oxide layers 622, a dielectric layer 62 is covered on the upper surface of the field oxide layer 86, the sixth polysilicon 709 is located on the inner upper surface of the thirteenth oxide layer 622, the upper surfaces of the two sixth polysilicon 709 are in contact with the twenty-fourth metal layer 151, the rest surfaces are surrounded by the thirteenth oxide layer 622, the twenty-third metal layer 150 covers the left side first heavy doping type contact regions 52, the thirteenth metal layer 151 covers the upper surfaces of the thirteenth oxide layers 709, and the upper surfaces of the thirteenth metal layer 151 cover the thirteenth metal layer 512.

Preferably, the spacer 21 is formed by a filling medium.

Preferably, the first doping type stripes 51 and the second doping type stripes 31 of the device periodic arrangement are formed by grooving filling.

Preferably, a thin layer of dielectric 63 is provided between the first doping type stripes 51 and the second doping type stripes 31 of the device periodic arrangement.

Preferably, the first doping type stripes 51 and the second doping type stripes 31 of the device periodic arrangement are directly disposed on the first doping type substrate 85, and the first doping type Buffer region 18 is removed.

Preferably, the devices 4-20 on the right side of the second type VDMOS device 3 are isolated from the directly underlying second doping type epitaxy 311 by a dielectric.

Preferably, the control gates 701 in the first-type VDMOS device 2 and the second-type VDMOS device 3 are replaced by two vertical separated polysilicon control gates 704.

Preferably, the split gate 702 in the first and second type VDMOS devices 2 and 3 is replaced by two split third type polysilicon split gates 705 in the vertical direction.

Preferably, the control gates 701 in the first and second VDMOS devices 2 and 3 are replaced by two laterally separated third polysilicon control gates 706, and the separation gate 702 is replaced by a fourth polysilicon separation gate 707, and the fourth polysilicon separation gate 707 passes through the two separated third polysilicon control gates 706 and contacts the first and third metal layers 102 and 104 above.

Preferably, the upper ends of the terminal structures 2 (n) of the first-type VDMOS devices 2 are covered by the field oxide 86, and the fifth-type polysilicon split gate 708 is surrounded by the first-type gate oxide 610.

The beneficial effects of the invention are as follows: the invention realizes the monolithic integration of the first type JFET, the first type VDMOS, the second type VDMOS, the LIGBT, the seven types of LDMOS, the second type JFET, NMOS, PMOS, the NPN, the PNP and the four types of diodes on the substrate. The drift region part is composed of first doping type strips and second doping type strips which are alternately arranged periodically, the first doping type strips and the second doping type strips form transverse junctions, a longitudinal electric field can be modulated when the voltage is reversely resisted, higher voltage resistance can be born, the modulation effect of the transverse junctions enables the doping concentration of the first doping type strips playing a role in conducting to be improved, the current capacity of the first JFET device 1, the first VDMOS device 2 and the second VDMOS device 3 is greatly improved, and the high voltage resistance of the device is realized while the conductivity is enhanced; the last epitaxy type of the drift region superjunction strip is changed, so that the transverse device and the high-voltage superjunction longitudinal device can be monolithically integrated together, and the manufacturing cost of the chip is reduced. In addition, by utilizing the process of forming the second doped well region compatible with the first-type JFET device 1, the first-type VDMOS device 2 and the second-type VDMOS device 3, the groove-shaped isolation structure of the devices 4-17 on the right side of the second-type VDMOS device 3 is realized, so that the devices are well isolated, and meanwhile, the overall performance of the chip is improved. The first-type JFET device 1, the first-type VDMOS device 2 and the second-type VDMOS device 3 are formed by alternately forming impurities of the first doping type and impurities of the second doping type to penetrate through the whole drift region to naturally form an isolation structure, so that longitudinal devices with different functions can work independently and are not affected by each other. The invention integrates the high-voltage device and the transverse device together without increasing the process cost, thereby greatly reducing the process cost. Compared with a conventional integrated high-voltage semiconductor device, the high-voltage semiconductor device provided by the invention has smaller on-resistance under the condition of the same chip area (or smaller chip area under the condition of the same on-capability), and the formed high-voltage power integrated circuit can be used in various products such as consumer electronics, display drive and the like. The inherent gate-drain capacitance of the DMOS device largely determines the switching frequency and switching loss of the device, and the gate-drain capacitance can be reduced to a certain extent by dividing the conventional polysilicon gate into a control gate (control gate) and a split gate (split gate), so that the switching loss is reduced and the switching frequency is increased. In addition to the conventional PiN diode, the process also integrates a schottky diode that can be used in a fast switching circuit with lower forward turn-on voltage, faster reverse recovery characteristics.

Drawings

Fig. 1 (a) -1 (d) are schematic structural diagrams of embodiment 1.

Fig. 2 (a) -2 (d) are schematic structural diagrams of embodiment 2.

Fig. 3 (a) -3 (d) are schematic structural diagrams of embodiment 3.

Fig. 4 (a) -4 (d) are schematic structural diagrams of embodiment 4.

Fig. 5 (a) -5 (d) are schematic structural diagrams of embodiment 5.

Fig. 6 is a schematic structural diagram of embodiment 6.

Fig. 7 is a schematic structural diagram of embodiment 7.

Fig. 8 is a schematic structural view of embodiment 8.

Fig. 9 is a schematic structural view of embodiment 9.

Wherein 1 is a first type JFET device, 204 is a first isolation structure, 2 is a first type VDMOS device, 203 is a second isolation structure, 3 is a second type VDMOS device, 4 is a LIGBT device, 5 is a first type LDMOS device, 6 is a second type LDMOS device, 7 is a third type LDMOS device, 8 is a fourth type LDMOS device, 9 is a fifth type LDMOS device, 10 is a sixth type LDMOS device, 11 is a seventh type LDMOS device, 12 is a second type JFET device, 13 is a low-voltage NMOS device, 14 is a low-voltage PMOS device, 15 is a low-voltage PNP,16 is a low-voltage NPN device, 17 is a first type diode, 18 is a second type diode, 19 is a third type diode, and 20 is a fourth type diode; 18 is a first doping type Buffer region, 85 is a first doping type substrate, 86 is a field oxide layer, 1 (1) -1 (n) is a cell of a first type JFET device 1, 2 (1) -2 (n) is a cell of a first type VDMOS device 2, 3 (1) -3 (n) is a cell of a second type VDMOS device 3, 51 is a first doping type strip, 31 is a second doping type strip, 511 is a third doping type strip, 311 is a second doping type epitaxial layer, 610-621 is a first to twelfth type gate oxide layer, 622-623 is a thirteenth to fourteenth type oxide layer, 701 is a first type polysilicon control gate, 702 is a first type polysilicon separation gate, 703 is a second type polysilicon separation gate, 704 is a second type polysilicon control gate, is a third type polysilicon separation gate, 706 is a third type polysilicon control gate, 707 is a fourth type polysilicon separation gate, 708 is a fifth type polysilicon split gate, 709 is a sixth type polysilicon, 72-81 is a third to twelfth type polysilicon layer, 512 is a first doping type epitaxial layer, 52 is a first heavily doping type source region, 32 is a second heavily doping type source region, 543 is a first lightly doping type depletion type channel region, 100 is a high voltage drain metal, 101 is a first electrode, 102-104 is a first to third type metal layer, 105 is a first type source metal, 106 is a first type drain metal, 107 is a second type source metal, 108 is a second type drain metal, 109 is a third type source metal, 111 is a third type drain metal, 110 is a first type field plate electrode metal, 112 is a fourth type source metal, 114 is a fourth type drain metal, 113 is a second type field plate electrode metal, 115 is a fifth type source metal, 116 is a third type field plate electrode metal, 117 is a fifth type drain electrode metal, 118 is a sixth type source electrode metal, 119 is a fourth type field plate electrode metal, 120 is a sixth type drain electrode metal, 121 is a seventh type source electrode metal, 122 is a seventh type drain electrode metal, 123 is an eighth type source electrode metal, 124 is a seventh type drain electrode metal, 125 is a fourth type metal layer, 126 is a fifth type metal layer, 127 is a sixth type metal layer, 128 is a first type body region metal layer, 129 is a ninth type source electrode metal, 130 is a ninth type drain electrode metal, 131 is a second type body region metal layer, 132 is a tenth type source electrode metal, 133 is a tenth type drain electrode metal, 134 is a seventh type metal layer, 135 is an eighth type metal layer, 136 is a ninth type metal layer, 137 is a tenth type metal layer, 138 is an eleventh type metal layer, 139 is a twelfth type metal layer, 140 is a thirteenth type metal layer, 141 is a fourteenth type metal layer, 142 is a fifteenth metal layer, 143 is a sixteenth metal layer, 144 is a seventeenth metal layer, 145 is an eighteenth metal layer, 146 is a nineteenth metal layer, 147 is a twentieth metal layer, 148 is a twentieth metal layer, 149 is a twenty-second metal layer, 150 is a twenty-third metal layer, 151 is a twenty-fourth metal layer, 152 is a twenty-fifth metal layer, 62 is a dielectric layer, 312 is a second doping type bulk region, 21 is a spacer, 500 is a first doping type buried layer, 501-510 is a first doping type first buried layer to a first doping type tenth buried layer, 5101 is a first doping type eleventh buried layer, 320 is a second doping type well region, 321-325 is a second doping type first well region to a fifth well region, 401 is a second doping type first buried layer, 402 is a second doping type top layer, 403 is a second doping type buried layer, 313-316, 301-305, 520-526, 550, 42-47, 61, 63, 82 and 82 respectively are second doping type third to seventh field-down layers.

Example 1

As shown in fig. 1 (a) -1 (d):

The spacer 21 is formed by a filling medium.

Example 2

As shown in fig. 2 (a) -2 (d): the difference between this embodiment and embodiment 1 is that:

the first doping type stripes 51 and the second doping type stripes 31 of the device periodic arrangement are formed by trench filling.

Example 3

As shown in fig. 3 (a) -3 (d): the difference between this embodiment and embodiment 1 is that:

the device is periodically arranged with a thin layer of dielectric 63 between the first doping type stripes 51 and the second doping type stripes 31.

Example 4

As shown in fig. 4 (a) -4 (d): the difference between this embodiment and embodiment 1 is that:

the first doping type strips 51 and the second doping type strips 31 of the device periodic arrangement are directly arranged on the first doping type substrate 85, and the first doping type Buffer region 18 is removed.

Example 5

As shown in fig. 5 (a) -5 (d), the present embodiment differs from embodiment 1 in that:

the devices 4-20 on the right side of the second type VDMOS device 3 are isolated from the directly underlying second doping type epi 311 by a dielectric.

Example 6

As shown in fig. 6, the present embodiment differs from embodiment 1 in that: the control gates 701 in the first and second type VDMOS devices 2, 3 are replaced by two vertically separated second type polysilicon control gates 704.

Example 7

As shown in fig. 7, the present embodiment differs from embodiment 1 in that: the split gate 702 in the first and second type VDMOS devices 2, 3 is replaced by two split third type polysilicon split gates 705 in the vertical direction.

Example 8

As shown in fig. 8, the present embodiment differs from embodiment 1 in that: the control gates 701 in the first and second VDMOS devices 2 and 3 are replaced by two laterally separated third polysilicon control gates 706, the separation gate 702 is replaced by a fourth polysilicon separation gate 707, and the fourth polysilicon separation gate 707 passes through the two separated third polysilicon control gates 706 and contacts the first and third metal layers 102 and 104 above. .

Example 9

As shown in fig. 9, the present embodiment differs from embodiment 1 in that: the upper ends of the terminal structures 2 (n) of the first-type VDMOS devices 2 are covered by the field oxide 86, and the fifth-type polysilicon split gates 708 are surrounded by the first-type gate oxide 610.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims of this invention, which are within the skill of those skilled in the art, can be made without departing from the spirit and scope of the invention disclosed herein.

Claims

1. A BCD semiconductor device characterized by: the semiconductor device comprises a first JFET device (1), a first isolation structure (204), a first VDMOS device (2), a second isolation structure (203), a second VDMOS device (3), a LIGBT device (4), a first LDMOS device (5), a second LDMOS device (6), a third LDMOS device (7), a fourth LDMOS device (8), a fifth LDMOS device (9), a sixth LDMOS device (10), a seventh LDMOS device (11), a second JFET device (12), a low-voltage NMOS device (13), a low-voltage PMOS device (14), a low-voltage PNP device (15), a low-voltage NPN device (16), a first diode (17), a second diode (18), a third diode (19) and a fourth diode (20) which are integrated on the same chip;

the first JFET device (1) comprises a plurality of cells which are identical in structure and are sequentially connected, the cells are directly arranged on a first doping type substrate (85), high-voltage drain metal (100) is arranged below the first doping type substrate (85), a drift region comprises a first doping type Buffer region at the bottom, a superjunction strip is arranged on the upper surface of the first doping type Buffer region, the superjunction strip comprises first doping type strips (51) and second doping type strips (31) which are periodically and alternately arranged, a third doping type strip (511) and a second doping type epitaxial layer (311), the first doping type epitaxial layer (512) and the second doping type epitaxial layer (312) are arranged on the upper surfaces of the third doping type strip (511) and the second doping type epitaxial layer (311), a first heavy doping type source region (52) is arranged on the upper surface of the first doping type epitaxial layer (512), a fourteenth oxide layer (623) is arranged on the second doping type epitaxial layer (312), the upper surface of the trench medium (61) is in contact with the first electrode (101), and the upper surface of the first JFET device (101) is surrounded by the first electrode (623);

The first-type VDMOS device (2) comprises a plurality of cells which are identical in structure and sequentially connected, the cells are directly arranged on a first doping type substrate (85), a high-voltage drain metal (100) is arranged below the first doping type substrate (85), a drift region comprises a first doping type Buffer region and a superjunction strip which comprise a first doping type strip (51) and a second doping type strip (31) which are periodically arranged in an alternating manner, and a third doping type strip (511) and a second doping type epitaxial layer (311) which are periodically arranged, a second doping type body region (312) is positioned on the upper surfaces of the third doping type strip (511) and the second doping type epitaxial layer (311), a second doping type body region (312) is internally provided with a second heavily doping type contact region (32) and a first heavily doping type contact region (52), a dielectric layer (62) covers a first-type gate oxide layer (610) and part of the first heavily doping type contact region (52), a first-type metal layer (102) covers the dielectric layer (62) and the first heavily-doped type contact region (62) and is positioned on the upper surface of the first-type gate region (610) and is surrounded by the first-type contact layer (610) and the upper surface of the first-type contact region (610) and the first-type contact region (62) is tangential to the upper surface of the first-type gate layer (610), the first type polysilicon separation gate (702) is positioned at the lower part in the first type gate oxide layer (610) and is surrounded by the first type gate oxide layer (610); the upper surface of the first type polycrystalline silicon control gate (701) is deep into the first heavy doping type contact region (52), the lower surface is deep into the third doping type strip (511), the cell 2 (n) at the rightmost side of the first type VDMOS is of a terminal structure, the second type metal layer (103) covers the dielectric layer (62) and part of the upper surface of the second type polycrystalline silicon separation gate (703), and the periphery of the second type polycrystalline silicon separation gate (703) is surrounded by the first type gate oxide layer (610);

The first isolation structure (204) is located between the last cell 1 (n) of the first JFET device (1) and the first cell 2 (1) of the first VDMOS device, and is directly formed on the first doping type substrate (85), the high-voltage drain metal (100) is located below the first doping type substrate (85), the drift region comprises a first doping type Buffer region at the bottom and a superjunction strip located on the upper surface of the first doping type Buffer region, the superjunction strip comprises a first doping type strip (51) and a second doping type strip (31) which are periodically and alternately arranged, and a third doping type strip (511) and a second doping type epitaxial layer (311) which are periodically arranged on the upper surfaces of the first doping type strip (51) and the second doping type strip (31), the first doping type epitaxial layer (512) and the second doping type body region (312) are located on the upper surfaces of the third doping type strip (511) and the second doping type epitaxial layer (311), the second doping type strip (31) and the second doping type epitaxial layer (311) are located on the upper surfaces of the first doping type epitaxial layer (512), the second doping type strip (31) and the second doping type epitaxial layer (311) are located on the whole surface of the first doping type epitaxial layer (86), the second doping type strip (86) is formed by oxidizing the whole isolation structure, and the first isolation structure (86) covers the drift region is formed by the whole surface of the isolation structure (86;

The second-type VDMOS device (3) comprises a plurality of cells which are identical in structure and sequentially connected, the cells are directly arranged on a first doping type substrate (85), a high-voltage drain metal (100) is arranged below the first doping type substrate (85), the drift region comprises a first doping type Buffer region and a superjunction strip at the bottom, the superjunction strip comprises a first doping type strip (51) and a second doping type strip (31) which are periodically arranged, a third doping type strip (511) and a second doping type epitaxial layer (311) which are periodically arranged, a second doping type body region (312) is positioned on the upper surfaces of the third doping type strip (511) and the second doping type epitaxial layer (311), a second heavily doping type body region (312) is internally provided with a second heavily doping type contact region (32) and a first heavily doping type contact region (52), a dielectric layer (62) covers a first type gate oxide layer (610) and part of the first heavily doping type contact region (52), a third metal layer (104) covers the dielectric layer (62) and the first heavily doping type contact region (62) and is positioned on the upper surface of the first doping type contact region (610) and is surrounded by the first heavily doping type contact region (610) and the first heavily doping type contact region (52), the second doping type contact region (312) is tangential to the upper surface of the first doping type contact region (610), the first type polysilicon separation gate (702) is positioned at the lower part in the first type gate oxide layer (610) and is surrounded by the first type gate oxide layer (610); the upper surface of the first type polysilicon control gate (701) stretches into the first heavy doping type contact region (52), and the lower surface stretches into the third doping type strip (511); the depletion type channels (543) are distributed on two sides of the first-type gate oxide layer (610) and are longitudinally communicated with the first heavy doping type contact region (52) and the third doping type strip (511);

The second isolation structure (203) is located between the last terminal cell 2 (n) of the first-type VDMOS device (2) and the first cell 3 (1) of the second-type VDMOS device (3), and is directly formed on the first doping type substrate (85), the high-voltage drain metal (100) is arranged below the first doping type substrate (85), the drift region comprises a first doping type Buffer region and a superjunction strip at the bottom, the superjunction strip comprises a first doping type strip (51) and a second doping type strip (31) which are periodically and alternately arranged, the first doping type strip (51) and the second doping type strip (31) are arranged side by side on the upper surface of the first doping type Buffer region, the third doping type strip (511) and the second doping type epitaxial layer (311) which are periodically arranged are located on the upper surface of the first doping type strip (51) and the second doping type strip (31), the first doping type epitaxial layer (512) and the second doping type body region (312) are located on the upper surface of the third doping type strip (511) and the second doping type strip (311) which are periodically arranged, the whole surface isolation structure (203) is formed by covering the second doping type epitaxial layer (31) and the whole surface isolation structure (203) of the drift region, the dielectric layer (62) covers the field oxide layer (86);

The right side of the last cell 3 (n) of the second VDMOS device (3) is sequentially provided with a LIGBT device (4), a first LDMOS device (5), a second LDMOS device (6), a third LDMOS device (7), a fourth LDMOS device (8), a fifth LDMOS device (9), a sixth LDMOS device (10), a seventh LDMOS device (11), a second JFET device (12), a low-voltage NMOS device (13), a low-voltage PMOS device (14), a low-voltage PNP (15), a low-voltage NPN device (16) and a diode; the devices on the right side of the last cell 3 (n) of the second-type VDMOS device (3) are all located in a second doping type epitaxial layer (311), the second doping type epitaxial layer (311) is located on the upper surface of a first doping type strip (51) and a second doping type strip (31) which are alternately arranged in a periodic manner, a field oxide layer (86) on the upper surface of the isolation strip (21) and a medium layer (62) covering the upper surface of the field oxide layer (86) form an isolation strip structure, and the isolation strip structure separates a LIGBT device (4), a first-type LDMOS device (5), a second-type LDMOS device (6), a third-type LDMOS device (7), a fourth-type LDMOS device (8), a fifth-type LDMOS device (9), a sixth-type LDMOS device (10), a seventh-type device (11), a second-type JFET device (12), a low-voltage NMOS device (13), a low-voltage PMOS device (14), a low-voltage PNP (15), a low-voltage device (16), a second-type diode (17) and a fourth-type LDMOS device (20) from each other;

The LIGBT device (4) is positioned between two adjacent isolation strip structures on the right side of the last cell 3 (n) of the second-type VDMOS device (3), the first doping type buried layer (500) is positioned on the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the first doping type buried layer (500) between two adjacent isolation strips (21), and a second doping type well region (320) is arranged on the left side of the first doping type epitaxial layer (512); a tangential first heavy doping type contact region (52) and a tangential second heavy doping type contact region (32) are arranged on the second doping type well region (320) close to the upper surface; the right side of the first doping type epitaxial layer (512) is provided with a first doping type first well region (520); a second heavy doping type contact region (32) is arranged at the middle of the first doping type first well region (520) close to the upper surface; a field oxide layer (86) is arranged on the upper surface of part of the first doping type epitaxial layer (512); a third gate oxide layer (612) is located between the spacer structure and the second doping type well region (320) and tangential to the left boundary of the second doping type well region (320); a third type of polysilicon (72) is located within the third type of gate oxide (612), surrounded by the third type of gate oxide (612); the upper surfaces of the third type gate oxide layer (612) and the upper surface of the field oxide layer (86) are covered with a dielectric layer (62), the first type emitter metal (105) covers part of the upper surfaces of the first heavy doping type contact region (52) and part of the second heavy doping type contact region (32), and the upper surface of the second heavy doping type contact region (32) close to the upper surface at the middle of the first doping type first well region (520) is covered with the first type collector metal (106);

The first LDMOS device (5) is positioned on the right side of the LIGBT device (4) and is separated from the adjacent LIGBT device (4) through a spacer structure; the first LDMOS device (5) is positioned in the second doping type epitaxial layer (311), a first doping type first buried layer (501) is arranged on the upper surface of a part of the second doping type epitaxial layer (311), a first doping type epitaxial layer (512) is arranged above the first doping type first buried layer (501) between two adjacent isolation strips (21), a second doping type first deep well region (301) is arranged on the upper surface of the first doping type epitaxial layer (512), a first doping type second well region (521) is arranged on the left side of the second doping type first deep well region (301), a first doping type field-reducing layer (550) is tangential to the first doping type second well region (521) under the first doping type second well region, and a first heavy doping type contact region (52) and a second heavy doping type contact region (32) tangential to the first heavy doping type contact region (52) are arranged on the position of the first doping type second well region (521) close to the upper surface; a second heavily doped type contact region (32) is arranged at the upper surface of the right side of the second doped type first deep well region (301), a part of field oxide layer (86) is arranged at the upper surface of the second doped type first deep well region (301), a space is reserved between the field oxide layer (86) of the upper surface of the second doped type first deep well region (301) and the first doped type second well region (521), a fourth type gate oxide layer (613) is connected with the left boundary of the field oxide layer (86) and the second heavily doped type contact region (32) which is positioned at the upper surface of the first doped type second well region (521), the fourth type gate oxide layer (613) is tangential to the right boundary of the second heavily doped type contact region (32), a fourth type polysilicon layer (73) is covered at the upper surface of the fourth type gate oxide layer (613), the left end of the fourth type polysilicon layer (73) is tangential to the fourth type gate oxide layer (613) or does not extend to the left boundary of the fourth type gate oxide layer (613), and the fourth type polysilicon layer (73) is tangential to the right boundary of the fourth type polysilicon layer (73) which is covered at the right side of the fourth type gate oxide layer (613); the exposed part of the fourth type gate oxide layer (613), the upper surface of the fourth type polysilicon layer (73), the exposed upper surface of the field oxide layer (86) is covered with a dielectric layer (62), the upper surfaces of the first heavy doping type contact region (52) and part of the second heavy doping type contact region (32) which are positioned on the upper surface of the first doping type second well region (521) are covered with a second type source metal (107), and the upper surface of the second heavy doping type contact region (32) which is positioned on the right side of the second doping type first deep well region (301) and is close to the upper surface is covered with a second type drain metal (108);

The second type LDMOS device (6) is separated from the adjacent first type LDMOS device (5) through a spacer structure; the second LDMOS device (6) is provided with a first doping type second buried layer (502) at the part upper surface of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is arranged above the first doping type second buried layer (502), the second doping type first buried layer (401) is arranged right above the first doping type second buried layer (502), the upper left part of the first doping type epitaxial layer (512) is provided with a second doping type first well region (321), the second doping type second reduced field layer (42) is arranged right below the second doping type first well region (321) and tangential to the second doping type first well region (321), the first doping type epitaxial layer (512) is provided with a first doping type third well region (522) at the right side and is provided with a first heavy doping type contact region (52) at the position close to the upper surface, the first doping type epitaxial layer (512) is provided with a field oxide layer (86), the field oxide layer (86) right above the first doping type epitaxial layer (512) is arranged right above the first doping type epitaxial layer (321) and is connected with a fifth doping type well region (614) at a position of a fifth doping type (614) which is larger than the first doping type well region (614), the left end part of the fifth type gate oxide layer (614) covers or is tangential to the right boundary of the first heavy doping type contact region (52), a fifth type polysilicon layer (74) is covered at the upper surface of the fifth type gate oxide layer (614), the left side of the fifth type polysilicon layer (74) is tangential or does not extend to the left boundary of the fifth type gate oxide layer (614), and covers or is tangential to the right boundary of the first heavy doping type contact region (52), the right end of the fifth type polysilicon layer (74) covers part of the field oxide layer (86), the dielectric layer (62) covers the exposed part of the fifth type gate oxide layer (614), the upper surface of the fifth type polysilicon layer (74) and the exposed upper surface of the field oxide layer (86), the third type source metal (109) covers part of the upper surface of the first heavy doping type contact region (52) in the second doping type first well region (321) and the upper surface of the second heavy doping type contact region (32) tangential to the left side of the first heavy doping type contact region (52), and the third type source metal (109) covers part of the upper surface of the third type polysilicon layer (110);

The third type LDMOS device (7) is separated from the adjacent second type LDMOS device (6) through a spacer structure, a first doping type third buried layer (503) is arranged on the upper surface of a part of the second doping type epitaxial layer (311), a first doping type epitaxial layer (512) is arranged above the first doping type third buried layer (503), a field oxide layer (86) is arranged right above the first doping type epitaxial layer (512), a second doping type second well region (322) is arranged on the left side of the first doping type epitaxial layer (512), a second doping type third field dropping layer (43) is arranged right below the second doping type second well region (322) and tangential to the second doping type second well region (322), and a first heavy doping type contact region (52) is arranged on the right side of the first doping type epitaxial layer (512) and near the upper surface inside the first doping type fourth well region (523); a space is arranged between a field oxide layer (86) above the first doping type epitaxial layer (512) and a second doping type second well region (322), a sixth type gate oxide layer (615) is connected with a left boundary between a first heavy doping type contact region (52) and the field oxide layer (86) at the upper surface of the second doping type second well region (322), the left end part of the sixth type gate oxide layer (615) covers or is tangential to the right boundary of the first heavy doping type contact region (52), the upper surface of the sixth type gate oxide layer (615) is covered with a sixth type polysilicon layer (75), the left end of the sixth type polysilicon layer (75) is tangential or does not extend to the left boundary of the sixth type gate oxide layer (615), and covers or is tangential to the right boundary of the first heavy doping type contact region (52), and the right side of the sixth type polysilicon layer (75) covers part of the field oxide layer (86); the dielectric layer (62) covers the exposed part of the sixth type gate oxide layer (615), the upper surface of the sixth type polysilicon layer (75) and the exposed upper surface of the field oxide layer (86), the fourth type source metal (112) covers the upper surfaces of the left part of the first heavy doping type contact region (52) and the second heavy doping type contact region (32), the fourth type drain metal (114) covers the right part of the first heavy doping type contact region (52), and the second type field plate electrode metal (113) covers the right part of the upper surface of the sixth type polysilicon layer (75);

The fourth type LDMOS device (8) is separated from the adjacent third type LDMOS device (7) through a spacer structure, the fourth type LDMOS device (8) is provided with a first doping type fourth buried layer (504) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the first doping type fourth buried layer (504), a second doping type top layer (402) is arranged right above the first doping type epitaxial layer (512), a field oxide layer (86) is arranged above the second doping type top layer (402), a second doping type third well region (323) is arranged on the left side of the first doping type epitaxial layer (512), a second doping type fourth reduced field layer (44) is positioned right below the second doping type third well region (323) and tangential to the second doping type third well region (323), a first doping type fifth well region (524) is arranged on the right side of the first doping type epitaxial layer (512) and a second doping type contact well region (52) is arranged inside the first doping type fifth well region (524) near the upper surface; a space is arranged between the field oxide layer (86) above the second doping type top layer (402) and the second doping type third well region (323), a seventh gate-like oxide layer (616) is connected with the left boundary of the field oxide layer (86) and the first heavy doping type contact region (52) at the upper surface of the second doping type third well region (323), the left end part of the seventh gate-like oxide layer (616) is covered or tangent to the right boundary of the first heavy doping type contact region (52), a seventh polysilicon-like layer (76) is covered at the upper surface of the seventh gate-like oxide layer (616), the left end of the seventh polysilicon-like layer (76) is tangent or not extended to the left boundary of the seventh gate-like oxide layer (616), and is covered or tangent to the right boundary of the first heavy doping type contact region (52), and the seventh polysilicon-like layer (76) covers part of the field oxide layer (86); the dielectric layer (62) covers the exposed part of the seventh gate-like oxide layer (616), the upper surface of the seventh polysilicon layer (76) and the exposed upper surface of the field oxide layer (86), the fifth source-like metal (115) covers part of the first heavily doped contact region (52) and part of the upper surface of the second heavily doped contact region (32), the fifth drain-like metal (117) covers the first heavily doped contact region (52) on the right side, and the third field plate electrode metal (116) covers part of the upper surface of the seventh polysilicon layer field plate (76) on the right side;

The fifth type LDMOS device (9) is separated from the adjacent fourth type LDMOS device (8) through a spacer structure; the fifth LDMOS device (9) is provided with a first doping type fifth buried layer (505) at the part upper surface of the second doping type epitaxial layer (311), the second doping type buried layer (403) is located above the first doping type fifth buried layer (505), a field oxide layer (86) is arranged above the second doping type buried layer (403), a second doping type fourth well region (324) is arranged at the left side of the first doping type epitaxial layer (512), a second doping type fifth field dropping layer (45) is located right below the second doping type fourth well region (324) and tangential to the second doping type fourth well region (324), a first doping type sixth well region (525) is arranged at the right side of the first doping type epitaxial layer (512), and a first heavy doping type contact region (52) is arranged in the first doping type sixth well region (525) close to the upper surface; a space is arranged between the field oxide layer (86) and the second doping type fourth well region (324), an eighth type gate oxide layer (617) is connected with the left boundary between the first heavy doping type contact region (52) positioned on the upper surface of the second doping type fourth well region (324) and the field oxide layer (86), the left end part of the eighth type gate oxide layer (617) covers or is tangential to the right boundary of the first heavy doping type contact region (52), an eighth type polysilicon layer (77) is covered on the upper surface of the eighth type gate oxide layer (617), the left end of the eighth type polysilicon layer (77) is tangential or does not extend to the left boundary of the eighth type gate oxide layer (617), and covers or is tangential to the right boundary of the first heavy doping type contact region (52), and the right side of the eighth type polysilicon layer (77) covers part of the eighth type field oxide layer (86); the dielectric layer (62) covers the exposed part of the eighth type gate oxide layer (617), the upper surface of the eighth type polysilicon layer (77) and the exposed upper surface of the field oxide layer (86), the sixth type source metal (118) covers part of the first heavy doping type contact region (52) and the second heavy doping type contact region (32), the sixth type drain metal (120) covers part of the first heavy doping type contact region (52) on the right side of the first doping type epitaxial layer (512), and the fourth type field plate electrode metal (119) covers part of the polysilicon layer (77) on the right side;

The sixth type LDMOS device (10) is separated from the adjacent fifth type LDMOS device (9) through a spacer structure; the sixth LDMOS device (10) is provided with a first doping type sixth buried layer (506) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is arranged above the first doping type sixth buried layer (506), a field oxide layer (86) is arranged above the first doping type epitaxial layer (512), the left side of the first doping type epitaxial layer (512) is provided with a second doping type fifth well region (325), the second doping type sixth drop field layer (46) is tangential to the right side of the second doping type fifth well region (325), the first doping type epitaxial layer (512) is provided with a first doping type seventh well region (526) at the right side of the first doping type epitaxial layer and is provided with a first heavy doping type contact region (52) at the position close to the upper surface of the first doping type epitaxial layer, a gap is arranged between the field oxide layer (86) above the first doping type epitaxial layer (512) and the second doping type fifth well region (325), a ninth gate oxide layer (618) is connected with the first doping type fifth well region (325) at the position of the right side of the second doping type fifth well region and is tangential to the first heavy doping type contact region (618) at the boundary layer (78), the ninth doping type epitaxial layer (618) is tangential to the left side of the ninth doping type epitaxial layer (618) and covers the first doping type contact region (52), the left end of the ninth type polycrystalline silicon layer (78) is tangential or not extended to the left boundary of the ninth type gate oxide layer (618) and covers or is tangential to the right boundary of the first heavy doping type contact region (52), and the right end of the ninth type polycrystalline silicon layer (78) covers part of the ninth type field oxide layer (86); the dielectric layer (62) covers the exposed part of the ninth type gate oxide layer (618), the upper surface of the ninth type polysilicon layer (78) and the exposed upper surface of the field oxide layer (86), the seventh type source metal (121) covers the upper surfaces of the first heavily doped type contact region (52) and the second heavily doped type contact region (32) on the left side of the first doped type epitaxial layer (512), and the seventh type drain metal (122) covers the first heavily doped type contact region (52) on the right side of the first doped type epitaxial layer (512);

The seventh type LDMOS device (11) is separated from the adjacent sixth type LDMOS device (10) by a spacer structure; the seventh LDMOS device (11) is provided with a first doping type seventh buried layer (507) at the part upper surface of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the first doping type seventh buried layer (507), the left side of the first doping type epitaxial layer (512) is provided with a second doping type sixth well region (326), the second doping type seventh field dropping layer (47) is positioned right below the second doping type sixth well region (326) and tangent to the second doping type sixth well region (326), the right side of the first doping type epitaxial layer (512) is provided with a first heavy doping type contact region (52), the tenth type gate oxide layer (619) covers the right boundary of the first heavy doping type contact region (52), the upper surface of the tenth type gate oxide layer (619) is covered with a tenth polysilicon layer (79), the left end of the tenth type polysilicon layer (79) is tangent or does not extend to the left boundary of the tenth type gate oxide layer (619), and the tenth type polysilicon layer (79) is covered with the right boundary of the first heavy doping type contact region (52); the dielectric layer (62) covers the exposed part of the tenth type gate oxide layer (619), the upper surface of the tenth type polysilicon layer (79) and the exposed upper surface of the field oxide layer (86), the eighth type source metal (123) covers the upper surfaces of the first heavily doped type contact region (52) and the second heavily doped type contact region (32) on the left side of the first doped type epitaxial layer (512), and the eighth type drain metal (124) covers the first heavily doped type contact region (52) on the right side of the first doped type epitaxial layer (512);

The second type JFET device (12) is separated from the adjacent seventh type LDMOS device (11) by a spacer structure; the second-type JFET device (12) is characterized in that a first doping type epitaxial layer (512) is arranged on the upper surface of a part of the second doping type epitaxial layer (311), a second heavily doping type contact region (32) is arranged on the position, close to the right middle of the upper surface, of the first doping type epitaxial layer (512), first heavily doping type contact regions (52) are symmetrically arranged on the left side and the right side of the second heavily doping type contact region (32), the first heavily doping type contact region (52) and the second heavily doping type contact region (32) are isolated in the horizontal direction through a field oxide layer (86), a dielectric layer (62) is covered above the field oxide layer (86), a fourth-type metal layer (125) covers the first heavily doping type contact region (52) on the left side of the second heavily doping type contact region (32), a fifth-type metal layer (126) covers the second heavily doping type contact region (32), and a sixth-type metal layer (127) covers the first heavily doping type contact region (52) on the right side of the second heavily doping type contact region (32);

the low-voltage NMOS device (13) is separated from the adjacent second-type JFET devices (12) through a spacer structure; the low-voltage NMOS device (13) is provided with a first doping type eighth buried layer (508) at the part upper surface of the second doping type epitaxial layer 311), the first doping type epitaxial layer (512) is positioned above the first doping type eighth buried layer (508), a second doping type second deep well region (302) is arranged above the first doping type epitaxial layer (512), a first heavy doping type contact region (52) and a second heavy doping type contact region (32) are arranged at the left side of the second doping type second deep well region (302), a first heavy doping type contact region (52) is arranged at the right side of the second doping type second deep well region (302), the upper surfaces of two adjacent first heavy doping type contact regions (52) are connected through an eleventh type gate oxide layer (620), two ends of the tenth type gate oxide layer (620) are tangent or cover a part of the first heavy doping type contact region (52), an eleventh type polysilicon layer (80) covers the upper surface of the eleventh type gate oxide layer (620), a dielectric layer (62) covers the upper surface of the eleventh type contact region (52), a second heavy doping type contact region (128) covers the second heavy doping type contact region (128), the ninth drain metal layer (130) covers the first heavy doping type contact region (52) on the right side of the second doping type second deep well region (302);

The low-voltage PMOS device (14) is separated from the adjacent low-voltage NMOS device (13) through a spacer structure; the low-voltage PMOS device (14) is provided with a first doping type ninth buried layer (509) at the part upper surface of the second doping type epitaxial layer (311), a first doping type epitaxial layer (512) is positioned above the first doping type ninth buried layer (509), a first doping type deep well region (5102) is positioned above the first doping type epitaxial layer (512), a first heavy doping type contact region (52) and a second heavy doping type contact region (32) are arranged at the left side of the first doping type deep well region (5102), a second heavy doping type contact region (32) is arranged at the right side of the first doping type deep well region (5102), the upper surfaces of two adjacent second heavy doping type contact regions (32) are connected through a twelfth type gate oxide layer (621), two ends of the second tenth gate oxide layer (621) or a part of the second heavy doping type contact region (32) is tangential, a twelfth type polysilicon layer (81) covers the upper surface of the twelfth type gate oxide layer (621), a medium layer (62) covers the upper surface of the twelfth type contact region (52), a second heavy doping type contact region (132) is covered by the second heavy doping type contact region (81), the tenth-type drain metal (133) covers the second-doped-type contact region (32) on the right side of the first-doped-type deep well region (5102);

The low-voltage PNP device (15) is separated from the adjacent low-voltage PMOS device (14) through a spacer structure; the low-voltage PNP device (15) is provided with a first doping type tenth buried layer (510) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the first doping type tenth buried layer (510), two first heavy doping type contact areas (52) and two second heavy doping type contact areas (32) are arranged above the first doping type epitaxial layer (512), the first heavy doping type contact areas (52) and the second heavy doping type contact areas (32) are alternately distributed and have equal intervals, the leftmost side of the first doping type epitaxial layer (512) is the first heavy doping type contact area (52), the surfaces of the adjacent first heavy doping type contact areas (52) and second heavy doping type contact areas (32) are isolated through a field oxide layer (86), the two second heavy doping type contact areas (32) are surrounded by a second doping type third deep well area (303), a seventh metal layer (134) covers the upper surface of the leftmost first heavy doping type contact area (52), an eighth metal layer (135) covers the middle metal layer (32) and a ninth metal layer (137) covers the second heavy doping type contact area (32);

The low-voltage NPN device (16) is separated from the adjacent low-voltage PNP device (15) through a spacer structure; the low-voltage NPN device (16) is provided with a first doping type eleventh buried layer (5101) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the first doping type eleventh buried layer (5101), the upper left side of the first doping type epitaxial layer (512) is provided with a second doping type fourth deep well region (304), the upper surface of the second doping type fourth deep well region (304) is provided with a first heavy doping type contact region (52) and a second heavy doping type contact region (32) which are isolated by a field oxide layer (86), the upper surface of the field oxide layer (86) is covered with a dielectric layer (62), the upper surface of the first doping type epitaxial layer (512) at the right side outside of the second doping type fourth deep well region (304) is provided with a first heavy doping type contact region (52), a first heavy doping type contact region (52) outside the second doping type fourth deep well region (304) is arranged between the first heavy doping type contact region (52) and the second doping type fourth well region (304) through a field oxide layer (86), the inner part of the fourth doping type contact region (32) is covered with a metal layer (138) which covers the inner part of the second doping type contact region (32), the thirteenth metal-like layer (140) covers the first heavily doped type contact region (52) outside the fourth deep well region (304);

The first diode device (17) is separated from the adjacent low-voltage NPN device (16) through a spacer structure; the first diode device (17) is provided with a second doping type third buried layer (313) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is positioned above the second doping type third buried layer (313), two sides of the first doping type epitaxial layer (512) are respectively provided with a second doping type fifth deep well region (305), the lower surface of the second doping type fifth deep well region (305) is deep into the second doping type third buried layer (313), the upper surface of the second doping type fifth deep well region (305) is provided with a second doping type contact region (32), two second doping type contact regions (32) and a first heavily doping type contact region (52) arranged at the right middle of the second doping type contact region (32) are positioned on the upper surface of the first doping type epitaxial layer (512), the surfaces of the first heavily doping type contact region (52) and two second heavily doping type contact regions (32) adjacent to the first heavily doping type epitaxial layer are isolated through a field oxide layer (86), the upper surface of the field oxide layer (86) is covered with a second heavily doping type contact region (62), the left side of the second heavily doping type contact region (52) is covered with a sixteen-doped metal layer (141), and the second heavily doping type contact region (32) is covered with a left side of a second heavily doping type contact region (52);

The second type diode device (18) is separated from the adjacent first type diode device (17) by a spacer structure; the second-type diode device (18) is provided with a second doping type fourth buried layer (314) at the part upper surface of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is located above the second doping type fourth buried layer (314), two first heavy doping type contact areas (52) are arranged at the upper surface of the first doping type epitaxial layer (512), a dielectric layer (62) is covered on the upper surface of the field oxide layer (86), a seventeenth metal layer (144) covers the first heavy doping type contact areas (52) on the left side, an eighteenth metal layer (145) covers part upper surface of the first doping type epitaxial layer (512), and a nineteenth metal layer (146) covers the first heavy doping type contact areas (52) on the right side;

the third type diode device (19) is separated from the adjacent second type diode device (18) by a spacer structure; the third diode device (19) is provided with a second doping type fifth buried layer (315) at the part upper surface of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is located above the second doping type fifth buried layer (315), two first heavy doping type contact areas (52) and two second heavy doping type contact areas (32) are arranged at the upper surface of the first doping type epitaxial layer (512), a space is arranged between the two second heavy doping type contact areas (32) and located between adjacent field oxide layers (86), the upper surface of the field oxide layer (86) is covered with a dielectric layer (62), the twenty-second metal layer (147) covers the first heavy doping type contact area (52) at the left side, the twenty-second metal layer (148) covers part upper surface of the first doping type epitaxial layer (512), and the upper surfaces of the two second heavy doping type contact areas (32), and the twenty-second metal layer (149) covers the first heavy doping type contact areas (52) at the right side;

The fourth type diode device (20) is separated from the adjacent third type diode device (19) by a spacer structure; the fourth diode device (20) is provided with a second doping type sixth buried layer (316) at the upper surface of a part of the second doping type epitaxial layer (311), the first doping type epitaxial layer (512) is located above the second doping type sixth buried layer (316), two first heavy doping type contact areas (52), two thirteenth type oxide layers (622) and two sixth type polycrystalline silicon (709) are arranged at the upper surface of the first doping type epitaxial layer (512), the two thirteenth type oxide layers (622) are located between the two first heavy doping type contact areas (52), an interval is arranged between the two thirteenth type oxide layers (622), the first heavy doping type contact areas (52) and the thirteenth type oxide layers (622) are field oxide layers (86), the upper surface of the field oxide layers (86) is covered with a dielectric layer (62), the sixth type polycrystalline silicon (709) is located on the inner upper surface of the thirteenth type oxide layer (622), the upper surface of the two sixth type polycrystalline silicon (709) and the twenty-fourth type metal layer (622), the rest of the thirteenth type polycrystalline silicon (709) and the thirteenth type metal layer (151) are covered by the upper surface of the thirteenth type epitaxial layer (151), the thirteenth type epitaxial layer (622) is covered by the upper surface of the thirteenth metal layer (151), the thirteenth type epitaxial layer (150) is covered by the upper surface of the thirteenth type oxide layer (151), and the upper surfaces of the two sixth-type polycrystalline silicon (709), wherein the second fifteen-type metal layer (152) covers the first heavy doping type contact region (52) on the right side.

2. The BCD semiconductor device of claim 1, wherein: the spacer (21) is formed by a filling medium.

3. The BCD semiconductor device of claim 1, wherein: the first doping type strips (51) and the second doping type strips (31) which are periodically and alternately arranged are formed through grooving filling.

4. The BCD semiconductor device of claim 1, wherein: a thin layer medium (63) is arranged between the first doping type strips (51) and the second doping type strips (31) which are periodically and alternately arranged.

5. The BCD semiconductor device of claim 1, wherein: the first doping type strips (51) and the second doping type strips (31) which are periodically and alternately arranged are directly arranged on the first doping type substrate (85), and a first doping type Buffer region is removed.

6. The BCD semiconductor device of claim 1, wherein: the devices (4-20) on the right side of the second-type VDMOS device (3) are isolated from the second doping type epitaxial layer (311) right below by a medium.

7. The BCD semiconductor device of claim 1, wherein: the first type polycrystalline silicon control grid (701) in the first type VDMOS device (2) and the second type VDMOS device (3) is replaced by two vertical separated second type polycrystalline silicon control grids (704).

8. The BCD semiconductor device of claim 1, wherein: the first type polycrystalline silicon separation grid (702) in the first type VDMOS device (2) and the second type VDMOS device (3) is replaced by a third type polycrystalline silicon separation grid (705) which is longitudinally separated.

9. The BCD semiconductor device of claim 1, wherein: the first type polycrystalline silicon control grid (701) in the first type VDMOS device (2) and the second type VDMOS device (3) is replaced by a third type polycrystalline silicon control grid (706) which is transversely separated, the first type polycrystalline silicon separation grid (702) is replaced by a fourth type polycrystalline silicon separation grid (707), and the fourth type polycrystalline silicon separation grid (707) passes through the two separated third type polycrystalline silicon control grids (706) and is in contact with the first type metal layer (102) and the third type metal layer (104) above.

10. The BCD semiconductor device of claim 1, wherein: the upper ends of the terminal structures 2 (n) of the first-type VDMOS devices (2) are covered by a field oxide layer (86), and the fifth-type polysilicon separation gate (708) is surrounded by a first-type gate oxide layer (610).