CN111769824B

CN111769824B - Configurable delay circuit

Info

Publication number: CN111769824B
Application number: CN202010667700.1A
Authority: CN
Inventors: 李建军; 谢宇; 陈诚; 杜涛; 李威
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2020-07-13
Filing date: 2020-07-13
Publication date: 2022-06-14
Anticipated expiration: 2040-07-13
Also published as: CN111769824A

Abstract

The invention belongs to the technical field of integrated circuits and provides a configurable delay circuit. A configurable delay cell, comprising: a configuration circuit 1 with an enable terminal; a delay element that may comprise a configuration circuit 2 with an enable terminal; a pulse shaping circuit may optionally be included. A configurable delay module including a configurable delay cell, comprising: at least one configurable delay element; one or several non-configurable delay cells may be optionally included. A delay circuit including a configurable delay module, comprising: at least one configurable delay module; optionally a p-q decoding module; at least one output port; the data selection module can be selectively contained, and is provided with m +1 input ports and n output ports; a number of pulse shaping circuits may optionally be included.

Description

Configurable delay circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a configurable delay circuit.

Background

Delay circuits are often used in integrated circuit designs for delaying signals, removing jitter from signals, for signal generation, and so forth.

Disclosure of Invention

The invention relates to a configurable delay circuit.

A configurable delay cell, as shown in fig. 1, may comprise: the configuration circuit with the enable terminal 1 comprises at least one logic gate with the enable terminal, the output end of the at least one logic gate with the enable terminal is used as the output end of the configuration circuit with the enable terminal 1, a common logic gate is used for ensuring the logic is correct, and the input end of the configuration circuit with the enable terminal 1 is connected to the input end of the configurable delay unit; a delay element which can comprise a configuration circuit 2 with an enable end, wherein the output end of the delay element is connected to the output end of the configuration circuit 1 with the enable end, the input end of the delay element is connected to the input end of the configuration circuit 1 with the enable end, the delay element can selectively comprise the configuration circuit 2 with the enable end, and the configuration circuit 2 with the enable end can comprise at least one logic gate with the enable end; optionally, a pulse shaping circuit may be included for shaping the delayed signal into an approximately square wave signal.

A configurable delay module including a configurable delay cell, as shown in fig. 2, may include: at least one configurable delay element; one or several non-configurable delay cells (differing from configurable delay cells in that there are no

configuration circuits

1 and 2 with enable terminals) may optionally be included. The input end of the first delay unit (both the configurable delay unit and the non-configurable delay unit) is connected to the input end of the configurable delay module, the output end of the first delay unit is connected to the input end of the second delay unit, the output end of the second delay unit is connected to the input end of the third delay unit, the first delay unit and the second delay unit are sequentially connected, and the output end of the last delay unit is connected to the output end of the configurable delay module. Each configurable delay cell has an enable signal input port.

A delay circuit including a configurable delay module, as shown in fig. 3, may include: at least one configurable delay module; optionally, a p-q decoding module is included, the p-q decoding module can be used for decoding p input signals into q enable signals of the configurable delay module, and both p and q need to be greater than or equal to 1; at least one output port; the data selection module can be used for selecting one signal from m +1 input signals for each output port to output, and both m and n need to be more than or equal to 1; optionally, a plurality of pulse shaping circuits may be included for shaping the delayed signal into a substantially square wave signal.

Drawings

FIG. 1 is a diagram of a configurable delay cell

FIG. 2 is a block diagram of a configurable delay module including configurable delay cells

FIG. 3 is a delay circuit including a configurable delay block

FIG. 4 is a diagram of an embodiment of a configurable delay cell

FIG. 5 is a simulation effect diagram of an embodiment of a configurable delay cell

FIG. 6 is a block diagram of an embodiment of a non-configurable delay cell

FIG. 7 is a simulation effect diagram of an embodiment of a non-configurable delay cell

FIG. 8 is a block diagram of an embodiment of a configurable delay module including configurable delay cells

FIG. 9 is a truth table for an embodiment of a configurable delay block including configurable delay cells

FIG. 10 is a simulation diagram of an embodiment of a configurable delay module including configurable delay cells

FIG. 11 is a block diagram of an embodiment of a delay circuit including a configurable delay block

FIG. 12 is a truth table for a 3-7 decoding circuit

FIG. 13 is a truth table for an 8-out-of-1 data selection circuit

FIG. 14 is a simulation result diagram of an embodiment of a delay circuit including a configurable delay block

Detailed Description

Various embodiments will be described in more detail below with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein.

When an element is referred to as being "connected to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. Furthermore, when the terms "comprising," including, "and" may be used in this specification, there is an indication that the element is present, and there is no exclusion of the presence or addition of one or more other elements.

For convenience of description, the following enable signals are all active high.

An embodiment of a configurable delay cell is shown in fig. 4, and a configuration circuit 1 with an enable terminal may include: 1 inverter with enable terminal; 1 ordinary inverter. The output end of the inverter with the enabling end is connected to the input end of the pulse shaping circuit, when the enabling signal of the configurable delay unit is invalid, the inverter with the enabling end operates like a common inverter, and the delay function of the inverter type in the delay element which can comprise the configuration circuit 2 with the enabling end can be made invalid. The common inverter is used to ensure that the output signal of the configuration circuit 1 with the enable terminal has correct logic.

A delay element that may include a configuration circuit 2 with an enable terminal may include: 1 inverter with enable terminal; 1 inverter of inverse ratio tube; 2 ordinary inverters; 1 capacitor; 1 transmission gate with enable terminal. The common inverter connected with the input end of the inverter of the inverting tube is used for isolating the input end of the configurable delay unit from the input end of the inverter of the inverting tube, so that the level overturning speed of the input end of the configurable delay unit is not influenced by the inverter of the inverting tube. The inverter with enable terminal and the capacitor function as delay when the enable signal of the configurable delay unit is valid, the transmission gate with enable terminal is in off state when the enable signal of the configurable delay unit is invalid, so that the output signal of the delay element of the configuration circuit 2 with enable terminal can be protected from the influence of the delay function of the capacitor, and the inverter with enable terminal can synchronize the logic level of the capacitor with the output signal of the delay element of the configuration circuit 2 with enable terminal.

A pulse shaping circuit may include: 2 ordinary inverters. The pulse shaping circuit is used for shaping pulse waveforms.

The delay time set in this embodiment is 50ns, when the enable signal of the configurable delay unit is valid, the output signal may be delayed by 50ns compared with the input signal, and when the enable signal of the configurable delay unit is invalid, the output signal is not delayed compared with the input signal, as shown in fig. 5.

One embodiment of a non-configurable delay cell is shown in fig. 6, a delay element comprising: 1 inverter of inverse ratio tube; 1 common inverter; 1 capacitor. Compared with the embodiment shown in fig. 4, without the configuration circuit 1 with the enable terminal and the configuration circuit 2 with the enable terminal, the delay time set by the embodiment is 50ns, the signal port is not enabled, and the output signal is delayed by 50ns compared with the input signal as shown in fig. 7.

Based on the embodiments of fig. 4 and 6, an embodiment of a configurable delay module including a configurable delay unit is shown in fig. 8, and may include: 7 configurable delay cells; 1 unconfigurable delay unit; 7 enable signal input ports; 1 input port for signals to be processed and 1 output port. In this embodiment, the delay time of each delay unit is set to 50ns, and the larger the effective number of the enable signal is, the longer the delay time of this embodiment is, as shown in fig. 9. FIG. 10 shows the delay effect of this embodiment when the enable signal EN [6:0] is equal to 0001111 and 0000000 (i.e., the EN active counts are 4 and 0, respectively).

Based on the embodiment of fig. 8, an embodiment of a delay circuit including a configurable delay module, as shown in fig. 11, may include: 7 configurable delay modules, the delay time of each configurable delay module being configurable; 1 3-7 decoding module, the 3-7 decoding module has 3 input terminals DEC _ SEL [2:0], 7 output terminals EN [6:0], the truth table is shown in FIG. 12; 1 data selection module (composed of 3 data selection units of 1 from 8), in this embodiment, 3 data selection units of 1 from 8 are used to configure OUT 2, OUT 1, and OUT 0, each data selection unit of 1 from 8 has 3 input terminals, which are MUX _ SEL [8:6], MUX _ SEL [5:3], MUX _ SEL [2:0], take MUX _ SEL [2:0] and OUT 0 as examples, and the truth table is shown in fig. 13. The delay effect of this embodiment is shown in FIG. 14, when DEC _ SEL [2:0] is 000, the delay time of each configurable delay block is 50ns, if MUX _ SEL [8:0] is 011100110, OUT 2 is delayed by 150ns, OUT 1 is delayed by 200ns, OUT 0 is delayed by 300ns, if MUX _ SEL [8:0] is 101001001, OUT 2 is delayed by 250ns, OUT 1 is delayed by 50ns, OUT 0 is delayed by 50 ns; the delay time of each configurable delay block is 250ns when DEC _ SEL [2:0] is 100, OUT 2 is 750ns, OUT 1 is 1us, OUT 0 is 1.5us if MUX _ SEL [8:0] is 011100110, OUT 2 is 1.25us, OUT 1 is 250ns, OUT 0 is 250ns if MUX _ SEL [8:0] is 101001001.

The foregoing embodiments have fully described the essential technical content of the present invention, and those skilled in the art can implement the invention according to the description, so that other technical details are not described in detail.

Where, as mentioned above, it is only a specific embodiment of the present invention, any feature disclosed in this specification may be replaced by alternative features serving an equivalent or specific similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims

1. A configurable delay cell, comprising: a configuration circuit 1 with an enable terminal, the circuit comprising at least one logic gate with an enable terminal, an output terminal of the at least one logic gate with an enable terminal being connected to an output terminal of the configuration circuit 1 with an enable terminal; a delay element comprising a configuration circuit 2 with an enable terminal, the configuration circuit 2 with an enable terminal comprising at least one logic gate with an enable terminal; the pulse shaping circuit is used for shaping the delayed signals into signals similar to square waves;

the following enable signals are all active at high level;

the configuration circuit 1 with an enable end comprises: 1 inverter with enable end, 1 common inverter; the output end of the inverter with the enabling end is connected to the input end of the pulse shaping circuit, when the enabling signal of the configurable delay unit is invalid, the operation state of the inverter with the enabling end is similar to that of a common inverter, and the delay function of the inverter of the inverting ratio tube in the delay element comprising the configuration circuit 2 with the enabling end can be made invalid; the common inverter is used for ensuring that the output signal logic of the configuration circuit 1 with the enable end is correct;

the delay element of the configuration circuit 2 with an enable end comprises: 1 inverter with enable end, 1 inverter of inverse ratio tube, 2 ordinary inverters, 1 capacitor, 1 transmission gate with enable end; the common inverter connected with the input end of the inverter of the inverting tube is used for isolating the input end of the configurable delay unit from the input end of the inverter of the inverting tube, so that the level overturning speed of the input end of the configurable delay unit is not influenced by the inverter of the inverting tube; when the enable signal of the configurable delay unit is valid, the inverter and the capacitor play a delay function, when the enable signal of the configurable delay unit is invalid, the transmission gate with the enable end is in a cut-off state, the output signal of the delay element of the configuration circuit 2 with the enable end can be free from the influence of the capacitor delay function, and the inverter with the enable end can enable the logic level of the capacitor to be synchronous with the output signal of the delay element comprising the configuration circuit 2 with the enable end;

the logic gate with the enable end comprises an inverter with the enable end, a NAND gate with the enable end, a NOR gate with the enable end and a transmission gate with the enable end.

2. A configurable delay module including a configurable delay cell, comprising: at least one configurable delay cell of claim 1; the delay circuit comprises one or a plurality of non-configurable delay units, wherein the non-configurable delay units are different from the configurable delay units in that configuration circuits 1 and 2 with enabling ends are not arranged; the input end of the first delay unit is connected to the input end of the configurable delay module, the output end of the first delay unit is connected to the input end of the second delay unit, the first delay unit is a configurable delay unit or a non-configurable delay unit, the output end of the second delay unit is connected to the input end of the third delay unit and is connected in sequence, and the output end of the last delay unit is connected to the output end of the configurable delay module; each configurable delay cell has an enable signal input port.

3. A delay circuit including a configurable delay module, comprising: at least one configurable delay module of claim 2; the device comprises a p-q decoding module, wherein the p-q decoding module can be used for decoding p input signals into q enable signals of a configurable delay module, and both p and q need to be more than or equal to 1; at least one output port; the data selection module is provided with m +1 input ports and n output ports, the data selection module can be used for selecting one signal from m +1 input signals for each output port to output, and both m and n are more than or equal to 1; the pulse shaping circuit is used for shaping the delayed signals into signals approximate to square waves.