CN111697048A - Method for improving total dose irradiation resistance of FinFET device - Google Patents
Method for improving total dose irradiation resistance of FinFET device Download PDFInfo
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- CN111697048A CN111697048A CN201910187276.8A CN201910187276A CN111697048A CN 111697048 A CN111697048 A CN 111697048A CN 201910187276 A CN201910187276 A CN 201910187276A CN 111697048 A CN111697048 A CN 111697048A
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 239000013078 crystal Substances 0.000 claims abstract description 34
- 238000013461 design Methods 0.000 claims abstract description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 4
- 239000002070 nanowire Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 2
- 229910052732 germanium Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005855 radiation Effects 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
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- 230000001186 cumulative effect Effects 0.000 description 1
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- 239000012212 insulator Substances 0.000 description 1
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- 238000004377 microelectronic Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
The invention discloses a method for improving total dose irradiation resistance of a FinFET device. The method ensures that the crystal orientation of a channel of the FinFET device is <100> by properly adjusting the device arrangement direction during layout design by utilizing the crystal orientation dependence of the oxide layer trapped charge density and the interface state, so that the oxide layer trapped charge density and the interface state density generated in the prepared FinFET device by total dose irradiation are lower, the influence of the total dose irradiation on the FinFET device is reduced, and the total dose irradiation resistance of the FinFET device is improved.
Description
Technical Field
The invention relates to a method for improving the total dose irradiation resistance of a fin field effect transistor (FinFET), belonging to the technical field of super-large-scale integrated circuit manufacturing.
Background
With the rapid development of integrated circuit technology, the feature size of devices has been reduced to the nanometer scale. The FinFET device has good grid control capability, and can overcome the problems of short channel effect, mobility degradation and the like of the traditional planar bulk silicon device. From the 22nm technology node, finfets have become the dominant device in the fabrication of nanoscale very large scale integrated circuits. FinFET devices may be classified into bulk silicon FinFET devices and Silicon On Insulator (SOI) FinFET devices, depending on the substrate. On the other hand, with the rapid development of the aerospace technology, more and more integrated circuits work in the space radiation environment. After a microelectronic device working in the outer space is irradiated by electrons, X rays, gamma rays and the like in a space radiation environment, a total dose radiation effect is generated, so that the direct current characteristics of the device are changed, such as threshold voltage drift, off-state leakage current increase, transconductance change and the like, and the power consumption of an integrated circuit is increased, the performance is reduced and even the function is failed. In order to enable the integrated circuit to normally work in a severe space radiation environment, higher requirements are put on the radiation resistance of the device. Existing research shows that degradation phenomena such as increase of off-state leakage current and threshold voltage drift occur after a FinFET device is irradiated by total dose. The total dose irradiation is the main reason for the direct current characteristic change of the device due to the oxide layer trap charges introduced in the oxide layer (such as Shallow Trench Isolation (STI) and gate oxide layer) of the device and the interface state generated at the oxide layer/semiconductor interface. Therefore, the density of oxide layer trap charges and the density of interface states generated near the channel of the FinFET device in the irradiation process are reduced, and the total dose irradiation resistance of the device can be improved.
Disclosure of Invention
In order to improve the total dose irradiation resistance of the FinFET device, the invention provides a method for improving the total dose irradiation resistance of the FinFET device based on layout design. The technical scheme of the invention is as follows:
a method for improving the total dose irradiation resistance of a FinFET device is characterized in that the orientation of a FinFET channel is enabled to be <100> by adjusting the arrangement direction of the FinFET device during layout design, and then the FinFET device is prepared by the layout. According to the method for improving the total dose irradiation resistance of the FinFET device, the crystal orientation of the channel of the FinFET device is designed by properly adjusting the placement direction of the device by utilizing the crystal orientation dependence of the oxide layer trap charge density and the interface state, so that the oxide layer trap charge density and the interface state density generated in the prepared FinFET device by total dose irradiation are lower, the influence of the total dose irradiation on the FinFET device is reduced, and the total dose irradiation resistance of the FinFET device is improved. The method specifically comprises the following steps:
firstly, determining a crystal face of a wafer;
secondly, properly adjusting the arrangement direction of the FinFET devices according to the crystal face of the wafer to ensure that the crystal orientation of FinFET channels is <100 >;
and thirdly, preparing the FinFET device according to the layout obtained in the second step and a normal process flow.
According to the method for improving the total dose irradiation resistance of the FinFET device, the FinFET device comprises a bulk silicon FinFET device, an SOI FinFET device and a Nanowire (NW) FinFET device, the channel material can be Si, Ge, SiGe, a III-V semiconductor material or a heterostructure thereof, and the device structure can be a tri-gate, an omega-gate, an n-gate and the like.
In the method for improving the total dose irradiation resistance of the FinFET device, in the first step, the crystal plane of the wafer is usually (100), and the crystal direction is usually <110> along the orientation edge.
In the second step, the most preferable crystal orientation of the channel is <100> for the silicon material channel. If the crystal plane of the wafer is (100), the direction forming an included angle of 45 degrees with the positioning edge is the preferred channel direction of the FinFET device, and the channel crystal direction is <100 >. If the wafer is other crystal faces, the arrangement direction of the device should be correspondingly adjusted, and the crystal orientation of the FinFET channel is ensured to be <100 >.
According to the method for improving the total dose irradiation resistance of the FinFET device, except for the change of the layout direction of the device, other process preparation flows are unchanged, and the FinFET device is prepared according to the normal process flow in the third step.
According to the method, the crystal orientation of the channel of the FinFET device is ensured to be <100> by properly adjusting the layout direction of the device by utilizing the oxide layer trap charge density and the crystal orientation dependence of the interface state introduced by total dose irradiation, so that the oxide layer trap charge density and the interface state density introduced by irradiation are smaller after the prepared FinFET device is irradiated by the total dose, the influence of the total dose irradiation on the characteristics of the FinFET device is reduced, and the total dose irradiation resistance of the FinFET device is improved. The method has the advantages of simple operation, no additional cost increase and improvement of the total dose irradiation resistance of the FinFET device.
Drawings
Fig. 1 is a schematic diagram (a) of a common layout FinFET channel crystal orientation and a schematic diagram (b) of the layout FinFET channel crystal orientation of the present invention.
Fig. 2 is a graph comparing threshold voltage shifts for bulk silicon FinFET devices with channel orientations <110> and <100> after total dose irradiation in an example embodiment.
Detailed Description
According to the method, the crystal orientation of the channel of the FinFET device is ensured to be <100> by properly adjusting the layout direction of the device by utilizing the oxide layer trap charge density and the crystal orientation dependence of the interface state introduced by total dose irradiation, so that the oxide layer trap charge density and the interface state density introduced by irradiation are smaller after the prepared FinFET device is irradiated by the total dose, the influence of the total dose irradiation on the characteristics of the FinFET device is reduced, and the total dose irradiation resistance of the FinFET device is improved. The invention is described in detail below with reference to the figures and examples.
Example 1: p-type FinFET devices with channel orientations <110> and <100> were fabricated on the same bulk silicon (100) wafer and compared for total dose exposure resistance. The method comprises the following specific steps:
step 1, designing a P-type FinFET device layout with channel crystal orientations of <110> and <100> on a (100) bulk silicon wafer, wherein the parameters are the same except that the channel crystal orientations are different. For the (100) wafer, the alignment mark (Notch) is oriented downward in the positive direction, and the crystal orientation in the horizontal axis direction is <110 >. The channel crystal orientation of a common layout FinFET device is <110>, as shown in the left diagram (a) of fig. 1. The direction forming an included angle of 45 degrees with the horizontal axis is the channel direction of the FinFET device provided by the invention, and the crystal direction of the FinFET channel is <100>, as shown in the right diagram (b) in FIG. 1;
step 2, preparing two P-type FinFET devices by adopting the same process;
step 3, testing transfer characteristic curves of the two P-type FinFET devices;
and 4, performing an irradiation experiment ON the two P-type FinFET devices by using X rays ON a wafer-level total dose irradiation experiment platform, wherein the irradiation process is performed at room temperature, and the irradiation bias is in an ON state (V)g-1V, with the other end grounded), for a final cumulative total dose of 1mrad (si);
step 5, testing the transfer characteristic curves of the two irradiated P-type FinFET devices;
and 6, extracting the threshold voltages of the two P-type FinFET devices before and after irradiation by using a constant current method, and calculating the threshold voltage drift, as shown in FIG. 2.
As can be seen from fig. 2, the threshold voltage drift of the P-type FinFET device with a channel crystal orientation of <100> after being irradiated by 1mrad (si) is 21% lower than that of the P-type FinFET device with a channel crystal orientation of <110>, and the P-type FinFET device has a higher total dose irradiation resistance.
Therefore, the invention ensures that the crystal orientation of the channel of the FinFET device is <100> by adjusting the layout direction of the device and utilizing the oxide layer trap charge density introduced by total dose irradiation and the crystal orientation dependence of the interface state, so that the prepared FinFET device has higher total dose irradiation resistance. The method has the advantages of simple operation, no additional cost increase and improvement of the total dose irradiation resistance of the FinFET device.
The above-described embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, which is defined by the appended claims.
Claims (6)
1. A method for improving the total dose irradiation resistance of a FinFET device is characterized in that the orientation of a FinFET channel is enabled to be <100> by adjusting the arrangement direction of the FinFET device during layout design, and then the FinFET device is prepared by the layout.
2. A method as claimed in claim 1, characterized in that the method comprises the following steps:
1) determining a crystal face of the wafer;
2) adjusting the arrangement direction of the FinFET devices according to the crystal face of the wafer to ensure that the crystal orientation of FinFET channels is <100 >;
3) and 5) preparing the FinFET device according to the layout obtained in the step 2).
3. The method of claim 1 or 2, wherein the FinFET device is a bulk silicon FinFET device, a soi FinFET device, or a nanowire FinFET device.
4. The method of claim 1 or 2, wherein a channel material of the FinFET device is Si, Ge, SiGe, and/or a III-V semiconductor material.
5. The method of claim 1 or 2, wherein the structure of the FinFET device is a tri-gate, an omega-gate, or a Π -gate.
6. The method of claim 2, wherein the wafer crystal plane is (100), and the direction forming an angle of 45 degrees with the positioning edge in step 2) is a channel direction of the FinFET device, and the channel crystal direction is <100 >.
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| CN201910187276.8A CN111697048A (en) | 2019-03-13 | 2019-03-13 | Method for improving total dose irradiation resistance of FinFET device |
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| CN201910187276.8A CN111697048A (en) | 2019-03-13 | 2019-03-13 | Method for improving total dose irradiation resistance of FinFET device |
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Citations (7)
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| US20050184283A1 (en) * | 2004-02-20 | 2005-08-25 | Shigenobu Maeda | Semiconductor device having a triple gate transistor and method for manufacturing the same |
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2019
- 2019-03-13 CN CN201910187276.8A patent/CN111697048A/en active Pending
Patent Citations (7)
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| US20050184283A1 (en) * | 2004-02-20 | 2005-08-25 | Shigenobu Maeda | Semiconductor device having a triple gate transistor and method for manufacturing the same |
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Application publication date: 20200922 |