CN111641396B - Charge amplifying circuit for front-end reading system of silicon drift detector - Google Patents
Charge amplifying circuit for front-end reading system of silicon drift detector Download PDFInfo
- Publication number
- CN111641396B CN111641396B CN202010617850.1A CN202010617850A CN111641396B CN 111641396 B CN111641396 B CN 111641396B CN 202010617850 A CN202010617850 A CN 202010617850A CN 111641396 B CN111641396 B CN 111641396B
- Authority
- CN
- China
- Prior art keywords
- mos tube
- capacitor
- amplifying circuit
- electrode
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 17
- 239000010703 silicon Substances 0.000 title claims abstract description 17
- 230000008878 coupling Effects 0.000 claims abstract description 5
- 238000010168 coupling process Methods 0.000 claims abstract description 5
- 238000005859 coupling reaction Methods 0.000 claims abstract description 5
- 239000003990 capacitor Substances 0.000 claims description 74
- 101100219315 Arabidopsis thaliana CYP83A1 gene Proteins 0.000 claims description 3
- 101000806846 Homo sapiens DNA-(apurinic or apyrimidinic site) endonuclease Proteins 0.000 claims description 3
- 101000835083 Homo sapiens Tissue factor pathway inhibitor 2 Proteins 0.000 claims description 3
- 101100269674 Mus musculus Alyref2 gene Proteins 0.000 claims description 3
- 101100140580 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) REF2 gene Proteins 0.000 claims description 3
- 102100026134 Tissue factor pathway inhibitor 2 Human genes 0.000 claims description 3
- 230000003321 amplification Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 229910052500 inorganic mineral Inorganic materials 0.000 description 1
- 239000011707 mineral Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/70—Charge amplifiers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
- H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
- H04N25/773—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses a charge amplifying circuit for a front end reading system of a silicon drift detector, which comprises a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the input end of the first-stage amplifying circuit is connected with the detector in a direct current coupling way, the output end of the first-stage amplifying circuit is connected with the input end of the second-stage amplifying circuit, and the output end of the second-stage amplifying circuit outputs amplified signals. Aiming at the situation that the input signal of the silicon drift detector is extremely weak, the invention provides a pre-amplifying circuit structure adopting a two-stage accurate charge amplifying circuit, the structure multiplies and amplifies the charge quantity firstly, then converts the charge quantity into a voltage signal, and can exchange the maximum charge-voltage gain with the minimum noise cost, thereby meeting the requirement of a silicon drift detector reading system on the gain.
Description
Technical Field
The present invention relates to a charge amplifying circuit, and more particularly, to a charge amplifying circuit for a front-end readout system of a silicon drift detector.
Background
The silicon drift detector has the advantages of low capacitance, low noise, quick response time, high energy resolution and the like as a novel semiconductor radiation detector, is widely applied to the fields of aerospace, high-energy physical experiments, medical instruments, mineral exploration and the like, and has wide application prospect. The output signal of the silicon drift detector is very weak, so that in the silicon drift detector reading system, the pre-amplifier is required to pre-amplify the detected output signal with low noise and then carry out subsequent processing, thus the noise of the whole system can be reduced, the signal to noise ratio can be improved, the design requirements of the post-stage circuit on indexes such as noise, gain and the like can be reduced, and the design of the post-stage circuit can be simplified.
In a silicon drift detector front-end read-out system, the preamplifier is typically a charge sensitive amplifier, a typical charge sensitive amplifier is shown in FIG. 1, where C T The total capacitance to ground of the input end of the operational amplifier is equal to the sum of the capacitance of the detector body, the parasitic capacitance to ground of the negative input tube of the operational amplifier, the parasitic capacitance to ground of the PCB of the negative input end and the packaging bonding line, wherein i d Is the pulse current output by the detector, C F For feeding back capacitance, R F To reduce noise and ballistic losses, the resistance value of the feedback resistor can be very large, in the order of hundred megabytes. Assuming that the detector outputs a charge quantity Q, a voltage v out The calculation formula of (2) can be approximated as:
the charge-voltage gain of the amplifier is 1/C F 。
The maximum detection energy of the output signal of the silicon drift detector is 20keV, which is about 5500 electrons, which is weaker than that of a common radiation detector, and the common charge amplifying circuit cannot reach the charge-voltage gain required by the common charge amplifying circuit. In addition, common charge amplifiers use double-ended input single-ended output operational amplifiers, which have good suppression effects on common mode noise and power supply noise, but use double devices relative to single-ended input operational amplifiers, so intrinsic noise is twice that of single-ended input.
Disclosure of Invention
In order to solve the technical problems, the invention provides a charge amplifying circuit for a front-end reading system of a silicon drift detector, which has a simple structure and is safe and reliable.
The technical scheme for solving the problems is as follows: the charge amplifying circuit comprises a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the input end of the first-stage amplifying circuit is connected with the detector in a direct current coupling way, the output end of the first-stage amplifying circuit is connected with the input end of the second-stage amplifying circuit, and the output end of the second-stage amplifying circuit outputs amplified signals.
The first-stage amplifying circuit comprises a first MOS tube, a second MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a second capacitor and a first operational amplifier, wherein the first operational amplifier is provided with an input end and two output ends, the input end, one end and the drain electrode of the first operational amplifier are connected and serve as the input end of the charge amplifying circuit, the first output end, the other end and one end of the first capacitor of the first operational amplifier are connected, the second output end of the first operational amplifier is connected with the grid electrode of the fifth MOS tube, the drain electrode of the fifth MOS tube, the grid electrode of the first MOS tube, the grid electrode of the sixth MOS tube, the drain electrode of the sixth MOS tube and the grid electrode of the second MOS tube are connected, and the source electrode of the first MOS tube, the source electrode of the sixth MOS tube and the source electrode of the second MOS tube are connected together and grounded, and the drain electrode of the second MOS tube is connected with the other end of the second capacitor and serves as the output end of the first operational amplifier.
The second-stage amplifying circuit comprises a third MOS tube, a fourth MOS tube, a seventh MOS tube, an eighth MOS tube, a third capacitor, a fourth capacitor and a second operational amplifier, wherein the second operational amplifier is provided with an input end and two output ends, the input end of the second operational amplifier, the drain electrode of the second MOS tube, the other end of the second capacitor, one end of the third capacitor and the drain electrode of the third MOS tube are connected, the first output end of the second operational amplifier is connected with the gate electrode of the seventh MOS tube, the second output end of the second operational amplifier is connected with the other end of the third capacitor and one end of the fourth capacitor, the drain electrode of the seventh MOS tube, the gate electrode of the third MOS tube, the gate electrode of the eighth MOS tube, the drain electrode of the fourth MOS tube are connected, the source electrode of the fifth MOS tube, the source electrode of the third MOS tube and the drain electrode of the fourth MOS tube are connected, and the other end of the fourth MOS tube is connected with the drain electrode of the fourth capacitor and is used as the drain electrode of the amplifying circuit.
The first operational amplifier and the second operational amplifier have the same structure, the first operational amplifier comprises a ninth to a twentieth MOS tube and a fifth to a seventh capacitor, the gate of the ninth MOS tube is used as the input end of the first operational amplifier, the source of the ninth MOS tube is grounded, the drain of the ninth MOS tube, the drain of the tenth MOS tube and the source of the eleventh MOS tube are connected, the drain of the eleventh MOS tube, the drain of the twelfth MOS tube, the gate of the fourteenth MOS tube and one end of the seventh capacitor are connected and used as the first output end of the first operational amplifier, the gate of the twelfth MOS tube, one end of the sixth capacitor and the gate of the twenty first MOS tube are connected, the drain of the twenty first MOS tube is connected with the drain of the twenty first MOS tube, the drain of the fourteenth MOS tube, the source of the twelfth MOS tube, the other end of the sixth capacitor and the source of the twenty first MOS tube are connected in parallel, the gate of the eleventh tube, the gate of the twenty first MOS tube, the gate of the twenty eighth MOS tube, the drain of the sixteenth MOS tube are connected in parallel, and the bias voltage of the sixteenth MOS tube is connected to the drain of the sixteenth MOS tube REF1 The source electrode of the sixteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube, and the drain electrode of the eighteenth MOS tube is connected with the bias voltage I REF2 The source electrode of the twenty-eighth MOS tube is connected with the drain electrode of the nineteenth MOS tube, and the grid electrode of the nineteenth MOS tube, the grid electrode of the seventeenth MOS tube, the drain electrode of the seventeenth MOS tube and the nineteenth MOS tube are connected with the drain electrode of the nineteenth MOS tubeOne end of the fifth capacitor is connected with the source electrode of the eighteenth MOS tube, the grid electrode of the tenth MOS tube is connected with the grid electrode of the thirteenth MOS tube, the source electrode of the fifteenth MOS tube, the source electrode of the seventeenth MOS tube, the other end of the fifth capacitor, the source electrode of the nineteenth MOS tube, the source electrode of the tenth MOS tube, the other end of the seventh capacitor and the source electrode of the thirteenth MOS tube are connected together and connected to VSS in parallel, and the source electrode of the fourteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube and serves as a second output end of the operational amplifier.
The invention has the beneficial effects that:
1. aiming at the situation that the input signal of the silicon drift detector is extremely weak, the invention provides a pre-amplifying circuit structure adopting a two-stage accurate charge amplifying circuit, the structure multiplies and amplifies the charge quantity firstly, then converts the charge quantity into a voltage signal, and can exchange the maximum charge-voltage gain with the minimum noise cost, thereby meeting the requirement of a silicon drift detector reading system on the gain.
2. The invention applies the single-ended input double-ended output operational amplifier to the charge amplifying circuit for the first time, thereby greatly reducing the gain nonlinearity of the charge amplifying circuit.
Drawings
Fig. 1 is a circuit diagram of a typical sensitive charge amplifier.
Fig. 2 is a circuit configuration diagram of the present invention.
Fig. 3 is a circuit diagram of a single-ended input double-ended output operational amplifier of the present invention.
FIG. 4 is a graph of simulated input pulse current waveforms in accordance with the present invention.
Fig. 5 is a waveform diagram of the voltage response of the first stage and the second stage of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and examples.
As shown in FIG. 1, the charge amplifying circuit for the front end reading system of the silicon drift detector comprises a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the input end of the first-stage amplifying circuit is connected with the detector in a direct current coupling way, the output end of the first-stage amplifying circuit is connected with the input end of the second-stage amplifying circuit, and the output end of the second-stage amplifying circuit outputs amplified signals.
The first stage amplifying circuit comprises a first MOS tube M 1 Second MOS tube M 2 Fifth MOS tube M n1 Sixth MOS transistor M p1 First capacitor C 1 A second capacitor C 2 And a first operational amplifier U 1 The first operational amplifier U 1 Having one input and two outputs, the first operational amplifier U 1 Input terminal of (C), first capacitor C 1 One end of the first MOS tube M 1 The drain is connected with and used as the input end of the charge amplifying circuit, the first operational amplifier U 1 A first output terminal of (C), a first capacitor C 1 Another end, a second capacitor C 2 One end is connected with a first operational amplifier U 1 And a fifth MOS transistor M n1 The grid electrode of the fifth MOS tube M is connected with n1 Drain electrode of (a) first MOS transistor M 1 Grid electrode of (C), sixth MOS tube M p1 Grid electrode of (C), sixth MOS tube M p1 Drain electrode of (d), second MOS transistor M 2 The grid electrode of the first MOS tube M is connected with 1 Source electrode of (d), sixth MOS transistor M p1 Source electrode of (2), second MOS tube M 2 The sources of the second MOS tube M are connected together and grounded 2 Drain of (C) and a second capacitor C 2 The other end is connected and used as a first operational amplifier U 1 Is provided.
The second-stage amplifying circuit comprises a third MOS tube M 3 Fourth MOS tube M 4 Seventh MOS tube M p2 Eighth MOS tube M n2 Third capacitor C 3 Fourth capacitor C 4 And a second operational amplifier U 2 The second operational amplifier U 2 Having one input and two outputs, the second operational amplifier U 2 Is a second MOS transistor M 2 Drain electrode of (C), second capacitor (C) 2 Another end, a third capacitor C 3 One end, a third MOS tube M 3 Is connected with the drain of the second operational amplifier U 2 A first output end of the (E) and a seventh MOS tube M p2 Gate of the second operational amplifier U 2 And a third capacitor C 3 Is arranged at the other end of (2)Fourth capacitor C 4 Is connected with one end of the seventh MOS tube M p2 Drain electrode of (d), third MOS transistor M 3 Gate electrode of (v), eighth MOS transistor M n2 Gate electrode of (v), eighth MOS transistor M n2 Drain electrode of (d), fourth MOS transistor M 4 The grid electrode of the fifth MOS tube M is connected with n1 Source electrode of (C), third MOS transistor M 3 Source electrode of (v), eighth MOS transistor M n2 Source electrode of (C), fourth MOS tube M 4 The source electrode of the fourth capacitor C is connected to 4 The other end of (C) is connected with a fourth MOS tube M 4 Is connected to the drain of the charge amplifying circuit and serves as the output terminal of the charge amplifying circuit.
The essence of the charge amplifying circuit is: a two-stage Miller integrator interspersed with a multiplying capacitor and a subthreshold current mirror accurately amplifies the charge signal output by the silicon drift detector, the specific circuit diagram of which is shown in fig. 2. The first-stage amplifying circuit is directly connected with the detector in a direct-current coupling way, and the first-stage charge amplifying multiple N 1 =32, second stage charge amplification N 2 =24. The leakage current of the detector provides DC current bias for the charge amplifying circuit, and because the leakage current of the detector is 10 pA-1 nA, other MOS tubes except the core operational amplifier in the circuit all work in a subthreshold region, and at the moment, the voltage V between the grid electrode and the source electrode of the MOS tube GS Slightly smaller than the threshold voltage V TH The tube is in a weak conduction state, and the drain current I of the tube D And V is equal to GS An exponential relationship is presented. The drain current formula of the MOS transistor in the subthreshold region is as follows:
wherein I is 0 Is an intrinsic current value of the MOS tube, is related to the width-to-length ratio, and is a subthreshold factor, V DS Is the voltage between the drain electrode and the source electrode of the MOS tube, V T Is thermal voltage, V T =kt/q, k is boltzmann constant, T is kelvin temperature, q is electron charge amount, V at normal temperature T Is about 26mV. According to the above, only V is taken DS >>V T Then the drain current of the MOS transistor is only V GS Control, work in subthreshold regionThe MOS tube of (2) can also be used for linear mirror current. In addition, the first MOS tube M 1 And a second MOS tube M 2 Third MOS transistor M 3 And a fourth MOS tube M 4 The current ratio is 32 times and 24 times respectively for subthreshold current mirror.
Accurate amplification of charge depends on the first capacitor C 1 And a second capacitor C 2 The integration of the charge on is completed. In the first stage of amplifying circuit, the input of the circuit is the charge-carrying signal Q output by the detector D Pulse current i of (2) 1 In the direction from point 1 to the anode of the detector, for Miller integrating capacitance C 1 Charging a first capacitor C 1 The upper electrode plate of (2) is connected with the input point 1 of the operational amplifier, can be regarded as virtual ground, and the charge is integrated into the first capacitor C 1 After the upper step, assuming that the potential rise of the lower electrode plate point 2 is DeltaV, the first capacitor C is integrated 1 Charge quantity Q on 1 Can be expressed as:
Q 1 ＝Q D ＝C 1 ·ΔV (3)
and a second capacitor C 2 The upper polar plate of (a) is also the input end of the operational amplifier, and is also virtual ground, the second capacitor C 2 And a first capacitor C 1 Common point 2, then integrate into the second capacitance C 2 Is of the charge quantity Q of (2) 2 Can be expressed as:
Q 2 ＝C 2 ·ΔV (4)
due to C 2 The capacitance value of (2) is C 1 N of (2) 1 Multiple times, then integrate into C 2 The charge amount on is C 1 N of (2) 1 Doubling, pair C 2 Charged i 2 The current comes from the second stage charge amplification circuit and the current direction flows from point 2 to point 3. From the above calculation, it can be concluded that the charge amount output by the detector is amplified by N by the first stage charge amplifying circuit 1 Multiple times and in the form of a current into the second stage circuit.
Also, in the second-stage charge amplifying circuit, the input signal is a charge carrying amount N 1 ·Q D Is the current signal i of (2) 2 Integrating the charge into a third capacitor C 3 On, make C 3 The potential of the lower plate point 4 of (C) decreases, and the same applies to the points 3 and 5The input end of the operational amplifier can be regarded as virtual short, and C 4 Has a capacitance value of C 3 N of (2) 2 Doubling, homomorphism integration to C 4 The charge quantity of (2) is integrated to C 3 N on 2 Multiple, so integrate to C 4 The charge quantity Q on the capacitor 4 Can be expressed as:
Q 4 ＝N 1 ·N 2 ·Q D (5)
charge-implemented amplification N 1 ·N 2 Doubling to C 4 The charging current is i 3 From the next stage circuit, the direction is shape flow to point 4, and the final charge amount entering the next stage circuit is Q 4 Two-stage accurate amplification of charges is realized.
To reduce gain nonlinearity of the charge amplifying circuit, a single-ended input-double-ended output operational amplifier is applied to a two-stage charge amplifying circuit for the first time, as shown in fig. 3. The first operational amplifier U 1 And a second operational amplifier U 2 The first operational amplifier U has the same structure 1 Comprises a ninth MOS tube M 9 Tenth MOS transistor M 10 Eleventh MOS tube M 11 Twelfth MOS transistor M 12 Thirteenth MOS tube M 13 Fourteenth MOS tube M 14 Fifteenth MOS tube M 15 Sixteenth MOS tube M 16 Seventeenth MOS tube M 17 Eighteenth MOS tube M 18 Nineteenth MOS pipe M 19 Twentieth MOS transistor M 20 Twenty-first MOS transistor M 21 Fifth capacitor C 5 Sixth capacitor C 6 Seventh capacitor C C . The ninth MOS tube M 9 Is taken as the grid electrode of the first operational amplifier U 1 Is a ninth MOS transistor M 9 The source electrode of the ninth MOS tube M is grounded 9 Drain electrode of (C), tenth MOS transistor M 10 Drain electrode of (d), eleventh MOS transistor M 11 The source electrode of the eleventh MOS tube M is connected with 11 Drain electrode of (d) twelfth MOS transistor M 12 Drain electrode of (d), fourteenth MOS transistor M 14 Gate of (C), seventh capacitor C C One end of the twelfth MOS tube M is connected with and used as a first output end of the first operational amplifier 12 Is a gate of (2)Electrode, sixth capacitor C 6 One end and twenty-first MOS tube M 21 Is connected with the grid electrode of the twenty-first MOS tube M 21 Drain electrode of (c) and twentieth MOS transistor M 20 The drain electrode of the fourteenth MOS tube M is connected with 14 Drain electrode of (d) twelfth MOS transistor M 12 Source of (C), sixth capacitance (C) 6 Another end, twenty-first MOS tube M 21 The source electrode of the eleventh MOS tube M is connected with the power supply VDD in parallel 11 Gate of (c) and twentieth MOS transistor M 20 Gate electrode of (E) MOS tube M 18 Grid electrode of (C) and sixteenth MOS tube M 16 Grid electrode of (C) and sixteenth MOS tube M 16 Drain electrode of (fifteenth) MOS transistor M 15 Is connected with the bias voltage I REF1 Sixteenth MOS tube M 16 Is connected with a fifteenth MOS tube M 15 The eighteenth MOS tube M 18 Is connected with bias voltage I REF2 The twentieth MOS tube M 20 Source electrode of (c) and nineteenth MOS transistor M 19 The nineteenth MOS transistor M is connected with the drain electrode of the transistor 19 Gate of seventeenth MOS transistor M 17 Gate of seventeenth MOS transistor M 17 Drain of (d), fifth capacitor C 5 One end, eighteenth MOS tube M 18 A tenth MOS transistor M connected with the source electrode 10 Gate of (d) and thirteenth MOS transistor M 13 The fifteenth MOS tube M is connected with the grid electrode 15 Seventeenth MOS transistor M 17 Source of (C) fifth capacitor 5 Another end, nineteenth MOS tube M 19 Source electrode of (S), tenth MOS transistor M 10 Source of (C) seventh capacitor C Another end, thirteenth MOS tube M 13 The sources of the fourteenth MOS tube M are connected together and connected to VSS 14 Source electrode of (d) and thirteenth MOS transistor M 13 Is connected to the drain of the operational amplifier and serves as a second output terminal of the operational amplifier.
Wherein NS (NMOS Current Source) is the gate voltage of the NMOS current mirror, ND (NMOS Diode) is the gate voltage of the NMOS Cascode transistor, and PS (PMOS Current Source) is the gate voltage of the PMOS current mirror. ND is formed by M in series 15 And M 16 Generating M 15 And M 16 The two MOS transistors connected in this way can be regarded as one MOS transistor with added channel lengths, and NS is formed by a diodeM of the grafting 17 Generating M 18 And M 20 For defining a current mirror M 17 、M 19 And M 10 To increase the matching of the current, PS by diode-connected M 21 And (3) generating. C (C) 5 And C 6 For filtering high-frequency noise of the front-stage bias circuit, the cut-off frequencies are g respectively m9 /2πC 1 、g m12 /2πC 2 ，g m9 Is a ninth MOS tube M 9 G is the transconductance of (g) m12 Is a twelfth MOS tube M 12 Is a transconductance of the first pair. In addition, due to the high-frequency conduction characteristic of the capacitor, C 5 And C 6 The high-frequency noise of the power supply can be coupled to the grid electrode of the MOS tube of the current mirror, so that the grid source voltage V of the MOS tube can be reduced GS The influence of power supply noise is reduced, and the influence of the power supply noise on the amplifier is reduced. Output ports OUT1 and IN are connected across Miller integrating capacitors, OUT2 is connected to MOS feedback network, capacitor C C The capacitance is compensated for frequency. With this design, the nonlinearity of the source follower does not affect the integration of charge on the capacitor, and a sufficient voltage margin can be ensured.
Simulation results
In the charge amplifying circuit, C is designed 1 Capacitance of 54.5fF, C 2 Capacitance value is 32×54.5fF, C 3 The capacitance value is 4 multiplied by 54.5fF, and after the input charge is amplified by 32 times by the first stage charge amplifying circuit, the integration is carried out on the input charge in C 3 And (3) upper part. Ideally, assuming that the input charge is 0.9fC, then C 1 Voltage rise of lower polar plate delta V 1 Should be 16.5mV, and C 3 Voltage drop DeltaV on lower plate 3 Should be 16.5×8=132 mV. Fig. 4 is a graph of simulated input pulse current, which is a peak current of 90nA and a pulse current with a duration of 20ns, and carries an amount of charge of 0.9fC, at this time, we assume that the total parasitic capacitance to ground of the input terminal of the charge amplifying circuit is 200fF. FIG. 5 is C 1 And C 3 Lower plate voltage response graph, where C 1 The voltage of the lower polar plate rises by about 16.47mV, C 3 The bottom plate dropped by about 131.04mV and the simulation results were slightly off-set from the ideal calculation, but the charge could be considered to have been amplified 32 times.
Claims (1)
1. A charge amplifying circuit for a front-end readout system of a silicon drift detector, characterized by: the detector comprises a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the input end of the first-stage amplifying circuit is connected with the detector in a direct current coupling way, the output end of the first-stage amplifying circuit is connected with the input end of the second-stage amplifying circuit, and the output end of the second-stage amplifying circuit outputs amplified signals;
the first-stage amplifying circuit comprises a first MOS tube, a second MOS tube, a fifth MOS tube, a sixth MOS tube, a first capacitor, a second capacitor and a first operational amplifier, wherein the first operational amplifier is provided with an input end and two output ends, the input end of the first operational amplifier, one end of the first capacitor and the drain electrode of the first MOS tube are connected and serve as the input end of the charge amplifying circuit, the first output end of the first operational amplifier, the other end of the first capacitor and one end of the second capacitor are connected, the second output end of the first operational amplifier is connected with the grid electrode of the fifth MOS tube, the drain electrode of the first MOS tube, the grid electrode of the sixth MOS tube, the drain electrode of the sixth MOS tube and the grid electrode of the second MOS tube are connected, the source electrode of the first MOS tube, the source electrode of the sixth MOS tube and the source electrode of the second MOS tube are connected together and grounded, and the drain electrode of the second MOS tube is connected with the other end of the second capacitor and serves as the output end of the first-stage amplifying circuit;
the second-stage amplifying circuit comprises a third MOS tube, a fourth MOS tube, a seventh MOS tube, an eighth MOS tube, a third capacitor, a fourth capacitor and a second operational amplifier, wherein the second operational amplifier is provided with an input end and two output ends, the input end of the second operational amplifier, the drain electrode of the second MOS tube, the other end of the second capacitor, one end of the third capacitor and the drain electrode of the third MOS tube are connected, the first output end of the second operational amplifier is connected with the grid electrode of the seventh MOS tube, the second output end of the second operational amplifier is connected with the other end of the third capacitor and one end of the fourth capacitor, the drain electrode of the seventh MOS tube, the grid electrode of the third MOS tube, the grid electrode of the eighth MOS tube, the drain electrode of the fourth MOS tube are connected, the source electrode of the fifth MOS tube, the source electrode of the eighth MOS tube and the source electrode of the fourth MOS tube are connected, and the other end of the fourth capacitor is connected with the drain electrode of the fourth MOS tube and serves as an output end of the amplifying circuit;
the first operational amplifier and the second operational amplifier have the same structure, the first operational amplifier comprises a ninth to a twentieth MOS tube and a fifth to a seventh capacitor, the grid electrode of the ninth MOS tube is used as the input end of the first operational amplifier, the source electrode of the ninth MOS tube is grounded, the drain electrode of the ninth MOS tube, the drain electrode of the tenth MOS tube and the source electrode of the eleventh MOS tube are connected, the drain electrode of the eleventh MOS tube, the drain electrode of the twelfth MOS tube, the grid electrode of the fourteenth MOS tube and one end of the seventh capacitor are connected and used as the first output end of the first operational amplifier, the grid electrode of the twelfth MOS tube, one end of the sixth capacitor and the grid electrode of the twenty first MOS tube are connected, the drain electrode of the fourteenth MOS tube, the source electrode of the twelfth MOS tube, the other end of the sixth capacitor and the source electrode of the twenty first MOS tube are connected, the grid electrode of the eleventh MOS tube, the grid electrode of the sixteenth MOS tube and the drain electrode of the sixteenth MOS tube are connected with a bias voltage I of the seventeenth MOS tube REF1 The source electrode of the sixteenth MOS tube is connected with the drain electrode of the fifteenth MOS tube, and the drain electrode of the eighteenth MOS tube is connected with the bias voltage I REF2 The source electrode of the twenty-eighth MOS tube is connected with the drain electrode of the nineteenth MOS tube, the grid electrode of the nineteenth MOS tube, the drain electrode of the seventeenth MOS tube, one end of the fifth capacitor and the source electrode of the eighteenth MOS tube are connected, the grid electrode of the tenth MOS tube is connected with the grid electrode of the thirteenth MOS tube, the source electrode of the fifteenth MOS tube, the source electrode of the seventeenth MOS tube, the other end of the fifth capacitor, the source electrode of the nineteenth MOS tube, the source electrode of the tenth MOS tube, the other end of the seventh capacitor and the source electrode of the thirteenth MOS tube are connected together and connected to VSS in parallel, and the source electrode of the fourteenth MOS tube is connected with the drain electrode of the thirteenth MOS tube and serves as a second output end of the operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010617850.1A CN111641396B (en) | 2020-06-30 | 2020-06-30 | Charge amplifying circuit for front-end reading system of silicon drift detector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010617850.1A CN111641396B (en) | 2020-06-30 | 2020-06-30 | Charge amplifying circuit for front-end reading system of silicon drift detector |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111641396A CN111641396A (en) | 2020-09-08 |
| CN111641396B true CN111641396B (en) | 2023-05-05 |
Family
ID=72331713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010617850.1A Active CN111641396B (en) | 2020-06-30 | 2020-06-30 | Charge amplifying circuit for front-end reading system of silicon drift detector |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111641396B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112326044B (en) * | 2020-09-25 | 2022-05-31 | 昆明物理研究所 | Logarithmic response ultrahigh-speed infrared focal plane pixel reading unit circuit |
| CN112564634A (en) * | 2020-12-02 | 2021-03-26 | 重庆中易智芯科技有限责任公司 | Front-end reading circuit applied to radiation detector |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079594A (en) * | 2006-05-22 | 2007-11-28 | 普诚科技股份有限公司 | Single-end input and dual-end output amplifier circuit and signal processing circuit |
| WO2016034740A1 (en) * | 2014-09-05 | 2016-03-10 | University College Cork - National University Of Ireland, Cork | Iq signal generator system and method |
| CN110417359A (en) * | 2018-04-27 | 2019-11-05 | 立积电子股份有限公司 | Amplifier |
| CN110460313A (en) * | 2019-08-22 | 2019-11-15 | 湘潭大学 | A kind of small-signal reading circuit for radiation detector |
-
2020
- 2020-06-30 CN CN202010617850.1A patent/CN111641396B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101079594A (en) * | 2006-05-22 | 2007-11-28 | 普诚科技股份有限公司 | Single-end input and dual-end output amplifier circuit and signal processing circuit |
| WO2016034740A1 (en) * | 2014-09-05 | 2016-03-10 | University College Cork - National University Of Ireland, Cork | Iq signal generator system and method |
| CN110417359A (en) * | 2018-04-27 | 2019-11-05 | 立积电子股份有限公司 | Amplifier |
| CN110460313A (en) * | 2019-08-22 | 2019-11-15 | 湘潭大学 | A kind of small-signal reading circuit for radiation detector |
Non-Patent Citations (3)
| Title |
|---|
| 唐俊雄 ; 唐明华 ; 杨锋 ; 张俊杰 ; 周益春 ; 郑学军 ; .全耗尽SOI MOSFETs阈值电压和电势分布的温度模型(英文).半导体学报.2008,(第01期),全文. * |
| 张海潮 ; 谢亮 ; 金湘亮 ; .高速硅微条探测器中流水线ADC的设计与实现.中国集成电路.2020,(第Z1期),全文. * |
| 朱颖 ; 何乐年 ; 严晓浪 ; .高速高增益运算放大器的设计及应用.电路与系统学报.2008,(第02期),全文. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111641396A (en) | 2020-09-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111641396B (en) | Charge amplifying circuit for front-end reading system of silicon drift detector | |
| Ma et al. | A 66-dB Linear Dynamic Range, 100-dB· $\Omega $ Transimpedance Gain TIA With High-Speed PDSH for LiDAR | |
| CN100549898C (en) | Utilize two-way asymmetric buffer structure to improve the LDO circuit of performance | |
| CN110912540A (en) | High-speed pre-amplification latch comparator with low dynamic mismatch | |
| US7408410B2 (en) | Apparatus for biasing a complementary metal-oxide semiconductor differential amplifier | |
| US6998913B2 (en) | Method and apparatus for linear low-frequency feedback in monolithic low-noise charge amplifiers | |
| CN111384940B (en) | High-linearity wide-swing CMOS voltage follower | |
| CN110247645B (en) | Voltage comparator | |
| Giroletti et al. | Charge Sensitive Amplifiers with Bi-and Trilinear Signal Compression Feature for LGAD Detectors | |
| US20240136985A1 (en) | Bias circuit and power amplifier | |
| CN210670009U (en) | High-speed pre-amplification latch comparator with low dynamic mismatch | |
| US11101776B2 (en) | Common source preamplifier for a MEMS capacitive sensor | |
| CN113779916A (en) | Charge sensitive preamplifier structure and design method | |
| CN109905105B (en) | Low-delay low-voltage current comparator and circuit module | |
| Castoldi et al. | Low-noise slew-rate free voltage preamplifier with current-limited continuous reset | |
| CN112564634A (en) | Front-end reading circuit applied to radiation detector | |
| Lu et al. | Design and Characterization of a Picosecond Timing ASIC in 55-nm CMOS | |
| Costantini et al. | A CMOS 0.13 µm low power front-end for GEM detectors | |
| Hu et al. | A new design of a low noise, low power consumption CMOS charge amplifier | |
| Dzahini et al. | A CMOS current preamplifier and shaper with 50/spl Omega/line driver for liquid argon preshower | |
| CN221328929U (en) | High-CMRR super source follower amplifier circuit for DCR detection | |
| Park et al. | A dual-feedback folded-cascode fully differential transimpedance amplifier in 65-nm CMOS | |
| CN118353391B (en) | Output stage circuit, electronic device and signal output method | |
| CN117277974A (en) | High-bandwidth transimpedance amplifier based on current buffer | |
| Zhao et al. | NTIMP1—A Fast Pulse Readout Chip With 1.2 V Power Supply Applied to the Diamond Detector in HIAF |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |