CN111554621A - Chip packaging method - Google Patents
Chip packaging method Download PDFInfo
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- CN111554621A CN111554621A CN202010365991.9A CN202010365991A CN111554621A CN 111554621 A CN111554621 A CN 111554621A CN 202010365991 A CN202010365991 A CN 202010365991A CN 111554621 A CN111554621 A CN 111554621A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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- Microelectronics & Electronic Packaging (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The application discloses a chip packaging method, which comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one packaging unit, and each packaging unit comprises a first chip, a second chip and a first plastic packaging layer which are adjacently arranged; forming a first rewiring layer on one side of the functional surfaces of the first chip and the second chip; arranging a connecting chip and a first conductive column on the first redistribution layer, wherein a connecting pad on a functional surface of the connecting chip is electrically connected with signal transmission area pads of the first chip and the second chip through the first redistribution layer, and the first conductive column is electrically connected with a non-signal transmission area pad through the first redistribution layer; and enabling the first conductive columns to face the package substrate with the flat surface, and enabling the first conductive columns to be directly and electrically connected with the package substrate through the solder. By means of the method, the signal transmission rate between the first chip and the second chip can be improved, and the performance of the packaging device is improved.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a chip packaging method.
Background
With the upgrading of electronic products, the requirements for chip packaging technology are increasing, and in the existing chip packaging technology, a chip is usually connected to a silicon interposer first, and then the silicon interposer is connected to a substrate. The electrical performance and the heat conduction performance of the packaged device formed in the mode are excellent, but the cost is high, and the silicon medium plate is high in brittleness, so that the stability of the packaged device is low. Therefore, it is necessary to develop a new packaging technology that can reduce the cost and form a packaged device with excellent performance.
Disclosure of Invention
The technical problem mainly solved by the application is to provide a chip packaging method, which can reduce the cost and improve the signal transmission rate between a first chip and a second chip.
In order to solve the technical problem, the application adopts a technical scheme that: a chip packaging method is provided, which comprises the following steps: providing a first packaging body, wherein the first packaging body comprises at least one packaging unit, and each packaging unit comprises a first chip, a second chip and a first plastic packaging layer which are adjacently arranged; the information transmission areas of the first chip and the second chip are arranged adjacently, and the first plastic packaging layer covers the side faces of the first chip and the second chip; forming a first rewiring layer on one side of the functional surfaces of the first chip and the second chip, wherein different areas of the first rewiring layer are respectively and electrically connected with a signal transmission area bonding pad and a non-signal transmission area bonding pad of the functional surfaces of the first chip and the second chip; a connection chip and a first conductive pillar are arranged on the first redistribution layer, wherein a connection pad on a functional surface of the connection chip is electrically connected with the signal transmission area pads of the first chip and the second chip through the first redistribution layer, and the first conductive pillar is electrically connected with the non-signal transmission area pad through the first redistribution layer; and enabling the first conductive columns to face the packaging substrate with the flat surface, and enabling the first conductive columns to be directly and electrically connected with the packaging substrate through solder.
Wherein the providing a first package comprises: providing a removable carrier plate, wherein the carrier plate is defined with at least one area, and one area corresponds to one packaging unit; adhering the first chip and the second chip which are adjacently arranged to the inner side of each area, wherein the non-functional surfaces of the first chip and the second chip face the carrier plate; forming the first plastic package layer on one side of the carrier plate, which is provided with the first chip and the second chip, wherein the first plastic package layer covers the functional surfaces and the side surfaces of the first chip and the second chip; and grinding the surface of one side, far away from the carrier plate, of the first plastic package layer until the positions, corresponding to the signal transmission area bonding pads and the non-signal transmission area bonding pads, of the first chip and the second chip are exposed out of the first plastic package layer.
Wherein the providing a first package comprises: providing a removable carrier plate, wherein the carrier plate is defined with at least one area, and one area corresponds to one packaging unit; adhering the first chip and the second chip which are adjacently arranged to the inner side of each area, wherein the functional surfaces of the first chip and the second chip face the carrier plate; forming the first plastic package layer on one side of the carrier plate, which is provided with the first chip and the second chip, wherein the first plastic package layer covers the non-functional surfaces and the side surfaces of the first chip and the second chip; and removing the carrier plate on one side of the functional surfaces of the first chip and the second chip so as to expose the functional surfaces of the first chip and the second chip.
Wherein, said forming a first rewiring layer on one side of the functional surfaces of said first chip and said second chip, different areas of said first rewiring layer being electrically connected to the signal transmission area pads and non-signal transmission area pads of said functional surfaces of said first chip and said second chip, respectively, comprises: forming a first passivation layer on one side of the functional surfaces of the first chip and the second chip, and forming a first opening at a position of the first passivation layer corresponding to the connection pad on the functional surfaces of the first chip and the second chip; and forming the first rewiring layer on the first passivation layer, wherein different areas of the first rewiring layer are respectively and electrically connected with the signal transmission area bonding pad and the non-signal transmission area bonding pad of the functional surfaces of the first chip and the second chip through the first passivation layer.
Wherein, set up connection chip and first conductive pillar on first rewiring layer, include: forming a second passivation layer on one side of the first rewiring layer, and forming a second opening in a position of the second passivation layer corresponding to the first rewiring layer, wherein the position of the second opening corresponds to a signal transmission area bonding pad and a non-signal transmission area bonding pad of the first chip and the second chip in a one-to-one mode; forming a first conductive pillar in the second opening corresponding to the non-signal transmission area pad, and forming a second conductive pillar in the second opening corresponding to the signal transmission area pad; and connecting the connecting pad on the functional surface of the connecting chip with the second conductive pillar in a bonding manner.
And the height of the second conductive pillar is smaller than that of the first conductive pillar.
After the first conductive pillars are directly and electrically connected to the package substrate through solder, a distance between the non-functional surface of the connection chip and the first redistribution layer is less than or equal to a height of the first conductive pillars.
Wherein, after the connection chip and the first conductive pillar are disposed on the first redistribution layer, the method includes: and forming a first underfill between the functional surface of the connection chip and the second passivation layer.
The first packaging body comprises at least two packaging units, each packaging unit comprises a first chip and a second chip which are adjacently arranged, and the first plastic packaging layer continuously covers all the packaging units; before the first conductive pillars are faced to the package substrate with a flat surface and the first conductive pillars are directly electrically connected with the package substrate through solder, the method further includes: and cutting off the area between the adjacent packaging units to obtain the packaging device containing the single packaging unit.
Wherein, after the first conductive pillar is faced to the package substrate with a flat surface and the first conductive pillar is directly electrically connected with the package substrate through the solder, the method further comprises: and forming a second underfill between the first redistribution layer and the package substrate.
The beneficial effect of this application is: the chip packaging method provided by the application adopts different connection modes for the signal transmission area and the non-signal transmission area of the main chip: for the signal transmission area, the connecting chip is adopted to connect the first chip and the second chip, so that the signal transmission rate between the first chip and the second chip is improved, and the performance of a packaged device is improved; for the non-signal transmission area, the first conductive columns and the solder are connected with the packaging substrate, so that the packaging cost can be reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart diagram illustrating an embodiment of a chip packaging method according to the present application;
FIG. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in FIG. 1;
FIG. 3 is a schematic flowchart of an embodiment corresponding to step S101 in FIG. 1;
FIG. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in FIG. 3;
FIG. 4b is a schematic structural diagram of an embodiment corresponding to step S202 in FIG. 3;
FIG. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in FIG. 3;
FIG. 4d is a schematic structural diagram of an embodiment corresponding to step S204 in FIG. 3;
FIG. 5 is a schematic flow chart of another embodiment corresponding to step S101 in FIG. 1;
FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S302 in FIG. 5;
FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S303 in FIG. 5;
FIG. 6c is a schematic structural diagram of an embodiment corresponding to step S304 in FIG. 5;
FIG. 7 is a schematic structural diagram of an embodiment corresponding to step S102 in FIG. 1;
FIG. 8 is a schematic structural diagram of an embodiment corresponding to step S103 in FIG. 1;
FIG. 9 is a schematic structural diagram of an embodiment corresponding to the step S103 in FIG. 1;
fig. 10 is a schematic structural diagram of an embodiment corresponding to step S104 in fig. 1.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a chip packaging method according to the present application, the chip packaging method including:
step S101: a first package body 20 is provided, wherein the first package body 20 includes at least one package unit, each package unit includes a first chip 22 and a second chip 24 disposed adjacently, and a first molding compound layer 26.
Specifically, referring to fig. 2, fig. 2 is a schematic structural diagram of an embodiment corresponding to step S101 in fig. 1. Fig. 2 is a schematic diagram only showing that the first package 20 includes a first chip 22 and a second chip 24, and in practical applications, the first chip 22 may be connected to at least one second chip 24. For example, the signal transmission region pads (not shown) are disposed at four corners of the first chip 22, and the number of the second chips 24 corresponding to one first chip 22 may be four, and the chip types of the four second chips 24 may be the same or different. The information transmission regions of the first chip 22 and the second chip 24 are adjacently disposed, that is, in the drawing, the positions where the first chip 22 and the second chip 24 are close to each other are information transmission regions, the positions where the first chip 22 and the second chip 24 are far from each other are non-signal transmission regions, and the first molding compound layer 26 covers the side surfaces of the first chip 22 and the second chip 24. In the figure, the first molding layer 26 is not filled with the patterns on both sides of the first chip 22 and the second chip 24.
In one embodiment, please refer to fig. 3, fig. 3 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:
step S201: a removable carrier 11 is provided, wherein the carrier 11 defines at least one area, and each area corresponds to one package unit.
Specifically, referring to fig. 4a, fig. 4a is a schematic structural diagram of an embodiment corresponding to step S201 in fig. 3, the carrier 11 in fig. 4a only schematically shows one of the regions, in practical application, the carrier 11 may be a larger region divided into a plurality of small regions, and the package of the first package 20 is started in each of the small regions.
Step S202: the first chip 22 and the second chip 24 adjacently disposed are adhered to the inner side of each region, and the non-functional surfaces (222 and 242) of the first chip 22 and the second chip 24 face the carrier 11.
Specifically, referring to fig. 4b, fig. 4b is a schematic structural diagram of an embodiment corresponding to the step S202 in fig. 3, in which the first chip 22 includes a functional surface 220 and a non-functional surface 222 that are disposed opposite to each other, the second chip 24 includes a functional surface 240 and a non-functional surface 242 that are disposed opposite to each other, the non-functional surface 222 of the first chip 22 and the non-functional surface 242 of the second chip 24 face the carrier 11, and the first chip 22 and the second chip 24 are adhered to the carrier 11 by a peelable adhesive such as a double-sided adhesive, and the carrier 11 may be formed of a rigid material such as metal, plastic, and the like.
Step S203: a first molding compound layer 26 is formed on the side of the carrier 11 where the first chip 22 and the second chip 24 are disposed, and the first molding compound layer 26 covers the functional surfaces (220 and 240) and the side surfaces of the first chip 22 and the second chip 24.
Specifically, referring to fig. 4c, fig. 4c is a schematic structural diagram of an embodiment corresponding to step S203 in fig. 3, in which the first molding compound layer 26 covers the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24, and the side surfaces of the first chip 22 and the second chip 24. The first molding compound 26 can effectively fix the first chip 22 and the second chip 24, and the material of the first molding compound 26 may be epoxy resin or the like.
Step S204: the surface of the first molding compound layer 26 away from the carrier 11 is ground until the corresponding positions of the signal transmission area pads (not shown) and the non-signal transmission area pads (not shown) of the first chip 22 and the second chip 24 are exposed from the first molding compound layer 26.
Specifically, referring to fig. 4d, fig. 4d is a schematic structural diagram of an embodiment corresponding to the step S204 in fig. 3, in which the first molding compound layer 26 covers the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24, and further the first molding compound layer 26 covering the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24 is ground, so that the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24 are exposed.
In one embodiment, please refer to fig. 5, fig. 5 is a flowchart illustrating an embodiment corresponding to step S101 in fig. 1, where the step S101 specifically includes:
step S301: a removable carrier 11 is provided, wherein the carrier 11 defines at least one area, and each area corresponds to one package unit.
Specifically, referring to fig. 4a again, the carrier 11 only schematically shows one of the regions, and in practical applications, the carrier 11 may be a larger region, divided into a plurality of small regions, and the package of the first package 20 is started in each small region.
Step S302: the first chip 22 and the second chip 24 adjacently disposed are adhered to the inner side of each area, and the functional surfaces (220 and 240) of the first chip 22 and the second chip 24 face the carrier 11.
Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to the step S302 in fig. 5, in which the first chip 22 includes a functional surface 220 and a non-functional surface 222 that are disposed opposite to each other, the second chip 24 includes a functional surface 240 and a non-functional surface 242 that are disposed opposite to each other, the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24 face the carrier 11, and the first chip 22 and the second chip 24 are adhered to the carrier 11 by a peelable adhesive such as a double-sided adhesive, and the carrier 11 may be formed of a hard material such as metal, plastic, and the like.
Step S303: a first molding compound layer 26 is formed on the side of the carrier 11 where the first chip 22 and the second chip 24 are disposed, and the first molding compound layer 26 covers the non-functional surfaces (222 and 242) and the side surfaces of the first chip 22 and the second chip 24.
Specifically, referring to fig. 6b, fig. 6b is a schematic structural diagram of an embodiment corresponding to step S303 in fig. 5, in which the first molding compound layer 26 covers the non-functional surface 222 of the first chip 22 and the functional surface 242 of the second chip 24, and the side surfaces of the first chip 22 and the second chip 24. The first molding compound 26 can effectively fix the first chip 22 and the second chip 24, and the material of the first molding compound 26 may be epoxy resin or the like.
Step S304: the carrier board 11 on the side of the functional surfaces (220 and 240) of the first chip 22 and the second chip 24 is removed to expose the functional surfaces (220 and 240) of the first chip 22 and the second chip 24.
Specifically, referring to fig. 6c, fig. 6c is a schematic structural view of an embodiment corresponding to step S304 in fig. 5, after the carrier 11 is peeled off, the functional surface 220 of the first chip 22 and the functional surface 240 of the second chip 24 are exposed.
Further, the first molding compound layer 26 on the non-functional side 222 of the first chip 22 and the non-functional side 242 of the second chip 24 can be further ground to expose the non-functional side 222 of the first chip 22 and the non-functional side 242 of the second chip 24 for heat dissipation of the first chip 22 and the second chip 24.
Step S102: a first redistribution layer 32 is formed on the functional surfaces (220 and 240) side of the first chip 22 and the second chip 24, and different regions of the first redistribution layer 32 are electrically connected to the signal transmission area pads and the non-signal transmission area pads of the functional surfaces (220 and 240) of the first chip 22 and the second chip 24, respectively.
Specifically, referring to fig. 7, fig. 7 is a schematic structural diagram of an embodiment corresponding to step S102 in fig. 1, in which a first passivation layer 30 is formed on one side of the functional surfaces (220 and 240) of the first chip 22 and the second chip 24, a first opening (not shown) is formed at a position of the first passivation layer 30 corresponding to a connection pad on the functional surfaces (220 and 240) of the first chip 22 and the second chip 24, and a first redistribution layer 32 is further formed on the first passivation layer 30, and different regions of the first redistribution layer 32 are electrically connected to a signal transmission region pad and a non-signal transmission region pad of the functional surfaces (220 and 240) of the first chip 22 and the second chip 24 through the first passivation layer 30.
Step S103: the connection chip 36 and the first conductive pillar 37 are provided on the first redistribution layer 32.
Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1, in which a second passivation layer 34 is formed on one side of the first redistribution layer 32, and second openings (not shown) are formed in positions of the second passivation layer 34 corresponding to the first redistribution layer 32, where the positions of the second openings correspond to the signal transmission area pads and the non-signal transmission area pads of the first chip 22 and the second chip 24 one-to-one, so that first conductive pillars 37 are formed in the second openings corresponding to the non-signal transmission area pads, and second conductive pillars 38 are formed in the second openings corresponding to the signal transmission area pads. The height of the second conductive posts 38 is smaller than the height of the first conductive posts 37. In the inner region surrounded by the first conductive pillar 38, the connection chip 36 is provided.
The connecting chip 36 includes a functional surface 360 and a non-functional surface 362 opposite to each other, and connecting pads (not shown) on the functional surface 360 of the connecting chip 36 are bonded to the second conductive pillars 38. The first conductive pillar 37 and the second conductive pillar 38 are made of at least one metal material selected from copper, nickel, gold, and silver.
Specifically, the bonding connection is achieved by using a thermocompression method or a soldering method or the like for the connection pad on the functional surface 360 of the connection chip 36 and/or the second conductive pillar 38. Therefore, the connection pads on the functional surface 360 of the connection chip 36 are electrically connected to the signal transmission area pads of the first chip 22 and the second chip 24 through the first redistribution layer 32, and the first conductive pillars 37 are electrically connected to the non-signal transmission area pads through the first redistribution layer 32.
In a specific application scenario, the first chip 22 is a CPU chip, the second chip 24 is a GPU chip, and the connection chip 36 is a silicon bridge, so that the signal transmission region between the CPU chip and the GPU chip performs signal transmission through the silicon bridge, thereby improving the signal transmission performance.
Further, referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment corresponding to step S103 in fig. 1, after the connection chip 36 and the first conductive pillar 37 are disposed on the first redistribution layer 32, a first underfill 42 needs to be formed between the functional surface 360 of the connection chip 36 and the second passivation layer 34, and the first underfill 42 fills a gap between the functional surface 360 of the connection chip 36 and the second passivation layer 34, so as to further fix the position of the connection chip 36, reduce the probability that the connection chip 36 is tilted in the subsequent process, and the first underfill 42 can protect the corresponding circuit structure on the functional surface 360 of the connection chip 36, and reduce the probability that the circuit structure is shorted.
Further, referring to fig. 1-9, the drawings in the present application are only schematic, and in practical applications, the carrier 11 includes a plurality of regions, the first package 20 is packaged in the plurality of regions of the carrier 11 at the same time, and the first package 20 includes at least two package units, each package unit includes a first chip 22 and a second chip 24 that are adjacently disposed, and the first molding compound layer 26 continuously covers all the package units, so that before the final packaging step S104, the region between the adjacent package units needs to be cut off to obtain the packaged device including a single package unit.
Step S104: the first conductive posts 37 are directed toward the package substrate 60 with a flat surface, and the first conductive posts 37 are directly electrically connected to the package substrate 60 through the solder 39.
Specifically, referring to fig. 10, fig. 10 is a schematic structural view of an embodiment corresponding to step S104 in fig. 1, in which the package substrate 60 and the first conductive pillars 37 are soldered by the solder 39, and the package substrate 60 and the first conductive pillars 37 are electrically connected. At this time, the distance between the non-functional surface 360 of the connection chip 36 and the first redistribution layer 32 is less than or equal to the height of the first conductive pillar 37.
Specifically, the solder 39 is provided immediately after the first conductive post 37 is produced, and may also be provided before the package substrate 60 is ready for soldering.
Further, after the first conductive pillars 37 are directly electrically connected to the package substrate 60 by the solder 39, the second underfill 52 is formed between the first redistribution layer 32 and the package substrate 60. The second underfill 52 can further fix the package substrate 60, the connection chip 36 and the first conductive pillars 37, so that they are more reliable.
In summary, the chip packaging method provided by the present application adopts different connection methods for the signal transmission region and the non-signal transmission region of the first chip 22 and the second chip 24: for the signal transmission region, the connection chip 36 is used to connect the first chip 22 and the second chip 24, so as to improve the signal transmission rate between the first chip 22 and the second chip 24 and improve the performance of the packaged device; for the non-signal transmission region, the first conductive pillar 37 and the solder 39 are connected with the package substrate 60, so that the package cost can be reduced.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A chip packaging method is characterized by comprising the following steps:
providing a first packaging body, wherein the first packaging body comprises at least one packaging unit, and each packaging unit comprises a first chip, a second chip and a first plastic packaging layer which are adjacently arranged; the information transmission areas of the first chip and the second chip are arranged adjacently, and the first plastic packaging layer covers the side faces of the first chip and the second chip;
forming a first rewiring layer on one side of the functional surfaces of the first chip and the second chip, wherein different areas of the first rewiring layer are respectively and electrically connected with a signal transmission area bonding pad and a non-signal transmission area bonding pad of the functional surfaces of the first chip and the second chip;
a connection chip and a first conductive pillar are arranged on the first redistribution layer, wherein a connection pad on a functional surface of the connection chip is electrically connected with the signal transmission area pads of the first chip and the second chip through the first redistribution layer, and the first conductive pillar is electrically connected with the non-signal transmission area pad through the first redistribution layer;
and enabling the first conductive columns to face the packaging substrate with the flat surface, and enabling the first conductive columns to be directly and electrically connected with the packaging substrate through solder.
2. The chip packaging method according to claim 1, wherein the providing the first package body comprises:
providing a removable carrier plate, wherein the carrier plate is defined with at least one area, and one area corresponds to one packaging unit;
adhering the first chip and the second chip which are adjacently arranged to the inner side of each area, wherein the non-functional surfaces of the first chip and the second chip face the carrier plate;
forming the first plastic package layer on one side of the carrier plate, which is provided with the first chip and the second chip, wherein the first plastic package layer covers the functional surfaces and the side surfaces of the first chip and the second chip;
and grinding the surface of one side, far away from the carrier plate, of the first plastic package layer until the positions, corresponding to the signal transmission area bonding pads and the non-signal transmission area bonding pads, of the first chip and the second chip are exposed out of the first plastic package layer.
3. The chip packaging method according to claim 1, wherein the providing the first package body comprises:
providing a removable carrier plate, wherein the carrier plate is defined with at least one area, and one area corresponds to one packaging unit;
adhering the first chip and the second chip which are adjacently arranged to the inner side of each area, wherein the functional surfaces of the first chip and the second chip face the carrier plate;
forming the first plastic package layer on one side of the carrier plate, which is provided with the first chip and the second chip, wherein the first plastic package layer covers the non-functional surfaces and the side surfaces of the first chip and the second chip;
and removing the carrier plate on one side of the functional surfaces of the first chip and the second chip so as to expose the functional surfaces of the first chip and the second chip.
4. The chip packaging method according to claim 1, wherein the forming of a first rewiring layer on the functional surface side of the first chip and the second chip, different areas of the first rewiring layer being electrically connected to signal transmission area pads and non-signal transmission area pads of the functional surfaces of the first chip and the second chip, respectively, comprises:
forming a first passivation layer on one side of the functional surfaces of the first chip and the second chip, and forming a first opening at a position of the first passivation layer corresponding to the connection pad on the functional surfaces of the first chip and the second chip;
and forming the first rewiring layer on the first passivation layer, wherein different areas of the first rewiring layer are respectively and electrically connected with the signal transmission area bonding pad and the non-signal transmission area bonding pad of the functional surfaces of the first chip and the second chip through the first passivation layer.
5. The chip packaging method according to claim 1, wherein the providing the connection chip and the first conductive pillar on the first redistribution layer includes:
forming a second passivation layer on one side of the first rewiring layer, and forming a second opening in a position of the second passivation layer corresponding to the first rewiring layer, wherein the position of the second opening corresponds to a signal transmission area bonding pad and a non-signal transmission area bonding pad of the first chip and the second chip in a one-to-one mode;
forming a first conductive pillar in the second opening corresponding to the non-signal transmission area pad, and forming a second conductive pillar in the second opening corresponding to the signal transmission area pad;
and connecting the connecting pad on the functional surface of the connecting chip with the second conductive pillar in a bonding manner.
6. The chip packaging method according to claim 5, wherein the height of the second conductive pillars is smaller than the height of the first conductive pillars.
7. The chip packaging method according to claim 6,
after the first conductive pillars are directly and electrically connected with the package substrate through solder, a distance between the non-functional surface of the connection chip and the first redistribution layer is less than or equal to the height of the first conductive pillars.
8. The chip packaging method according to claim 5, wherein after the disposing the connection chip and the first conductive pillar on the first redistribution layer, the method includes:
and forming a first underfill between the functional surface of the connection chip and the second passivation layer.
9. The chip packaging method according to claim 1,
the first packaging body comprises at least two packaging units, each packaging unit comprises a first chip and a second chip which are adjacently arranged, and the first plastic packaging layer continuously covers all the packaging units;
before the first conductive pillars are faced to the package substrate with a flat surface and the first conductive pillars are directly electrically connected with the package substrate through solder, the method further includes: and cutting off the area between the adjacent packaging units to obtain the packaging device containing the single packaging unit.
10. The chip packaging method according to claim 1, wherein after the step of directing the first conductive pillars toward a package substrate with a flat surface and electrically connecting the first conductive pillars with the package substrate directly through solder, the method further comprises:
and forming a second underfill between the first redistribution layer and the package substrate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010365991.9A CN111554621A (en) | 2020-04-30 | 2020-04-30 | Chip packaging method |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105355569A (en) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | Packaging method |
| CN107017238A (en) * | 2016-01-27 | 2017-08-04 | 艾马克科技公司 | Electronic installation |
| CN107104096A (en) * | 2017-05-19 | 2017-08-29 | 华为技术有限公司 | Chip-packaging structure and circuit structure |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105355569A (en) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | Packaging method |
| CN107017238A (en) * | 2016-01-27 | 2017-08-04 | 艾马克科技公司 | Electronic installation |
| CN107104096A (en) * | 2017-05-19 | 2017-08-29 | 华为技术有限公司 | Chip-packaging structure and circuit structure |
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Application publication date: 20200818 |