CN111445850A - Pixel circuit and driving method thereof, display device and driving method thereof - Google Patents

Pixel circuit and driving method thereof, display device and driving method thereof Download PDF

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Publication number
CN111445850A
CN111445850A CN202010365978.3A CN202010365978A CN111445850A CN 111445850 A CN111445850 A CN 111445850A CN 202010365978 A CN202010365978 A CN 202010365978A CN 111445850 A CN111445850 A CN 111445850A
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node
sub
control
circuit
transistor
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徐攀
李永谦
林奕呈
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of El Displays (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

The invention relates to the technical field of display, in particular to a pixel circuit and a driving method thereof, and a display device and a driving method thereof. For reducing the number of driver ICs (Integrated circuits). A pixel circuit comprises a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit and a light-emitting device; the first control sub-circuit is connected with the first initial signal end, the second initial signal end, the first control end, the second control end, the first node and the second node; the second control sub-circuit is connected with the first voltage end, the third control end and the third node; the writing sub-circuit is connected with a data signal end, a fourth control end and the first node; the driving sub-circuit is connected with the first node, the second node and the third node, and the light-emitting device is connected with the second node and a second voltage end.

Description

Pixel circuit and driving method thereof, display device and driving method thereof
Technical Field
The invention relates to the technical field of display, in particular to a pixel circuit and a driving method thereof, and a display device and a driving method thereof.
Background
Currently, with the continuous progress of self-light Emitting technology, the technology of self-light Emitting display devices, such as O L ED (Organic light Emitting Diode) display devices, mini light Emitting Diode display devices, micro light Emitting Diode display devices, etc., is becoming more mature, and accordingly, flexible display devices applicable to wearable devices, and special-shaped display devices on automobile instruments, etc., are receiving more attention.
Disclosure of Invention
The embodiment of the invention provides a pixel circuit, a driving method thereof, a display device and a driving method thereof. For reducing the number of driver ICs (Integrated circuits).
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
in one aspect, an embodiment of the present invention provides a pixel circuit, which includes a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit, and a light emitting device.
The first control sub-circuit is connected with a first initial signal end, a second initial signal end, a first control end, a second control end, a first node and a second node; the first control sub-circuit is used for outputting a signal of a first initial signal end to the first node under the control of the first control end in an initialization stage; under the control of the second control end, outputting a signal of the second initial signal end to the second node so as to initialize the potentials of the first node and the second node; and in the compensation stage, under the control of the first control end, continuously outputting the signal of the first initial signal end to the first node, and keeping the potential of the first node.
The second control sub-circuit is connected with the first voltage end, the third control end and the third node; the second control sub-circuit is used for outputting a signal of the first voltage end to the third node under the control of the third control end in a compensation stage and a light-emitting stage; and stopping outputting the signal of the first voltage end to the third node in a data writing stage.
The writing sub-circuit is connected with a data signal end, a fourth control end and the first node; the write-in sub-circuit is used for outputting a signal of the data signal end to the first node under the control of the fourth control end in a data write-in stage; and stopping outputting the signal of the data signal end to the first node in a light-emitting stage.
The driving sub-circuit is connected with the first node, the second node and the third node, and the light-emitting device is connected with the second node and a second voltage end; the driving sub-circuit is used for conducting a third node and the second node in a compensation stage and carrying out voltage compensation on the second node according to the potentials of the third node and the first node; and in a light-emitting stage, conducting the third node and the second node to enable the light-emitting device to emit light according to the potential of the second node and the potential of the second voltage end.
Optionally, the driving sub-circuit includes a driving transistor and a storage capacitor.
The grid electrode of the driving transistor is connected with the first node, the first pole of the driving transistor is connected with the third node, and the second pole of the driving transistor is connected with the second node.
The first pole of the storage capacitor is connected with the first node, and the second pole of the storage capacitor is connected with the second node.
Optionally, the first control sub-circuit includes a first sub-control circuit and a second sub-control circuit.
The first sub-control circuit is connected with a first initial signal end, a first control end and a first node; the first sub-control circuit is used for outputting a signal of the first initial signal end to the first node under the control of the first control end in the initialization stage, and initializing the potential of the first node; and in the compensation stage, under the control of the first control end, continuously outputting the signal of the first initial signal end to the first node, and keeping the potential of the first node.
The second sub-control circuit is connected with the second initial signal end, the second control end and the second node; the second sub-control circuit is configured to, in the initialization stage, output a signal of the second initial signal end to the second node under the control of the second control end, and initialize a potential of the second node.
Optionally, the first sub-control circuit includes a first transistor, and the second sub-control circuit includes a second transistor.
The grid electrode of the first transistor is connected with the first control end, the first pole of the first transistor is connected with the first initial signal end, and the second pole of the first transistor is connected with the first node.
And the grid electrode of the second transistor is connected with the second control end, the first pole of the second transistor is connected with the second initial signal end, and the second pole of the second transistor is connected with the second node.
Optionally, the second control sub-circuit includes a third transistor.
The grid electrode of the third transistor is connected with the third control end, the first pole is connected with the first voltage end, and the second pole is connected with the third node.
Optionally, the write sub-circuit includes a fourth transistor, a gate of the fourth transistor is connected to the fourth control terminal, a first pole of the fourth transistor is connected to the data signal terminal, and a second pole of the fourth transistor is connected to the first node.
Optionally, the pixel circuit further includes a third control sub-circuit, and the third control sub-circuit is connected to the second node, the fifth control terminal, and the light emitting device; the signal used for controlling the fifth control end is turned on or off in a compensation stage; and in the light-emitting stage, under the control of the fifth control terminal, conducting the second node and the second voltage terminal to enable the light-emitting device to emit light according to signals of the second node and the second voltage terminal.
Optionally, the third control sub-circuit comprises a fifth transistor.
And the grid electrode of the fifth transistor is connected with a fifth control end, the first pole of the fifth transistor is connected with the second node, and the second pole of the fifth transistor is connected with the light-emitting device.
In another aspect, an embodiment of the present invention provides a display device, which includes a plurality of sub-pixels, and each sub-pixel includes a pixel circuit as described above.
Optionally, each column of the sub-pixels is connected with a data line; the pixel array further comprises a plurality of multiplexing sub-circuits, each multiplexing sub-circuit is connected with a data signal input end and at least two data lines and used for writing data signals into the at least two data lines in the data writing phases of the sub-pixels connected with the at least two data lines under the condition that a row of sub-pixels are scanned, and the data writing phases of the sub-pixels connected with the at least two data lines are not overlapped.
Optionally, the multiplexing sub-circuit includes at least two sixth transistors, a gate of each sixth transistor is connected to a shunt control signal terminal, a first pole of each sixth transistor is connected to a data signal input terminal, and second poles of each sixth transistor are connected to the data lines in multiple rows in a one-to-one correspondence.
Optionally, the plurality of sub-pixels includes a plurality of sub-pixel groups distributed repeatedly, each sub-pixel group including at least three columns of sub-pixels of different colors; the sub-pixels connected with the at least two data lines have the same light emitting color; or, the sub-pixels connected with the at least two data lines are at least two columns of sub-pixels which are distributed continuously.
On the other hand, an embodiment of the present invention provides a driving method for a pixel circuit, which is applied to the pixel circuit described above, and the driving method includes: one frame period includes an initialization phase, a compensation phase, a data writing phase, and a light emitting phase.
Wherein the initialization phase comprises: under the control of a first control terminal, a signal of a first initial signal terminal is output to a first node, and under the control of a second control terminal, a signal of a second initial signal terminal is output to a second node, so that the potentials of the first node and the second node are initialized.
The compensation phase comprises: and under the control of a first control end, continuously outputting a signal of a first initial signal end to a first node, keeping the potential of the first node, and under the control of a third control end, outputting a signal of a first voltage end to a third node, conducting the third node and the second node through the driving sub-circuit, and performing voltage compensation on the second node according to the potentials of the third node and the first node.
The data writing phase comprises: and stopping outputting the signal of the first voltage end to the third node, and outputting the signal of the data signal end to the first node under the control of the fourth control end.
The lighting phase comprises: and stopping outputting the signal of the data signal end to the first node, outputting the signal of the first voltage end to a third node under the control of the third control end, and conducting the third node and the second node through the driving sub-circuit to enable the light-emitting device to emit light according to the potential of the second node and the potential of the second voltage end.
Optionally, the pixel circuit further includes a third control sub-circuit, and the third control sub-circuit is connected to the second node, the fifth control terminal, and the light emitting device.
The driving method further includes: in the compensation stage, controlling the signal of the fifth control end to be switched on or off; and in the light-emitting stage, under the control of the fifth control terminal, conducting the second node and the second voltage terminal to enable the light-emitting device to emit light according to signals of the second node and the second voltage terminal.
In another aspect, an embodiment of the present invention provides a driving method for a display device, where the driving method is applied to the display device, and the driving method includes: scanning each row of sub-pixels in sequence; and under the condition that one row of sub-pixels are scanned, writing data signals into the at least two data lines in the data writing phases of the sub-pixels connected with the at least two data lines, wherein the data writing phases of the sub-pixels connected with the at least two data lines are not overlapped.
The embodiment of the invention provides a pixel circuit and a driving method thereof, and a display device and a driving method thereof. Through setting up the second control sub-circuit, in the data write-in stage, through turning off the second control sub-circuit, can avoid the signal of first voltage end constantly to charge to the second node, make the continuous lifting of voltage of second node to when being used for multiplexing technique, can not make the voltage variation of second node cause the luminance difference because the data write-in time of first row sub-pixel and second sub-pixel is different.
Therefore, the pixel circuit can achieve the purpose of reducing the number of the drive ICs, and the cost of the display device can be reduced by reducing the number of the drive ICs, the narrow frame design of special-shaped products can be realized, and the effective display area of the special-shaped products is increased.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic top view of a display device according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a multiplexing sub-circuit disposed on a display device according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 4 is an equivalent circuit diagram of 4T1C according to an embodiment of the present invention;
FIG. 5 is a detailed circuit block diagram of FIG. 3 according to an embodiment of the present invention;
FIG. 6 is another detailed circuit block diagram of FIG. 3 according to an embodiment of the present invention;
FIG. 7 is a timing control diagram of each control terminal in FIG. 6 according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another pixel circuit according to an embodiment of the present invention;
FIG. 9 is a detailed circuit block diagram of FIG. 8 according to an embodiment of the present invention;
FIG. 10 is a timing control diagram of each control terminal in FIG. 9 according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of another embodiment of a multiplexing sub-circuit disposed on a display device according to the present invention;
FIG. 12 is a timing control diagram of the control terminals and the data signal terminals of the pixel circuit of FIG. 11 according to an embodiment of the present invention;
fig. 13 is a flowchart illustrating a driving method of a display device according to an embodiment of the present invention.
Reference numeral 1-a display device, P-sub-pixels, 100-pixel circuits, 200-multiplexing sub-circuits, Data in-Data signal input terminals, P1-first column sub-pixels, P2-second column sub-pixels, LGate(n)-a gate line; 10-a first control sub-circuit; 20-a second control sub-circuit; 30-a write subcircuit; 40-a drive sub-circuit; 50-a light emitting device; vin 1-first initial signal terminal; vin 2-second initial signal terminal; s1-a first control end; s2-a second control end; n-a first node; s-a second node; VDD — first voltage terminal; s3 — a third control terminal; m-a third node; Data-Data signal terminal; s4-a fourth control end; VSS-second voltage terminal; a DTFT-drive transistor; cst — storage capacitance; 101-a first sub-control circuit; 102-a second sub-control circuit; t1 — first transistor; t2 — second transistor; t3 — third transistor; t4 — fourth transistor; 60-a third control sub-circuit; s5-a fifth control end; t5 — fifth transistor; cOLED-intrinsic capacitance of O L ED, T6-sixth transistor, L g 1-first shunt control signal, L g 2-second shunt control signal, LData1L first column data lineData2-a second column of data lines.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a display device 1, where the display device 1 is a display panel, or the display device 1 includes a display panel, such as a mobile phone, a tablet computer, a notebook computer, a Personal Digital Assistant (PDA), a vehicle-mounted computer, and the like. The embodiment of the present application does not specifically limit the specific form of the display device.
In some embodiments, as shown in fig. 1, the display device 1 comprises a plurality of sub-pixels P. For convenience of description, the sub-pixels P are arranged in a matrix form as an example in this embodiment. At this time, the sub-pixels P arranged in a line in the horizontal direction X are referred to as sub-pixels in the same row, and the sub-pixels P arranged in a line in the vertical direction Y are referred to as sub-pixels in the same column. The same row of subpixels P may be connected to one gate line, and the same column of subpixels P may be connected to one data line.
Further, as shown in fig. 2, one pixel circuit 100 is provided in one sub-pixel P, and the pixel circuit 100 is used to control the sub-pixel P to perform display. In other embodiments, as shown in fig. 2, the display device further includes a plurality of multiplexing sub-circuits 200, each multiplexing sub-circuit 200 is connected to a Data signal input terminal Data in and at least two Data lines, and is configured to, when a row of sub-pixels P is scanned, write Data signals Data to the at least two Data lines in the Data writing phases of the sub-pixels P connected to the at least two Data lines, and there is no overlap between the Data writing phases of the sub-pixels P connected to the at least two Data lines.
In some embodiments, the plurality of sub-pixels P includes a plurality of sub-pixel groups repeatedly distributed, each sub-pixel group including at least three sub-pixels P of different colors; the sub-pixels P connected with at least two data lines have the same light emitting color; or, the sub-pixels P connected to the at least two data lines are at least two sub-pixels P that are continuously distributed.
Illustratively, the at least three different color sub-pixels P may be a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B). In this case, the sub-pixels P connected to at least two data lines have the same emission color, which means that one multiplexing sub-circuit 200 is connected to at least two rows of sub-pixels P spaced apart and having the same color. The sub-pixels P connected to the at least two data lines are at least two rows of sub-pixels P distributed continuously, that is, if the sub-pixels P connected to the at least two data lines are two rows of sub-pixels P distributed continuously, two adjacent rows of sub-pixels P, such as RG, GB, BR, are respectively connected to one multiplexing sub-circuit 200; if the sub-pixels P connected by at least two data lines are three rows of sub-pixels P distributed consecutively, one sub-pixel group RGB is connected to one multiplexing sub-circuit 200.
Here, taking two columns of sub-pixels P connected to at least two data lines as an example, as shown in fig. 2, the two columns of sub-pixels P are respectively called a first column of sub-pixels P1 and a second column of sub-pixels P2, and when the multiplexing sub-circuit 200 is used for driving, one row of gate lines L is scannedGate(n)In the case of on, after writing data for the first column of subpixels P1, data for the second column of subpixels P2 is written, followed by the gate line L for bothGate(n)Are turned off simultaneously, which causes the data writing time of the first column subpixel P1 and the second column subpixel P2 to be different. I.e. the data writing time of the former is longer than that of the latter. In order to ensure the accuracy of data writing of the sub-pixel P, the operating state of the sub-pixel P needs to be stable during the data writing phase.
In view of this, the first embodiment of the present invention provides a pixel circuit 100, as shown in fig. 3, including a first control sub-circuit 10, a second control sub-circuit 20, a writing sub-circuit 30, a driving sub-circuit 40, and a light emitting device 50.
The first control sub-circuit 10 is connected to the first initial signal terminal Vin1, the second initial signal terminal Vin2, the first control terminal S1, the second control terminal S2, the first node N and the second node S; the first control sub-circuit 10 is configured to output a signal of a first initial signal terminal Vin1 to a first node N under the control of the first control terminal S1 during an initialization phase. And outputting a signal of a second initial signal terminal Vin2 to the second node S under the control of the second control terminal S2 to initialize the potentials of the first node N and the second node S. And in the compensation phase, under the control of the first control terminal S1, continuing to output the signal of the first initial signal terminal Vin1 to the first node N, and maintaining the potential of the first node N.
The second control sub-circuit 20 is connected to the first voltage terminal VDD, the third control terminal S3 and the third node M; the second control sub-circuit 20 is configured to output the signal of the first voltage terminal VDD to the third node M under the control of the third control terminal S3 in the compensation phase and the light emitting phase. In the data writing phase, the signal of the first voltage terminal VDD stops being output to the third node M.
The write sub-circuit 30 is connected with the Data signal terminal Data, the fourth control terminal S4 and the first node N; the write sub-circuit 30 is configured to output a signal of the Data signal terminal Data to the first node N under the control of the fourth control terminal S4 in the Data write phase; and stopping outputting the signal of the Data signal terminal Data to the first node N in the light emitting phase.
The driving sub-circuit 40 is connected to the first node N, the second node S and the third node M, and the light emitting device 50 is connected to the second node S and the second voltage terminal VSS; the driving sub-circuit 40 is configured to, in a compensation stage, turn on the third node M and the second node S, and perform voltage compensation on the second node S according to potentials of the third node M and the first node N; and in the light emitting stage, the third node M and the second node S are turned on, so that the light emitting device 50 emits light according to the potentials of the second node S and the second voltage terminal VSS.
Assuming that the pixel circuit 100 does not have the second control sub-circuit 20 between the third node M and the first voltage terminal VDD, as shown in fig. 4, it is an equivalent circuit diagram of a 4T1C pixel circuit, in the data writing phase, since the driving transistor DTFT is turned on, the signal of the first voltage terminal VDD is continuously output to the point S, which makes the point S continuously rise due to the current charging of the first voltage terminal VDD, that is, in the data writing phase, the non-uniformity of the driving transistor DTFT is still compensated, the higher the mobility of the driving transistor DTFT is, the larger the point S rises, and the smaller the gate-drain voltage Vgs of the driving transistor DTFT is in light emitting, conversely, the smaller the mobility of the driving transistor DTFT is, the smaller the point S rises, and the larger the Vgs in light emitting is. Further, when the multiplexing circuit 200 is used to drive the subpixels, the data writing time of the first column of subpixels P1 is different from that of the second column of subpixels P2, and thus the amount of change in voltage at the point S is also different, and particularly, when a plurality of columns of subpixels (three or more) are connected to one multiplexing circuit 200, the data writing time of the first column of subpixels is much longer than the data writing time of the last column of subpixels, resulting in a difference in luminance between the columns of subpixels.
In the embodiment, by providing the second control sub-circuit 20, in the data writing stage, by turning off the second control sub-circuit 20, the second node S can be prevented from being continuously charged by the signal of the first voltage terminal VDD, and the voltage of the second node S is continuously raised, so that when the multiplexing technique is used, the brightness difference caused by the difference in the voltage variation of the second node S due to the difference in the data writing time of the first column of sub-pixels P1 and the second column of sub-pixels P2 is avoided.
Therefore, the pixel circuit 100 can reduce the number of driver ICs, reduce the cost of the display device, realize the narrow frame design of the special-shaped product, and increase the effective display area of the special-shaped product.
Next, specific circuit structures of the first control sub-circuit 10, the second control sub-circuit 20, the writing sub-circuit 30, and the driving sub-circuit 40 included in the pixel circuit 100 according to the first embodiment of the present invention will be exemplarily described.
As shown in fig. 5 and 6, the driving sub-circuit 40 may include a driving transistor DTFT having a gate connected to a first node N, a first pole connected to a third node M, a second pole connected to a second node S, and a storage capacitor Cst having a first pole connected to the first node N and a second pole connected to the second node S.
As shown in fig. 5, the first control sub-circuit 10 includes a first sub-control circuit 101, and a second sub-control circuit 102; the first sub-control circuit 101 is connected to the first initial signal terminal Vin1, the first control terminal S1 and the first node N, and the first sub-control circuit is configured to output a signal of the first initial signal terminal Vin1 to the first node N under the control of the first control terminal S1 during an initialization phase, so as to initialize a potential of the first node N; and in the compensation phase, under the control of the first control terminal S1, continuing to output the signal of the first initial signal terminal Vin1 to the first node N, and maintaining the potential of the first node N.
The second sub-control circuit 102 is connected to the second initial signal terminal Vin2, the second control terminal S2 and the second node S, and is configured to output a signal of the second initial signal terminal Vin2 to the second node S under the control of the second control terminal S2 during an initialization phase, so as to initialize a potential of the second node S.
Illustratively, as shown in fig. 5 and 6, the first sub-control circuit 101 includes a first transistor T1, and the second sub-control circuit 102 includes a second transistor T2; a gate of the first transistor T1 is connected to the first control terminal S1, a first pole is connected to the first initial signal terminal Vin1, and a second pole is connected to the first node N; the gate of the second transistor T2 is connected to the second control terminal S2, the first pole is connected to the second initial signal terminal Vin2, and the second pole is connected to the second node S.
As shown in fig. 5 and 6, the second control sub-circuit 20 includes a third transistor T3, a gate of the third transistor T3 is connected to the third control terminal S3, a first pole is connected to the first voltage terminal VDD, and a second pole is connected to the third node M. The third transistor T3 is configured to output a signal of the first voltage terminal VDD to the third node M under the control of the third control terminal S3 during the compensation phase and the light emitting phase. And stopping outputting the signal of the first voltage terminal VDD to the third node M in the data writing stage.
As shown in fig. 5 and 6, the write sub-circuit 30 includes a fourth transistor T4, a gate of the fourth transistor T4 is connected to the fourth control terminal S4, a first pole is connected to the Data signal terminal Data, and a second pole is connected to the first node N. The fourth transistor T4 is configured to output a signal of the Data signal terminal Data to the first node N under the control of the fourth control terminal S4 during the Data write phase.
In some embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the driving transistor DTFT are all P-type transistors or all N-type transistors.
Having described the specific circuit structures of the first control sub-circuit 10, the second control sub-circuit 20, the driving sub-circuit 40 and the writing sub-circuit 30 provided in the first embodiment of the present invention, as shown in fig. 7, the pixel circuit 100 provided in some embodiments of the present invention includes: the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the driving transistor DTFT, and the storage capacitor Cst are connected as described above. The transistors can be P-type transistors or N-type transistors.
In some embodiments, as shown in fig. 5 and 6, the light emitting device 50 includes at least one light emitting diode. In a case where the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the driving transistor DTFT are all P-type transistors, the second voltage terminal VSS may be grounded, or 0V, and accordingly, the first voltage terminal VDD may be greater than 0V.
In some embodiments, the light emitting diode is a micro L ED (micro L ED), a mini L ED (mini L ED), or an organic light emitting diode, which is not limited by the embodiments of the present invention.
It should be noted that the transistor used in the circuit provided in the embodiment of the present invention may be a thin film transistor, a field effect transistor, or another switching device with the same characteristics, and the embodiment of the present invention is not limited thereto.
In some embodiments, the first pole of each transistor employed by the pixel circuit 100 is one of a source and a drain of the transistor, and the second pole is the other of the source and the drain of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain may not be different in structure, that is, the first and the second poles of the transistor in the embodiment of the present invention may not be different in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.
Based on the above description of the specific circuit structures of the first control sub-circuit 10, the second control circuit 20, the writing sub-circuit 30 and the driving sub-circuit 40 included in the pixel circuit 100 according to the first embodiment, a driving method of the pixel circuit 100 will be described next, taking the pixel circuit 100 shown in fig. 6 as an example, the description will be given with reference to the timing chart shown in fig. 7, where the pixel circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DTFT and a storage capacitor Cst, and the transistors are all N-type transistors, and the light emitting device 50 includes an O L ED.
The driving method includes:
one frame period includes an initialization phase, a compensation phase, a data writing phase, and a light emitting phase.
The initialization phase comprises the following steps: the signal of the first initial signal terminal Vin1 is output to the first node N under the control of the first control terminal, and the signal of the second initial signal terminal Vin2 is output to the second node S under the control of the second control terminal, so that the potentials of the first node N and the second node S are initialized.
Illustratively, high level signals are output at the first and second control terminals S1 and S2, the first and second transistors T1 and T2 are turned on, the remaining transistors are turned off, a signal of the first initial voltage terminal Vin1 is output to the first node N, and a signal of the second initial voltage terminal Vin2 is output to the second node S. An initial gate-drain voltage Vgs-Vin 2-Vin1 is written to the driving transistor DTFT.
At this stage, if the second control sub-circuit 20 is not turned off, the voltage Vs of the initialized second node S is greater than Vin1, and the compensation range of the threshold voltage Vth of the driving transistor DTFT is narrowed.
The compensation phase comprises: under the control of the first control terminal S1, the second control sub-circuit 20 outputs the signal of the first initial signal terminal Vin1 to the first node N to maintain the potential of the first node N, outputs the signal of the first voltage terminal VDD to the third node M under the control of the third control terminal, turns on the third node M and the second node S through the driving sub-circuit 40, and performs voltage compensation on the second node S according to the potentials of the third node M and the first node N.
For example, the first control terminal S1 continues to output the high-level signal, keeping the first transistor T1 turned on, the second transistor T2 turned off, and the third transistor T3 turned on, and outputting the signal of the first voltage terminal VDD to the second node S until Vgs of the driving transistor DTFT becomes Vth, and at this time, the anode voltage Vs of the O L ED becomes Vin2 to Vin 1.
The data writing phase comprises the following steps: the signal of the first voltage terminal VDD stops being output to the third node S, and the signal of the Data signal terminal Data is output to the first node N under the control of the fourth control terminal S4.
Illustratively, the fourth transistor T4 is turned on and the remaining transistors are turned off, and there is no current in the driving transistor DTFT, and the change of the second node S is only a capacitive coupling effect. Thus VN is VData, Vs is a (VData-Vin2) + Vin 2-Vth; then Vgs ═ 1-a (VData-Vin2) + Vth where a is the capacitive coupling coefficient and a ═ Cst/(Cst + C)OLED)，COLEDIs the intrinsic capacitance of the parallel O L ED.
At this stage, if the third transistor T3 is not turned off, since the driving transistor DTFT is turned on, there is a current in the driving transistor DTFT, and the voltage of the second node S rises quickly, so that Vgs after data writing is very small, even as small as near Vth, and light cannot be emitted. Therefore, in the Data writing phase, by turning off the third transistor T3, there is no current in the driving transistor DTFT, the second node S does not change due to the charging of the first voltage terminal VDD current (the second node S has a small capacitance, so the charging is faster, resulting in too fast voltage rise of the second node S), but only plays a role of capacitive coupling, and Data loss of the driving IC can be reduced.
The light-emitting stage comprises: the signal of the Data signal terminal Data is stopped from being output to the first node N, and under the control of the third control terminal S3, the signal of the first voltage terminal VDD is output to the third node M, and the third node M and the second node S are turned on, so that the light emitting device 50 emits light according to the potential of the second node S and the potential of the second voltage terminal VSS.
Illustratively, the third transistor T3 is turned on, the remaining transistors are turned off, the pixel emits light, IOLED＝K[(1-a)(VData-Vin2)]Λ 2, independent of the threshold voltage Vth, to achieve internal compensation.
On the basis of the first embodiment, as shown in fig. 8, a second embodiment of the present invention provides a pixel circuit 100, where the pixel circuit 100 includes, in addition to the first control sub-circuit 10, the second control sub-circuit 20, the writing sub-circuit 30, the driving sub-circuit 40, and the light emitting device 50 provided in the first embodiment, a third control sub-circuit 60, and the third control sub-circuit 60 is connected to the second node S, the fifth control terminal S5, and the light emitting device 50; and the signal for controlling the fifth control terminal S5 to be turned on or off in the compensation stage. And in the light emitting phase, the second node S and the second voltage terminal VSS are turned on under the control of the fifth control terminal S5, so that the light emitting device 50 emits light according to signals of the second node S and the second voltage terminal VSS.
Illustratively, as shown in fig. 9, the third control sub-circuit 60 includes a fifth transistor T5; the fifth transistor T5 has a gate connected to the fifth control terminal S5, a first terminal connected to the second node S, and a second terminal connected to the light emitting device 50. The fifth transistor T5 is configured to conduct the second node S with the second voltage terminal VSS under the control of the fifth control terminal S5, so that the light emitting device 50 emits light according to the voltages of the second node S and the second voltage terminal VSS.
It should be noted that the fifth transistor T5 and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4 and the driving transistor DTFT described in the first embodiment are of the same type, such as both P-type transistors or both N-type transistors.
The specific circuit structures of the first control sub-circuit 10, the second control sub-circuit 20, the driving sub-circuit 40, the writing sub-circuit 30 and the third control sub-circuit 60 provided by the second embodiment of the present invention have been described above, respectively, and next, the driving method of the pixel circuit 100 provided by the second embodiment is described below, taking the pixel circuit 100 shown in fig. 9 as an example and combining with the timing diagram shown in fig. 10, the pixel circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a driving transistor DTFT and a storage capacitor Cst, and the transistors are all N-type transistors, and the light emitting device 50 includes an O L ED.
The driving method includes:
one frame period includes an initialization phase, a compensation phase, a data writing phase, and a light emitting phase.
The driving method of the initialization stage and the compensation stage is substantially the same as that of the first embodiment, and is not described herein again. The difference is that:
in the compensation phase, the capacitor connected to the second node S has the storage capacitor Cst and the parasitic capacitances of the driving transistor DTFT, the second transistor T2 and the fifth transistor T5, and is not connected to COLEDThis large capacitor is connected, so the voltage at the second node S rises relatively quickly until Vgs becomes Vth, at which time Vs becomes Vin2-Vth, in other words, the time that Vgs reaches Vth is relatively short, so the compensation time is relatively short.
In the data writing phase, since the fourth transistor T4 is turned on, the third transistor T3 is turned off, and there is no current in the driving transistor DTFT, the change of the second node S is only a capacitive coupling effect, and thus VN is VData, Vs is a (VData-Vin2) + Vin 2-Vth; then Vgs is (1-a) (VData-Vin2) + Vth, where a is the capacitive coupling coefficient, a is Cst/(Cst + C0), and C0 is the sum of the parasitic capacitances of the transistors connected at the second node S, which is typically very small. Therefore, Vgs has only a relatively small part of the capacitive coupling loss (a is close to 1), and the data loss of the driver IC can be further reduced as compared with the case where the fifth transistor T5 is not provided.
In the light emitting period, the method further includes turning on the fifth transistor T5 to turn on the second node S and the second voltage terminal VSS, so that the light emitting device emits light according to the voltages of the second node S and the second voltage terminal VSS.
In summary, in the second embodiment, the second node S is connected to the capacitor O L ED and the intrinsic capacitor C of O L ED in the first embodimentOLEDThe larger, charged capacitor of the second node S comprises the stored energyCapacitance Cst, parasitic capacitance of transistor, and intrinsic capacitance C of O L EDOLEDThe former two are far smaller than O L ED intrinsic capacitance COLEDIn contrast, by providing the fifth transistor T5, the capacitance of the O L ED and the driving transistor DTFT can be disconnected, and the intrinsic capacitance C of the O L ED is removedOLEDIn the compensation, only the storage capacitor Cst and the parasitic capacitor of the transistor are charged, so that the time required to reach the target voltage is greatly reduced.
In addition to the first and second embodiments, a detailed description is given of a specific connection relationship between the multiplexing sub-circuit 200 and the pixel circuit 100 and a driving method of a display device having the multiplexing sub-circuit 200 in the third embodiment of the present invention.
In some embodiments, as shown in fig. 2 and 11, the multiplexing sub-circuit 200 includes at least two sixth transistors T6, each sixth transistor T6 has a gate connected to a shunt control signal terminal, a first pole connected to the Data signal input terminal Data in, and a second pole connected to at least two columns of Data lines in a one-to-one correspondence.
In the case where the multiplexing sub-circuit 200 includes two sixth transistors T6, for example, the left sixth transistor T6 is connected to one of the branch control signal terminals (referred to as the first branch control signal terminal L g1), the right sixth transistor T6 is connected to the other branch control signal terminal (referred to as the second branch control signal terminal L g2), and accordingly, as shown in fig. 2 and 11, the left sixth transistor T6 is connected to one of the columns of data lines (referred to as the first column of data lines L)Data1) The sixth transistor T6 on the right is connected to another column data line (referred to as the second column data line L)Data2)。
In other embodiments, the gates of the sixth transistors T6 at the same position in the plurality of multiplexing sub-circuits 200 are connected to the same shunt control signal terminal.
Here, still taking the case that the multiplexing sub-circuit 200 includes two sixth transistors T6 as an example, the sixth transistor T6 located on the left side of the multiplexing sub-circuits 200 is connected to the same shunt control signal terminal (i.e., the first shunt control signal terminal L g1), and the sixth transistor located on the right side is connected to the same shunt control signal terminal (i.e., the second shunt control signal terminal L g 2).
In the following description, the display device 1 shown in fig. 11 is taken as an example and is described in conjunction with the timing chart shown in fig. 12, the pixel circuit 100 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor DTFT, and a storage capacitor Cst, the light emitting device 50 includes an O L ED, and one multiplexing sub-circuit 200 includes at least two sixth transistors T6.
As shown in fig. 13, the driving method includes:
s1) sequentially scans the rows of sub-pixels P.
For example, the sequential scanning of the rows of the subpixels P may be from the 1 st row to the 6 th row, i.e., progressive scanning. It is also possible to scan lines 1, 3, and 5 first and then scan lines 2, 4, and 6.
S2) in the case where one row of the subpixels P is scanned, data signals are written to the at least two data lines in the data writing phases of the subpixels P connected to the at least two data lines, respectively, without overlapping between the data writing phases of the subpixels P connected to the at least two data lines.
Here, taking as an example that the sub-pixels P corresponding to the two data lines connected to one multiplexing sub-circuit 200 are the sub-pixels P1 in the first column and the sub-pixels P2 in the second column, and the sub-pixels P scanned to the nth row, a driving method in the data writing stage will be exemplarily described.
In the data writing phase, the nth row gate line LGate(n)Turning on the fourth transistor T4 in the first and second columns of sub-pixels in the row, and simultaneously turning on the sixth transistor T6 connected to the first column of sub-pixels P1 to the data line L connected to the first column of sub-pixels P1Data1Data voltage is input, and through capacitive coupling, Vgs _1 ═ K [ (1-a) (VData _1-Vin2)]Lamb 2, then the data line L corresponding to the first column of sub-pixels P1 is closedData1Sixth of the connectionA transistor T6 for turning on a sixth transistor T6 connected to the second column of sub-pixels P2, and a data line L connected to the second column of sub-pixels P2Data2Data voltage is input, and after capacitive coupling, Vgs _2 ═ K [ (1-a) (VData _2-Vin2)]Λ 2, where Vgs _1 is Vgs of the driving transistor DTFT in the first column of sub-pixels P1 of the row, Vgs _2 is Vgs of the driving transistor DTFT in the second column of sub-pixels P2 of the row, and VData _1 is a data line L connected to the first column of sub-pixels P1Data1The input Data voltage value VData _2 is the Data line L connected to the second column of sub-pixels P2Data2A is the intrinsic capacitance C of the storage capacitors Cst and O L ED across the gate-drain of the driving transistor DTFT in the subpixel POLEDA to Cst/(Cst + C)OLED)，COLEDIs the intrinsic capacitance of the parallel O L ED.
The display device provided by the third embodiment of the present invention has the same beneficial technical effects as the first embodiment of the present invention, and specific reference may be made to the description of the first embodiment of the present invention, which is not repeated herein.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (15)

1. A pixel circuit comprises a first control sub-circuit, a second control sub-circuit, a writing sub-circuit, a driving sub-circuit and a light emitting device;
the first control sub-circuit is connected with a first initial signal end, a second initial signal end, a first control end, a second control end, a first node and a second node; the first control sub-circuit is used for outputting a signal of a first initial signal end to the first node under the control of the first control end in an initialization stage; under the control of the second control end, outputting a signal of the second initial signal end to the second node so as to initialize the potentials of the first node and the second node; in the compensation stage, under the control of a first control end, a signal of a first initial signal end is continuously output to the first node, and the potential of the first node is maintained;
the second control sub-circuit is connected with the first voltage end, the third control end and the third node; the second control sub-circuit is used for outputting a signal of the first voltage end to the third node under the control of the third control end in a compensation stage and a light-emitting stage; in a data writing stage, stopping outputting the signal of the first voltage end to the third node;
the writing sub-circuit is connected with a data signal end, a fourth control end and the first node; the write-in sub-circuit is used for outputting a signal of the data signal end to the first node under the control of the fourth control end in a data write-in stage; and stopping outputting the signal of the data signal terminal to the first node in a light-emitting stage;
the driving sub-circuit is connected with the first node, the second node and the third node, and the light-emitting device is connected with the second node and a second voltage end; the driving sub-circuit is used for conducting a third node and the second node in a compensation stage and carrying out voltage compensation on the second node according to the potentials of the third node and the first node; and in a light-emitting stage, conducting the third node and the second node to enable the light-emitting device to emit light according to the potential of the second node and the potential of the second voltage end.
2. The pixel circuit according to claim 1, wherein the driving sub-circuit comprises a driving transistor and a storage capacitor;
the grid electrode of the driving transistor is connected with the first node, the first pole of the driving transistor is connected with the third node, and the second pole of the driving transistor is connected with the second node;
the first pole of the storage capacitor is connected with the first node, and the second pole of the storage capacitor is connected with the second node.
3. The pixel circuit according to claim 1, wherein the first control sub-circuit comprises a first sub-control circuit and a second sub-control circuit;
the first sub-control circuit is connected with a first initial signal end, a first control end and a first node; the first sub-control circuit is used for outputting a signal of the first initial signal end to the first node under the control of the first control end in the initialization stage, and initializing the potential of the first node; in the compensation stage, under the control of the first control end, the signal of the first initial signal end is continuously output to the first node, and the potential of the first node is maintained;
the second sub-control circuit is connected with the second initial signal end, the second control end and the second node; the second sub-control circuit is configured to, in the initialization stage, output a signal of the second initial signal end to the second node under the control of the second control end, and initialize a potential of the second node.
4. The pixel circuit according to claim 3, wherein the first sub-control circuit comprises a first transistor, and the second sub-control circuit comprises a second transistor;
the grid electrode of the first transistor is connected with the first control end, the first pole of the first transistor is connected with the first initial signal end, and the second pole of the first transistor is connected with the first node;
and the grid electrode of the second transistor is connected with the second control end, the first pole of the second transistor is connected with the second initial signal end, and the second pole of the second transistor is connected with the second node.
5. The pixel circuit according to claim 1, wherein the second control sub-circuit comprises a third transistor;
the grid electrode of the third transistor is connected with the third control end, the first pole is connected with the first voltage end, and the second pole is connected with the third node.
6. The pixel circuit according to claim 1, wherein the write sub-circuit comprises a fourth transistor, a gate of the fourth transistor is connected to the fourth control terminal, a first pole of the fourth transistor is connected to the data signal terminal, and a second pole of the fourth transistor is connected to the first node.
7. The pixel circuit according to claim 1, further comprising a third control sub-circuit connecting the second node, a fifth control terminal, and a light emitting device; the signal used for controlling the fifth control end is turned on or off in a compensation stage; and in the light-emitting stage, under the control of the fifth control terminal, conducting the second node and the second voltage terminal to enable the light-emitting device to emit light according to signals of the second node and the second voltage terminal.
8. The pixel circuit according to claim 7, wherein the third control sub-circuit comprises a fifth transistor;
and the grid electrode of the fifth transistor is connected with a fifth control end, the first pole of the fifth transistor is connected with the second node, and the second pole of the fifth transistor is connected with the light-emitting device.
9. A display device comprising a plurality of sub-pixels, a sub-pixel comprising a pixel circuit as claimed in any one of claims 1 to 8.
10. The display device according to claim 9, wherein one data line is connected to each column of the sub-pixels;
the pixel array further comprises a plurality of multiplexing sub-circuits, each multiplexing sub-circuit is connected with a data signal input end and at least two data lines and used for writing data signals into the at least two data lines in the data writing phases of the sub-pixels connected with the at least two data lines under the condition that a row of sub-pixels are scanned, and the data writing phases of the sub-pixels connected with the at least two data lines are not overlapped.
11. The display device according to claim 10, wherein the multiplexing sub-circuit comprises at least two sixth transistors, each of the sixth transistors has a gate connected to a shunt control signal terminal, a first pole connected to a data signal input terminal, and a second pole connected to a plurality of columns of the data lines in a one-to-one correspondence.
12. The display device according to claim 10 or 11, wherein the plurality of sub-pixels comprises a plurality of sub-pixel groups distributed repeatedly, each sub-pixel group comprising at least three columns of sub-pixels of different colors;
the sub-pixels connected with the at least two data lines have the same light emitting color; or
The sub-pixels connected with the at least two data lines are at least two rows of sub-pixels which are distributed continuously.
13. A driving method of a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 8, the driving method comprising: one frame period includes an initialization stage, a compensation stage, a data writing stage, and a light emitting stage; wherein
The initialization phase comprises: under the control of a first control end, outputting a signal of a first initial signal end to a first node, and under the control of a second control end, outputting a signal of a second initial signal end to a second node so as to initialize the potentials of the first node and the second node;
the compensation phase comprises: under the control of a first control end, continuously outputting a signal of a first initial signal end to a first node, keeping the potential of the first node, and under the control of a third control end, outputting a signal of a first voltage end to a third node, conducting the third node and the second node through the driving sub-circuit, and performing voltage compensation on the second node according to the potentials of the third node and the first node;
the data writing phase comprises: stopping outputting the signal of the first voltage end to the third node, and outputting the signal of the data signal end to the first node under the control of the fourth control end;
the lighting phase comprises: and stopping outputting the signal of the data signal end to the first node, outputting the signal of the first voltage end to a third node under the control of the third control end, and conducting the third node and the second node through the driving sub-circuit to enable the light-emitting device to emit light according to the potential of the second node and the potential of the second voltage end.
14. The method for driving the pixel circuit according to claim 13, wherein the pixel circuit further comprises a third control sub-circuit which connects the second node, a fifth control terminal, and a light emitting device;
the driving method further includes: in the compensation stage, controlling the signal of the fifth control end to be switched on or off; and in the light-emitting stage, under the control of the fifth control terminal, conducting the second node and the second voltage terminal to enable the light-emitting device to emit light according to signals of the second node and the second voltage terminal.
15. A driving method of a display device, characterized by being applied to the display device according to any one of claims 9 to 12;
the driving method includes:
scanning each row of sub-pixels in sequence;
and under the condition that one row of sub-pixels are scanned, writing data signals into the at least two data lines in the data writing phases of the sub-pixels connected with the at least two data lines, wherein the data writing phases of the sub-pixels connected with the at least two data lines are not overlapped.
CN202010365978.3A 2020-04-30 2020-04-30 Pixel circuit and driving method thereof, display device and driving method thereof Pending CN111445850A (en)

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Application publication date: 20200724