CN111381254A - High-reliability navigation sensor single-particle-upset-resisting device based on FPGA - Google Patents
High-reliability navigation sensor single-particle-upset-resisting device based on FPGA Download PDFInfo
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- CN111381254A CN111381254A CN201911378052.1A CN201911378052A CN111381254A CN 111381254 A CN111381254 A CN 111381254A CN 201911378052 A CN201911378052 A CN 201911378052A CN 111381254 A CN111381254 A CN 111381254A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/13—Receivers
- G01S19/21—Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S19/00—Satellite radio beacon positioning systems; Determining position, velocity or attitude using signals transmitted by such systems
- G01S19/01—Satellite radio beacon positioning systems transmitting time-stamped messages, e.g. GPS [Global Positioning System], GLONASS [Global Orbiting Navigation Satellite System] or GALILEO
- G01S19/015—Arrangements for jamming, spoofing or other methods of denial of service of such systems
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/048—Monitoring; Safety
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24125—Watchdog, check at timed intervals
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- Radar, Positioning & Navigation (AREA)
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- Automation & Control Theory (AREA)
- Computer Networks & Wireless Communication (AREA)
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Abstract
The invention discloses a high-reliability navigation sensor single particle upset resistance device based on an FPGA (field programmable gate array), which comprises: the monitoring unit is used for monitoring the number of signal jumping edges; the input end of the first identification output unit is connected with the monitoring unit and used for outputting a first abnormal identification signal when the number of the signal jumping edges is smaller than a preset threshold value in a preset duration of a monitoring window; and the input end of the control unit is connected with the identification output unit and used for stopping feeding the watchdog chip according to the first abnormal identification signal.
Description
Technical Field
The invention particularly relates to a high-reliability navigation sensor single particle upset resistance device based on an FPGA.
Background
The navigation sensor is a plurality of attitude sensors used on the current satellite or star body surrounding device, and is a precision device for optical imaging and attitude determination. By driving the detector to image, the image processing comprises the processes of image filtering, non-uniform correction, edge extraction and the like. And calculating the attitude of the sensor through the extracted edge points. All the processes are realized in FPGA, and the mainstream FPGA chip of the navigation sensor is SARM type. However, the SRAM type FPGA is easy to generate single event upset in space, so that the product cannot work normally. Whether the product works normally is judged by detecting key signals in the program of the whole system in real time.
Disclosure of Invention
The invention aims to provide a high-reliability navigation sensor single-particle-upset-resisting device based on an FPGA (field programmable gate array), which can effectively counteract adverse effects caused by single-particle upset of the FPGA in the outer space.
In order to achieve the purpose, the invention is realized by the following technical scheme:
a high-reliability navigation sensor single event upset resistance logic circuit based on FPGA is characterized by comprising:
the monitoring unit is used for monitoring the number of signal jumping edges;
the input end of the first identification output unit is connected with the monitoring unit and used for outputting a first abnormal identification signal when the number of the signal jumping edges is smaller than a preset threshold value in a preset duration of a monitoring window;
and the input end of the control unit is connected with the identification output unit and used for stopping feeding the watchdog chip according to the first abnormal identification signal.
The monitoring unit is also used for monitoring whether the signal is constant within the preset duration of the monitoring window.
Further comprising:
the input end of the second identification output unit is connected with the monitoring unit, and a second abnormal identification signal is output when the signal changes within the preset duration of the monitoring window;
and the control unit stops feeding the watchdog chip according to the second abnormal identification signal.
And after the watchdog chip stops receiving the dog feeding signal, the FPGA is controlled to reset and restart.
The first identification output unit outputs a first normal identification signal when the number of the signal jumping edges is larger than or equal to a preset threshold value in a preset time length of the monitoring window, and the control unit continuously feeds the watchdog chip according to the first normal identification signal.
The second identification output unit outputs a second normal identification signal when the signal is kept unchanged within the preset time length of the monitoring window, and the control unit continuously feeds the watchdog chip according to the second normal identification signal.
Compared with the prior art, the invention has the following advantages:
the comprehensiveness of the product. All key signals of the system can be detected to judge whether the product works normally.
And (5) timing detection. The detection time window is set by setting the starting time and the ending time of the detection window, the rising or falling edge of the signal is counted to judge whether the set threshold value is reached or the signal is a constant value, the set threshold value or the signal is constant, and the timer is cleared at fixed time to achieve the purpose of implementing detection.
Effectiveness. For non-antifuse type FPGAs, a single event upset in space is inevitable. The FPGA is an important device of the navigation sensor, and the abnormal operation of the FPGA directly causes the abnormal operation of the navigation sensor. The single event upset prevention logic circuit designed by the patent can effectively resist adverse effects caused by single event upset of the FPGA. The single event upset prevention logic circuit is matched with a hardware watchdog circuit to control resetting and restarting of the navigation sensor, and reloads a program from the FLASH to achieve the purpose of refreshing the program and resist adverse effects caused by single event upset of the FPGA.
Drawings
FIG. 1 is a structural diagram of a single event upset resistant device of a high-reliability navigation sensor based on an FPGA.
FIG. 2 is a state diagram of the abnormal state detection circuit according to the present invention.
Detailed Description
The present invention will now be further described by way of the following detailed description of a preferred embodiment thereof, taken in conjunction with the accompanying drawings.
As shown in fig. 1, a high-reliability navigation sensor anti-single event upset logic circuit based on FPGA includes: the monitoring unit is used for monitoring the number of signal jumping edges; the input end of the first identification output unit is connected with the monitoring unit and used for outputting a first abnormal identification signal when the number of the signal jumping edges is smaller than a preset threshold value in a preset duration of a monitoring window; and the input end of the control unit is connected with the identification output unit and used for stopping feeding the watchdog chip according to the first abnormal identification signal.
The monitoring unit is also used for monitoring whether the signal is constant within the preset duration of the monitoring window.
In a specific embodiment, the apparatus further comprises: the input end of the second identification output unit is connected with the monitoring unit, and a second abnormal identification signal is output when the signal changes within the preset duration of the monitoring window; and the control unit stops feeding the watchdog chip according to the second abnormal identification signal.
And after the watchdog chip stops receiving the dog feeding signal, the FPGA is controlled to reset and restart. The first identification output unit outputs a first normal identification signal when the number of the signal jumping edges is larger than or equal to a preset threshold value in a preset time length of the monitoring window, and the control unit continuously feeds the watchdog chip according to the first normal identification signal.
The second identification output unit outputs a second normal identification signal when the signal is kept unchanged within the preset time length of the monitoring window, and the control unit continuously feeds the watchdog chip according to the second normal identification signal.
Specifically, the key signals to be detected in real time are selected, that is, if the signals are inverted, the product cannot normally work, and the key signals include control signals of a detector, frame synchronization signals, line synchronization signals, data effective signals and the like. Working waveforms of these key signals are clarified to prepare for setting a real-time monitoring period.
And distinguishing whether the signal to be measured is constant or is a signal which changes along with time.
And setting a real-time monitoring period, and setting an implementation detection period according to a product restart time threshold value and key signal characteristics set by hardware watchdog chip hardware.
After the product is electrified, the waiting time is set to be certain, so that the waveform change of the key signal is stable. For a signal which is unchanged all the time after being electrified, the signal is detected to be high or low all the time, and the signal is considered to work normally. For signals which change along with time, the detection period is designed to be 5 seconds, the detection time window is 2 seconds, and the detection state result lasts for 3 seconds. Detecting the times of the rising edge or the falling edge of the signal in a detection time window, and when the times of the rising edge or the falling edge of the signal are greater than a set required value, considering that the signal works normally; otherwise, the signal is considered to have single event upset; and clearing the edge counter after 5 seconds, and detecting for another period again.
In a detection period, the duration of the detection state result which is kept unchanged is 3 seconds longer than the shortest time for the watchdog chip set by the hardware to power off the product. The dog feeding signal of the watchdog is controlled by the detection state variable. When the product working state is A5, the navigation sensor is considered to work normally, a dog feeding signal is continuously generated, and the product is not reset and restarted; when the working state of the product is B5, if the navigation sensor is considered to be abnormal, namely single event upset happens, the generation of a dog feeding signal is stopped, the product is reset and restarted, an FPGA program is refreshed, and adverse effects caused by the single event upset are resisted.
As shown in fig. 2, optionally, the initial state of the device is an IDLE state, i.e., an IDLE state, in which the state of each counter and status register is zero. Then after the time counter counts for 5s, the state register jumps to the Wait-5 s state; the time counter counts for 5s to ensure that all signals work stably and prepare for subsequent signal state monitoring; and immediately jumping to the state Risedge _ Cnt state, namely the signal jumping edge monitoring counting state after the state register jumps to the Wait _5s state. The signals in the FPGA are two types: one is a constant signal, i.e. a signal which is normally high or low, and the other is a signal with a time-varying level; the duration of the Risedge _ Cnt state is 4s, and the number of the lower threshold limits of the set jump edges of the monitoring signal is 6. For a constant signal, if the signal is continuously unchanged in a monitoring window of 4s, the signal is considered to work normally, otherwise, the signal is considered to have abnormal single event upset work. Regarding signals with high and low levels along with time, when the number of the edge counters is smaller than the lower threshold 6 in a monitoring window of 4s, the signals are considered to have abnormal single event upset work. And 4s later, the state register jumps to a Status _ Monitor state, and outputs the state identifier of the monitoring of the judgment of the single event upset resistant logic circuit. When all monitored signals work normally, the output result of the single event upset resistant logic circuit is A5; when one monitoring signal works abnormally, the output result of the single event upset resisting logic circuit is B5;
the control unit controls the dog feeding signal by monitoring the state identification output by the single event upset resistant logic circuit in real time. When the output result of the logic circuit resisting the single event upset is A5, continuously feeding a dog signal to the hardware watchdog; and when the output result of the single event upset resistant logic circuit is B5, the FPGA stops feeding the hardware watchdog, the hardware watchdog circuit controls the FPGA to restart, and the source program is loaded from the PROM again to counteract the adverse effect caused by the single event upset of the FPGA.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (6)
1. The utility model provides a high reliable navigation sensor anti single particle upset device based on FPGA which characterized in that includes:
the monitoring unit is used for monitoring the number of signal jumping edges;
the input end of the first identification output unit is connected with the monitoring unit and used for outputting a first abnormal identification signal when the number of the signal jumping edges is smaller than a preset threshold value in a preset duration of a monitoring window;
and the input end of the control unit is connected with the identification output unit and used for stopping feeding the watchdog chip according to the first abnormal identification signal.
2. The FPGA-based highly reliable navigation sensor single event upset resistant device of claim 1, wherein the monitoring unit is further configured to monitor whether the signal is constant within a preset duration of the monitoring window.
3. The FPGA-based highly reliable navigation sensor single event upset resistant device of claim 2, further comprising:
the input end of the second identification output unit is connected with the monitoring unit, and a second abnormal identification signal is output when the signal changes within the preset duration of the monitoring window;
and the control unit stops feeding the watchdog chip according to the second abnormal identification signal.
4. The FPGA-based high-reliability navigation sensor single event upset resistant device as claimed in claim 1 or 3, wherein the watchdog chip controls the reset restart of the FPGA after stopping receiving the dog feeding signal.
5. The FPGA-based high-reliability navigation sensor single event upset resistant device as claimed in claim 1, wherein the first identification output unit outputs a first normal identification signal when the number of signal transition edges is greater than or equal to a preset threshold value in a preset duration of a monitoring window, and the control unit continuously feeds the watchdog chip according to the first normal identification signal.
6. The FPGA-based high-reliability navigation sensor single event upset resistant device as claimed in claim 3, wherein the second identification output unit outputs a second normal identification signal when the signal is kept unchanged within a preset duration of the monitoring window, and the control unit continuously feeds the watchdog chip according to the second normal identification signal.
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