CN110910815A

CN110910815A - Electronic device

Info

Publication number: CN110910815A
Application number: CN201910294345.5A
Authority: CN
Inventors: 陈联祥; 郭拱辰; 曾名骏
Original assignee: Innolux Corp
Current assignee: Innolux Corp
Priority date: 2018-09-14
Filing date: 2019-04-12
Publication date: 2020-03-24
Also published as: KR20200031995A

Abstract

An electronic device includes a pixel. The pixel receives a data signal. The electronic device further comprises a driving transistor, a light-emitting circuit and a reset circuit. The driving transistor has a first gate, a first source/drain and a second source/drain. The first source/drain receives a first operating voltage. The light emitting circuit is coupled with the driving transistor. The reset circuit is coupled to the first gate for setting the level of the first gate. During a reset period, the voltage of the first gate is equal to a first default voltage. During a writing period, the voltage of the first gate is equal to a first difference between the first operating voltage and a threshold voltage of the driving transistor. During a display period, the voltage of the first gate is equal to the sum of the first difference and a second difference. The second difference is a difference between a reference voltage and the data signal.

Description

Electronic device

Technical Field

The present invention relates to an electronic device, and more particularly, to an electronic device having a light emitting element.

Background

Electronic devices have become increasingly popular in recent years because of their advantages of being thin, lightweight, or low-radiation. Display devices in electronic apparatuses may be classified into self-luminous (emission) display devices and non-self-luminous (non-emission) display devices. Non-self-luminous display devices (such as liquid crystal displays) utilize a backlight source to achieve the display function. Therefore, the non-self-luminous display device is larger in volume than the self-luminous display device.

Disclosure of Invention

In order to solve the problem that the non-self-luminous display device is larger in volume than the self-luminous display device, the invention provides an electronic device.

The invention provides an electronic device which comprises a pixel. The pixel receives a data signal. The electronic device further comprises a driving transistor, a light-emitting circuit and a reset circuit. The driving transistor has a first gate, a first source/drain and a second source/drain. The first source/drain receives a first operating voltage. The light emitting circuit is coupled with the driving transistor. The reset circuit is coupled to the first gate for setting the level of the first gate. During a reset period, the voltage of the first gate is equal to a first default voltage. During a writing period, the voltage of the first gate is equal to a first difference between the first operating voltage and a threshold voltage of the driving transistor. During a display period, the voltage of the first gate is equal to the sum of the first difference and a second difference. The second difference is a difference between a reference voltage and the data signal.

In an embodiment of the invention, the electronic device further includes a lighting circuit coupled to the light emitting circuit.

In an embodiment of the present invention, the electronic device further includes: a compensation circuit coupled between the first gate and the second source/drain.

In an embodiment of the invention, the electronic device further includes a storage circuit coupled to the first gate.

In an embodiment of the present invention, the electronic device further includes: a data input circuit coupled to the storage circuit. During the write period, the data input circuit transmits the data signal to the storage circuit according to a scanning signal.

In an embodiment of the present invention, the storage circuit includes: a first capacitor and a second capacitor. The first capacitor has a first end and a second end, and the first end is coupled to the first gate. The second capacitor is coupled between the first gate and a node.

In an embodiment of the present invention, the electronic device further includes: a first setting circuit coupled to the node, wherein the first setting circuit sets the node equal to the reference voltage during the display period.

In an embodiment of the invention, the light emitting circuit includes a light emitting element, and the electronic device further includes: a second setting circuit coupled to an anode of the light emitting device. Wherein the second setting circuit sets the voltage of the anode to be equal to a second default voltage during the reset period.

In an embodiment of the invention, the light emitting circuit receives a second operating voltage, and the second default voltage is smaller than the second operating voltage.

In an embodiment of the present invention, the electronic device further includes: and the impedance circuit is coupled between the second setting circuit and the second default voltage.

Drawings

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below, wherein:

fig. 1 is a schematic view of an electronic device according to the present invention.

FIG. 2A is a block diagram of a pixel according to the present invention.

FIG. 2B is another block diagram of a pixel according to the present invention.

Fig. 3A is a circuit diagram of a pixel according to the present invention.

Fig. 3B is a control timing diagram of the pixel shown in fig. 3A.

Fig. 3C is a state diagram of the transistor shown in fig. 3A.

FIG. 4 is another circuit diagram of a pixel according to the present invention.

FIG. 5 is another circuit diagram of a pixel according to the present invention.

Description of the symbols:

100: a display device;

110: a scan driver;

120: a data driver;

PX₁₁～PX_qp200A, 200B, 300, 400, 500: a pixel;

S₁～S_psn: scanning a signal;

D₁～D_qand DT: a data signal;

210. 310: a drive transistor;

220. 320, and (3) respectively: a lighting circuit;

321: lighting the transistor;

230. 330: a light emitting circuit;

240. 340, and (3): a reset circuit;

341: a first reset transistor;

342: a second reset transistor;

250. 350: a compensation circuit;

351: a compensation transistor;

260: a storage circuit;

270. 370: a first setting circuit;

371: a first setting transistor;

280. 380: a data input circuit;

381: a data input transistor;

290. 390: a second setting circuit;

295. 395: an impedance circuit;

211. 311: a first gate electrode;

212. 312: a first source/drain electrode;

213. 313: a second source/drain electrode;

ARVDD: a first operating voltage;

ARVSS: a second operating voltage;

231. 331: a light emitting assembly;

c1: a first capacitor;

cst: a second capacitor;

RST: a reset signal;

EM: a lighting signal;

VREF: a reference voltage;

VRST 1: a first default voltage;

VRST 2: a second default voltage;

CN: a control signal;

n: a node;

I_D: a drive current;

t310: a reset period;

t320, T340: during the shutdown period;

t330: a write period;

t350: the display period.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of each component in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

Fig. 1 is a schematic view of an electronic device according to the present invention. The invention is not limited to the field of application of electronic devices, which may comprise display devices, sensing devices, antenna devices, other suitable electronic devices, or combinations thereof. In one possible embodiment, the display device 100 may be applied to a Personal Digital Assistant (PDA), a cellular phone, a digital camera, a television, a Global Positioning System (GPS), a car display, an aviation display, a digital photo frame (digital photo frame), a notebook computer, a desktop computer, an outdoor billboard, or a tiled display, but the invention is not limited thereto.

As shown in fig. 1, the display device 100 includes a scan driver 110, a data driver 120, and a plurality of pixels PX₁₁～PX_qp. The scan driver 110 provides a scan signal S₁～S_p. The data driver 120 provides a data signal D₁～D_q. Pixel PX₁₁～PX_qpEach of which receives a corresponding scan signal and a corresponding data signal. For example, the pixel PX₁₁Receiving a scanning signal S₁And a data signal D₁. In this example, the pixel PX₁₁According to the scanning signal S₁Receiving a data signal D₁And according to the data signal D₁The corresponding brightness is presented.

FIG. 2A is a block diagram of a pixel according to the present invention. Due to the pixel PX₁₁～PX_qpHaving the same or similar circuit configuration, FIG. 2A shows a block configuration of a single pixel. As shown in fig. 2A, the pixel 200A includes a driving transistor 210, a lighting circuit 220, a light emitting circuit 230, a reset circuit 240, a compensation circuit 250, and a storage circuit 260.

The driving transistor 210 has a first gate 211, a first source/drain 212 and a second source/drain 213. The first gate 211 is coupled to the reset circuit 240, the compensation circuit 250 and the storage circuit 260. The first source/drain 212 receives a first operating voltage ARVDD. The second source/drain 213 is coupled to the lighting circuit 220 and the compensation circuit 250. In the present embodiment, the driving transistor 210 can be a first P-type transistor. As shown in fig. 2A, the gate of the first P-type transistor can be coupled to the reset circuit 240, the compensation circuit 250, and the storage circuit 260. The source of the first P-type transistor may receive a first operating voltage ARVDD. The drain of the first P-type transistor can be coupled to the lighting circuit 220 and the compensation circuit 250. The present invention does not limit the kind of the driving transistor 210. In other embodiments, the driving transistor 210 is an N-type transistor.

The lighting circuit 220 is coupled to the driving transistor 210 for transmitting a driving current to the light emitting circuit 230. The present invention is not limited to the circuit architecture of the lighting circuit 220. Any circuit capable of transmitting a driving current may be used as the lighting circuit 220.

The light emitting circuit 230 is coupled to the lighting circuit 220 and receives a second operating voltage ARVSS. In the present embodiment, the light emitting circuit 230, the lighting circuit 220 and the driving transistor 210 are connected in series between the first operating voltage ARVDD and the second operating voltage ARVSS. In one possible embodiment, the light emitting circuit 230 may include a light emitting element 231. The present invention does not limit the kind of the light emitting element 231. In one possible embodiment, the light emitting element 231 may include a Light Emitting Diode (LED), an Organic Light Emitting Diode (OLED), a submillimeter light emitting diode (Mini LED), a micro LED (micro LED), a Quantum Dot (Quantum Dot), a Quantum Dot light emitting diode (QD-LED, QLED), other suitable light emitting elements, or a combination thereof, but the invention is not limited thereto. In other embodiments, the light emitting elements in the light emitting circuit 230 may have phosphor materials (phosphors) or fluorescent materials (phosphors).

The reset circuit 240 may be coupled to the first gate 211 for setting a voltage of the first gate 211. The present invention is not limited to the circuit architecture of the reset circuit 240. As long as a circuit capable of setting the voltage of the first gate 211 can be used as the reset circuit 240.

The compensation circuit 250 may be coupled between the first gate 211 and the second source/drain 213. In the present embodiment, the compensation circuit 250 is also used to set the level of the first gate 211. In a possible embodiment, when the compensation circuit 250 turns on a path between the first gate 211 and the second source/drain 213, the driving transistor 210 may be referred to as a diode-connected transistor (diode-connected transistor).

The storage circuit 260 may be coupled to the first gate 211. In the present embodiment, the driving transistor 210 can operate according to the charge stored in the storage circuit 260. During a reset period, the reset circuit 240 may set the voltage of the first gate 211 to be equal to a first default voltage. During a write period, the compensation circuit 250 turns on a path between the first gate 211 and the second source/drain 213. Therefore, the voltage of the first gate 211 may be equal to a first difference between the first operating voltage ARVDD and a threshold voltage of the driving transistor 210. During a display period, the driving transistor 210 generates a driving current according to the charge stored in the storage circuit 260. At this time, the voltage of the first gate 211 may be equal to a sum of the first difference and a second difference, wherein the second difference is a difference between a reference voltage and a data signal (as will be described in detail later). During the display period, the lighting circuit 220 transmits the driving current generated by the driving transistor 210 to the light emitting circuit 230.

FIG. 2B is another block diagram of a pixel according to the present invention. Fig. 2B is similar to fig. 2A, except that the pixel 200B further includes a first setting circuit 270. The first setting circuit 270 may be coupled to the storage circuit 260 for setting a voltage of a node inside the storage circuit 260. For example, during display, the first setting circuit 270 sets the node equal to a reference voltage. The present invention does not limit the circuit architecture of the first setting circuit 270. Any circuit that can set the voltage of the node inside the storage circuit 260 can be used as the first setting circuit 270.

In other embodiments, the pixel 200B may further include a data input circuit 280. The data input circuit 280 is coupled to the storage circuit 260. During the write period, the data input circuit 280 transmits a data signal to the storage circuit 260 according to a scan signal. The present invention is not limited to the circuit architecture of the data input circuit 280. Any circuit that can transmit a data signal to the storage circuit 260 according to a scan signal can be used as the data input circuit 280.

In another possible embodiment, the pixel 200B further includes a second setting circuit 290. The second setting circuit 290 can be coupled to the anode or the cathode of the light emitting element 231. For example, the second setting circuit 290 may be coupled to the anode of the light emitting element 231, and the cathode of the light emitting element 231 may receive other voltage or ground. During the reset period, the second setting circuit 290 can set the voltage of the anode or the cathode of the light emitting element 231 to be equal to a second default voltage. The present invention does not limit the circuit structure of the second setting circuit 290. Any circuit that can set the voltage of the anode or the cathode of the light emitting element 231 can be used as the second setting circuit 290.

In other embodiments, the pixel 200B may further include an impedance circuit 295. The impedance circuit 295 may be coupled to the second setting circuit 290. Before forming the light emitting device 231, a tester may enable other circuits within the pixel 200B to generate a driving current (i.e., a current for driving the light emitting device 231). When the driving current flows through the impedance circuit 295, the voltage across the impedance circuit 295 varies with the driving current. Therefore, the tester can know whether the driving current reaches a target value by measuring the voltage across the impedance circuit 295. If the driving current does not reach a target value, it indicates that the pixel 200B is abnormal. At this time, the tester may replace the pixel 200B with a spare pixel, or not dispose the light emitting device 231 in the pixel 200B.

Fig. 3A is a circuit diagram of a pixel according to the present invention. As shown in fig. 3A, the pixel 300 includes a driving transistor 310, an illumination circuit 320, a light emitting circuit 330, a reset circuit 340, a first setting circuit 370, a data input circuit 380, and a storage circuit (C1, Cst). In the present embodiment, the driving transistor 310 may be a first P-type transistor. The driving transistor 310 may include a first gate 311, a first source/drain 312, and a second source/drain 313. The present invention does not limit the kind of the driving transistor 310. In other embodiments, the driving transistor 310 can be an N-type transistor.

The lighting circuit 320 may include a lighting transistor 321. The lighting transistor 321 may be coupled between the driving transistor 310 and the light emitting circuit 330, and receive a lighting signal EM. During a display period, the lighting transistor 321 is turned on to transmit a driving current I_DTo the light emitting circuit 330. The invention is not limited to the kind of the lighting transistor 321. In the present embodiment, the lighting transistor 321 may be a P-type transistor. As shown in fig. 3A, the gate of the P-type transistor receives the lighting signal EM. The source of the P-type transistor is coupled to the driving transistor 310. The drain of the P-type transistor is coupled to the light emitting circuit 330. In other embodiments, the lighting transistor 321 may be an N-type transistor.

The lighting circuit 330 may include a lighting component 331. The light emitting element 331 is driven by the driving current I_DAnd emits light. In the present embodiment, the anode of the light emitting element 331 can be coupled to the lighting transistor 321. The cathode of the light emitting element 331 can receive the second operating voltage ARVSS. The second operating voltage ARVSS may be less than the first operating voltage ARVDD. In one embodiment, the second operating voltage ARVSS is a ground voltage or a negative voltage.

The reset circuit 340 includes a first reset transistor 341 and a second reset transistor 342, but is not limited thereto. In other embodiments, the second reset transistor 342 may be omitted. As shown in fig. 3A, the first reset transistor 341 has a second gate, a third source/drain, and a fourth source/drain. The second gate of the first reset transistor 341 may receive a reset signal RST. The third source/drain of the first reset transistor 341 receives the first default voltage VRST 1. The fourth source/drain of the first reset transistor 341 is coupled to the first gate 311. During a reset period, the first reset transistor 341 is turned on to transmit the first default voltage VRST1 to the first gate 311.

The second reset transistor 342 has a third gate, a fifth source/drain and a sixth source/drain. The third gate of the second reset transistor 342 may receive the reset signal RST. The fifth source/drain of the second reset transistor 342 receives a reference voltage VREF. The sixth source/drain of the second reset transistor 342 is coupled to the node N. During the reset period, the second reset transistor 342 is also turned on to transmit the reference voltage VREF to the node N.

The present invention is not limited to the types of the first reset transistor 341 and the second reset transistor 342. In one embodiment, the first reset transistor 341 and the second reset transistor 342 may be both N-type transistors or both P-type transistors. In other embodiments, the kind of the first reset transistor 341 may be different from that of the second reset transistor 342. For example, one of the first reset transistor 341 and the second reset transistor 342 is an N-type transistor, and the other of the first reset transistor 341 and the second reset transistor 342 is a P-type transistor. In this example, the gates of the first reset transistor 341 and the second reset transistor 342 may receive different reset signals, such as a first reset signal and a second reset signal, wherein the phases of the first reset signal and the second reset signal are opposite. In the present embodiment, the first reset transistor 341 can be a second P-type transistor. In addition, the second reset transistor 342 is a third P-type transistor.

The compensation circuit 350 includes a compensation transistor 351. The compensation transistor 351 may be coupled between the first gate 311 and the second source/drain 313, and receive a scan signal Sn. During a write, the compensation transistor 351 is turned on, causing the driving transistor 310 to act as a diode. The present invention does not limit the kind of the compensation transistor 351. In the present embodiment, the compensation transistor 351 can be a P-type transistor. The gate of the P-type transistor receives the scan signal Sn. The source of the P-type transistor is coupled to the first gate 311. The drain of the P-type transistor is coupled to the second source/drain 313. In other embodiments, the compensation transistor 351 can be an N-type transistor.

The storage circuit includes a first capacitor C1 and a second capacitor Cst. The first capacitor C1 is used to stabilize the voltage of the first gate 311. As shown in fig. 3A, a first terminal of the first capacitor C1 is coupled to the first gate 311. The second terminal of the first capacitor C1 is coupled to the first source/drain 312, but not limited thereto. In other embodiments, the second terminal of the first capacitor C1 may be coupled to a dc power source for receiving a fixed voltage (or a third default voltage). In one possible embodiment, the voltage provided by the dc power supply is different from the first operating voltage ARVDD. The second capacitor Cst is coupled between the first gate 311 and the node N. In one possible embodiment, the capacitance of the first capacitor C1 may be smaller than the capacitance of the second capacitor Cst.

The first setting circuit 370 includes a first setting transistor 371. The first setting transistor 371 has a fourth gate, a seventh source/drain and an eighth source/drain. The fourth gate of the first setting transistor 371 may receive the lighting signal EM. The seventh source/drain of the first setting transistor 371 receives a reference voltage VREF. The eighth source/drain of the first setting transistor 371 may be coupled to the node N. During a display period, the first setting transistor 371 is turned on for transmitting the reference voltage VREF to the node N. In this case, since the voltage at the node N is equal to the reference voltage VREF, the charge stored in the first capacitor C1 is maintained. The invention is not limited to the kind of the first setting transistor 371. In this embodiment, the first setting transistor 371 can be a P-type transistor. In other embodiments, the first setting transistor 371 can be an N-type transistor.

The data input circuit 380 includes a data write transistor 381. The data write transistor 381 is coupled to the node N and transmits a data signal DT to the node N according to the scan signal Sn. During a write period, the data write transistor 381 is turned on to transmit the data signal DT to the node N. The present invention does not limit the kind of the data writing transistor 381. In one embodiment, the data write transistor 381 may be a P-type transistor. In other embodiments, the data write transistor 381 can be an N-type transistor.

Fig. 3B is a control timing diagram of the pixel 300 shown in fig. 3A. Fig. 3C is a state diagram of the transistor shown in fig. 3A. As shown in fig. 3A, 3B and 3C, the reset signal RST is low during a reset period T310. Accordingly, the first reset transistor 341 and the second reset transistor 342 are turned on. At this time, the voltage of the node N is equal to the reference voltage VREF, and the voltage of the first gate 311 is equal to the first default voltage VRST 1. Since the voltage of the first gate 311 is equal to the first default voltage VRST1 and the voltage of the first source/drain is equal to the first operating voltage ARVDD, the driving transistor 310 is turned on. In addition, since the scan signal Sn and the lighting signal EM are at a high level, the data input transistor 381, the compensation transistor 351, the first setting transistor 371, and the lighting transistor 321 are not turned on.

In a writing period T330, the scan signal Sn is at a low level to turn on the driving transistor 310, the data input transistor 381 and the compensation transistor 351. Since the data input transistor 381 is turned on, the level of the node N is equal to the data signal DT. Furthermore, since the driving transistor 310 and the compensation transistor 351 are turned on, the voltage of the first gate 311 is equal to a first difference (i.e. ARVDD-V) between the first operating voltage ARVDD and the threshold voltage of the driving transistor 310_TH)。

In a display period T350, the lighting signal EM is low. Therefore, the first setting transistor 371 and the lighting transistor 321 are turned on. Since the first setting transistor 371 is turned on, the voltage of the node N is equal to the reference voltage VREF. At this time, due to the capacitive coupling effect, the voltage of the first gate 311 is equal to the sum of the first difference and a second difference, wherein the second difference is the difference between the reference voltage VREF and the data signal DT (i.e. VREF-DT). In other words, the voltage V of the first gate 311_GAs shown in formula (1):

V_G＝ARVDD-V_TH+(VREF-DT)……………………………(1)

wherein, V_THTo drive the threshold voltage of transistor 310, ARVDD-V_THVREF-DT is a second difference value.

During the display period T350, the driving transistor 310 generates the driving current I_DAs shown in formula (2):

I_D＝K(V_SG-V_TH)²……………………………………………(2)

wherein K is a Conduction parameter (Conduction parameter).

The gate and source voltages (i.e., the first gate 311 and the first source/drain) of the driving transistor 310 are substituted by formula (2), and simplified to obtain formula (3):

I_D＝K(DT-VREF)²………………………………(3)

as shown in the formula (3), the driving current I generated by the driving transistor 310_DIs not affected by the threshold voltage of the driving transistor 310. Therefore, when the threshold voltage of the driving transistor 310 is shifted, the driving current I is not affected_D. In addition, in the display period T350, the lighting transistor 321 is turned on, so that the lighting transistor 321 transmits the driving current I_DThe light emitting circuit 330 is used to illuminate the light emitting element 331.

In the present embodiment, an off period T320 is provided between the reset period T310 and the write period T330. In the off period T320, the reset signal RST and the scan signal Sn are both high, so that the data input transistor 381 and the second reset transistor 342 are prevented from being turned on simultaneously, thereby affecting the voltage of the node N. The present invention does not limit the duration of the off period T320. In other embodiments, the off period T320 may be omitted.

In addition, an off period T340 is provided between the writing period T330 and the display period T350. During the turn-off period T340, the lighting signal EM is at a high level to ensure that the voltage of the first gate 311 reaches a predetermined value. The present invention does not limit the duration of the writing period T330. In one possible embodiment, the off period T340 is longer than the off period T320.

FIG. 4 is another circuit diagram of a pixel according to the present invention. FIG. 4 is similar to FIG. 3A, except that the pixel 400 of FIG. 4 has a second setting circuit 390. The second setting circuit 390 includes a second setting transistor 391. During the reset period, the second setting transistor 391 provides a second default voltage VRST2 to the anode of the light emitting element 331 according to a control signal CN, for resetting the voltage of the anode of the light emitting element 331. In one possible embodiment, the second default voltage VRST2 is less than or equal to the second operating voltage ARVSS.

In other embodiments, the control signal CN is a scan signal (i.e. Sn-1) of a previous stage or a scan signal (i.e. Sn +1) of a next stage of the scan signal Sn. For example, in FIG. 1, it is assumed that the scan driver 110 sequentially enables the scan signals S₁～S_p. If the scan signal Sn is the scan signal S₂Then the control signal CN can be the scanning signal S₁Or scanning the signal S₃. In some embodiments, the control signal CN may be equal to the scan signal Sn. In addition, the reset signal RST may be a scan signal (i.e., Sn-1) of a previous stage. Taking FIG. 1 as an example, if the scan signal Sn is the scan signal S₂Then the reset signal RST can be the scan signal S₁。

The invention does not limit the kind of the second setting transistor 391. In this embodiment, the second setting transistor 391 may be a P-type transistor. In other embodiments, the second setting transistor 391 may be an N-type transistor.

FIG. 5 is another circuit diagram of a pixel according to the present invention. FIG. 5 is similar to FIG. 4, except that the pixel 500 of FIG. 5 further includes an impedance circuit 395. The impedance circuit 395 may be coupled to the second setting circuit 390 and receive the second default voltage VRST 2. In one possible embodiment, the second default voltage VRST2 is equal to the second operating voltage ARVSS. In other embodiments, the second default voltage VRST2 is less than the second operating voltage ARVSS.

In the present embodiment, when the light emitting element 331 is not disposed in the pixel 500, the driving transistor 310 generates the driving current I when all circuits in the pixel 500 are activated_DFlow-through impedance circuit395. The tester measures the voltage of the node TN to obtain the driving current I_DWhether a target value is reached. If the current I is driven_DFailure to reach the target value indicates that the pixel 500 is operating abnormally. At this point, the tester may attempt to repair the pixel 500 or replace the pixel 500 with another spare pixel. In one possible embodiment, when the pixel 500 fails to work properly, the tester does not set the light emitting element 331 in the pixel 500.

The present invention does not limit the kind of material of the semiconductor layer of the transistor. In one embodiment, the semiconductor layer of the transistor may comprise amorphous silicon (amorphous silicon), polysilicon (polysilicon), low-temperature polysilicon (LTPS), oxide semiconductor (oxide semiconductor), such as Indium Gallium Zinc Oxide (IGZO), other suitable materials, or combinations thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be interpreted as commonly understood by one of ordinary skill in the art to which this invention belongs. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being consistent with its meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition.

While the present invention has been described with respect to the preferred embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention, and it is intended that all matter contained in the above description or shown in the accompanying drawings shall be interpreted as illustrative and not in a limiting sense. Therefore, the protection scope of the present invention is defined by the claims.

Claims

1. An electronic device, comprising:

a pixel, receiving a data signal, and comprising:

a driving transistor having a first gate, a first source/drain and a second source/drain, the first source/drain receiving a first operating voltage;

a light emitting circuit coupled to the driving transistor; and

a reset circuit coupled to the first gate for setting the level of the first gate,

the voltage of the first gate is equal to a first default voltage during a reset period, is equal to a first difference between the first operating voltage and a threshold voltage of the driving transistor during a write period, and is equal to the sum of the first difference and a second difference between a reference voltage and the data signal during a display period.

2. The electronic device of claim 1, further comprising a lighting circuit coupled to the light-emitting circuit.

3. The electronic device of claim 1, further comprising:

a compensation circuit coupled between the first gate and the second source/drain.

4. The electronic device of claim 1, further comprising a storage circuit coupled to the first gate.

5. The electronic device of claim 4, further comprising:

a data input circuit coupled to the storage circuit,

during the write period, the data input circuit transmits the data signal to the storage circuit according to a scanning signal.

6. The electronic device of claim 4, wherein the storage circuit comprises:

a first capacitor having a first end and a second end, the first end being coupled to the first gate; and

and a second capacitor coupled between the first gate and a node.

7. The electronic device of claim 6, further comprising:

a first setting circuit coupled to the node, wherein the first setting circuit sets the node equal to the reference voltage during the display period.

8. The electronic device of claim 1, wherein the light-emitting circuit comprises a light-emitting element, the electronic device further comprising:

a second setting circuit coupled to an anode of the light emitting device,

wherein the second setting circuit sets the voltage of the anode to be equal to a second default voltage during the reset period.

9. The electronic device of claim 8, wherein the light emitting circuit receives a second operating voltage, and the second default voltage is less than the second operating voltage.

10. The electronic device of claim 8, further comprising:

and the impedance circuit is coupled between the second setting circuit and the second default voltage.