CN110752847A

CN110752847A - Digital-to-analog converter

Info

Publication number: CN110752847A
Application number: CN201810820578.XA
Authority: CN
Inventors: 刘菁
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2018-07-24
Filing date: 2018-07-24
Publication date: 2020-02-04
Also published as: WO2020020092A1

Abstract

Disclosed is a digital-to-analog converter including: a first resistor string including a plurality of first resistors connected between a reference voltage and a reference ground; a second resistor string including a plurality of second resistors connected between the first input terminal and the second input terminal; a first switching network for selecting at least one first resistor in the first resistor string according to a first significant bit of an input digital signal; a second switching network for selecting at least one second resistor in the second resistor string according to a second significant bit of the input digital signal, wherein the digital-to-analog converter further comprises a third switching network for providing a current path from the first switching network to the second resistor string. The voltage changes at two ends of the resistor in the second resistor string are consistent when the first resistor string is switched, and the matching performance is greatly improved, so that the output analog signal difference of adjacent codes cannot generate strong correlation with absolute codes, and the conversion precision of digital-to-analog conversion is influenced.

Description

Digital-to-analog converter

Technical Field

The present invention relates to the field of integrated circuit manufacturing, and more particularly to a digital-to-analog converter.

Background

With the rapid development of computer technology, multimedia technology and signal processing technology, advanced electronic systems are emerging, and digital to analog converters (DACs) are applied to both front and back ends of modern electronic systems.

Digital-to-analog converters are used to convert digital signals to analog signals, and resistive type digital-to-analog converters are preferred in integrated circuit designsIs a common one. As shown in fig. 1, a structure diagram of a resistor-type digital-to-analog converter is shown, and as shown in fig. 1, a conventional resistor-type digital-to-analog converter 100 connects resistors R1-R64 having the same resistance value in series with each other, connects between a reference voltage Vref and a reference ground, is connected at a connection node between the resistors by parallel switches S0-S64, and a plurality of switches S0-S64 are controlled by decoded digital signals, selectively outputting voltages at respective nodes between the resistors as analog voltages corresponding to the digital signals. For a digital-to-analog converter of a conventional structure, when the precision N is 10 bits or more, 2 bits are required^NThe circuit occupies a larger area due to the switch, and the stray capacitance of the switch can limit the speed of digital-to-analog conversion.

Disclosure of Invention

In view of the above, the present invention provides a digital-to-analog converter with higher efficiency and accuracy.

According to the present invention there is provided a digital to analogue converter comprising: a first resistor string including a plurality of first resistors connected between a reference voltage and a reference ground; a second resistor string including a plurality of second resistors connected between the first input terminal and the second input terminal; a first switching network for selecting at least one first resistor in the first resistor string according to a first significant bit of an input digital signal; a second switching network for selecting at least one second resistor in the second resistor string according to a second significant bit of the input digital signal, wherein the digital-to-analog converter further comprises a third switching network for providing a current path from the first switching network to the second resistor string.

Preferably, both ends of the first resistor include a first terminal, and both ends of the second resistor include a second terminal.

Preferably, adjacent first resistors in the first resistor string share the first terminal, and adjacent second resistors in the second resistor string share the second terminal.

Preferably, the first switch network includes a plurality of first switches, first path ends of the plurality of first switches are correspondingly connected to the first terminals, and second path ends are connected to output ends of the first switch network; the second switch network comprises a plurality of second switches, a first path end of each second switch is correspondingly connected with the corresponding second terminal, a second path end of each second switch is connected with an output end of the second switch network, and the output end of the second switch network is used for outputting an analog signal corresponding to the digital signal.

Preferably, the first switch network includes a first output terminal and a second output terminal, wherein the second pass terminals of the even-numbered first switches are connected to the first output terminal, and the second pass terminals of the odd-numbered first switches are connected to the second output terminal.

Preferably, the first switch network includes a first output terminal and a second output terminal, wherein the second pass terminals of the odd-numbered first switches are connected to the first output terminal, and the second pass terminals of the even-numbered first switches are connected to the second output terminal.

Preferably, the third switch network includes a first switch circuit and a second switch circuit, and the first switch circuit and the second switch circuit both include a third switch and a fourth switch, where a first pass end of the third switch in the first switch circuit is connected to the first output end, a second pass end is connected to the first input end, a first pass end of the fourth switch is connected to the first output end, a second pass end is connected to the second input end, a first pass end of the third switch in the second switch circuit is connected to the second output end, a second pass end is connected to the second input end, a first pass end of the fourth switch is connected to the second output end, and a second pass end is connected to the first input end.

Preferably, the digital-to-analog converter further comprises: a first decoding circuit, configured to obtain a first control signal according to the first valid bit of the digital signal, where the first control signal is used to control on/off states of the plurality of first switches; and the second decoding circuit is used for obtaining a second control signal according to the second effective bit of the digital signal, and the second control signal is used for controlling the on/off states of the plurality of second switches.

Preferably, the first control signal and the second control signal are independent of each other.

Preferably, the first significant bit is a most significant bit and the second significant bit is a least significant bit.

In summary, the digital-to-analog converter of the present invention includes a third switching network, configured to couple two ends of a selected resistor in the first resistor string to the first input end and the second input end of the second resistor string during the operation of the digital-to-analog converter, and when the resistor in the first resistor string is switched, the first input end and the second input end of the second resistor string are simultaneously switched. Therefore, when the resistance on the first resistor string is switched, the first input end and the second input end of the second resistor string are boosted to the ground by the same voltage. Therefore, the voltage changes at the two ends of the resistor in the second resistor string are consistent when the first resistor string is switched every time, the matching performance is greatly improved, and the conversion precision of digital-to-analog conversion cannot be influenced by the difference of output analog signals caused by different codes.

Meanwhile, in the process of switching the resistor of the first resistor string, the direction of the current in the second resistor string is always fixed and cannot be changed along with the switching of the resistor in the first resistor string, so that the logic switching of the second switch network and the switching logic of the first switch network are mutually independent, and finally, the first control signal and the second control signal are mutually independent, so that the first decoding circuit and the second decoding circuit are mutually independent, the decoding complexity is greatly reduced, the working efficiency is improved, and the power consumption is reduced.

Meanwhile, the third switch and the fourth switch in the third switch network are switched in sequence only along with the selection sequence of the resistors of the first resistor string, so that the complexity is not high. Therefore, the digital-to-analog converter of the invention has higher conversion efficiency and smaller area under high bit.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a conventional resistive digital-to-analog converter.

Fig. 2 shows a schematic diagram of a typical 4-bit digital-to-analog converter composed of a master resistor string and a slave resistor string.

Fig. 3 shows a schematic structure of a conventional digital-to-analog converter when an input digital signal is 0011.

Fig. 4 shows a schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention.

Fig. 5 shows a schematic diagram of the relationship between the bits of the digital signal I4I3I2I1 in fig. 4 and the closed/open states of the switches SM1-SM5, SHI and SH2 and SL1-SL 4.

Fig. 6 shows a schematic structural diagram of the digital-to-analog converter of the first embodiment of the present invention when the input digital signal is 0000.

Fig. 7 shows a schematic structural diagram of the digital-to-analog converter according to the first embodiment of the present invention when the input digital signal is 0100.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Fig. 2 shows a typical 4-bit dac 200 comprising a master resistor string and a slave resistor string, which includes a first resistor string 210, a second resistor string 230, a first switching network 220, a second switching network 240, and a decoding module 260.

The decoding module 260 is configured to obtain M control signals according to the received digital signal, where the M control signals are divided into a first control signal and a second control signal. For example, in the embodiment, the decoding module 260 obtains the first control signals C0-C4 and the second control signals D0-D3 according to the four-bit digital signal I4I3I2I 1. Wherein I4 and I3 represent the Most Significant Bits (MSBs), and the first control signals C0-C4 are, for example, higher-order control signals; i1 and I2 represent the Least Significant Bits (LSBs), and the second control signals D0-D3 are, for example, low-order Bit control signals.

In particular, the decoding module 260 includes a first decoding circuit 261 and a second decoding circuit 262, the first decoding circuit 261 for generating the first control signals C0-C4 from the two most significant bits I4 and I3 of the four-bit digital signals I4, I3, I2, I1. In the present embodiment, the first decoding circuit 461 is implemented using, for example, a first decoder, and performs decoding by using a gray code.

The second decoding circuit 262 is used for generating second control signals D0-D3 according to I3, I2 and I1 in four-bit digital signals I4, I3, I2 and I1. The second decoding circuit 262 includes a second decoder 263 and a selection circuit 264.

The second decoder 263 receives the two least significant bits I2 and I1 and generates binary signals at output terminals a0, a1, a2, and A3 according to I2 and I1. The selection circuit 264 includes a first input terminal a connected to the output terminals a0, a1, a2, and A3, and a second input terminal B connected to the output terminals a0, a1, a2, and A3 through a plurality of inverters 51, the output terminals a0, a1, a2, and A3 being correspondingly connected to the input terminals of the plurality of inverters 51, and the output terminal of the inverter 51 being connected to the second input terminal B of the selection circuit 264. The selection circuit 264 is, for example, a multiplexer for selectively coupling one of the first input terminal a or the second input terminal B to the output terminal of the selection circuit 264 according to the bit I3. More specifically, when the binary signal of the bit I3 is logic 0, the selection circuit 264 couples the output terminals a0, a1, a2, and A3 to the output terminals, respectively, as shown by the solid line 52 in fig. 2, and the second decoder 263 generates the binary signals at the output terminals a0, a1, a2, and A3 to output directly as the second control signals D0-D3. When the binary signal of the bit I3 is logic 1, the output terminals a0, a1, a2, and A3 are connected to the output terminal of the selection circuit 264 after passing through the inverter 51, respectively, as shown by the dotted line 54 in fig. 2, and the inverted signals of the binary signals generated at the output terminals a0, a1, a2, and A3 by the second decoder 263 are output as the second control signals D0-D3.

The first resistor string 210 is formed by serially connecting a plurality of resistors Ra4-Ra1 with equal resistance, and a plurality of resistors Ra4-Ra1 are connected between the reference voltage Vref and the reference ground. The second resistor string 230 is composed of a plurality of resistors Rb3-Rb1 which are equal in resistance and connected in series. The first switching network 220 includes a plurality of switches SM0-SM4 and the second switching network includes a plurality of switches SL0-SL 3. The first switch network 220 is controlled by the first control signals C0-C4 generated by the first decoding circuit 261, and the second switch network 240 is controlled by the second control signals D0-D3 generated by the second decoding circuit. Assuming that the reference voltage Vref is equal to 1V, table 1 shows the relationship between the output result of the DAC and the first and

second switching networks

220 and 240 in an ideal case.

TABLE 1

Fig. 3 shows a schematic structure of a conventional digital-to-analog converter when the digital signal is 0011. As shown in fig. 3, when the input is 0011, the switches SM1, SM0 and SL3 are closed, and assuming that the resistances of the resistors Ra4-Ra1 on the first resistor string are all R1 and the resistances of the resistors Rb3-Rb1 on the second resistor string are all R2, the total resistor connected into the circuit from the reference voltage Vref can be obtained

The voltage generated across resistor Ra1 is

In an ideal 4-bit digital-to-analog converter: R1-R2, the voltage Va 1-3/15 Vref on Ra1 can be obtained according to the above formula, and there are resistors Rb1-Rb3 connected in parallel to Ra1, i.e. 3 LSBs (Least significant bit), so we can obtain that one LSB of the 4-bit dac is 1/15 Vref. Of course, this is only an ideal situation, and in the actual circuit design of the resistor type digital-to-analog converter, the magnitudes of the resistances of the main resistor string and the second resistor string are often unequal.

The prior art digital-to-analog converters suffer from the following disadvantages: 1. in order to eliminate the interference of the closing current on the second resistor string 230 to the first resistor string 210, which causes an error for each LSB, the conventional digital-to-analog converter inserts a voltage buffer between the main and second resistor strings. However, the error of the voltage buffer itself increases the error of the output voltage, and the voltage buffer consumes additional power consumption and chip area. 2. As can be seen from table 1, when a different resistance is selected in the first resistor string, the logic of the second switching network of the second resistor string is different, for example: the switch SM0 and the switch SM1 are closed, namely when the resistor Ra1 is selected in the first resistor string, corresponding to the DAC output voltage of 0-3/15V, the closed switches of the second switch network are SL0-SL3 in sequence; and when switch SM1 and switch SM2 are closed, i.e. resistor Ra2 is selected in the first resistor string, the switches closed by the second switch network are SL3-SL0 in sequence, corresponding to DAC output voltages 4/15V-7/15V, as shown in table 1. Therefore, the decoding logic of the second switch network in the existing digital-to-analog converter changes according to the resistance selected by the first resistor string, the complexity of digital decoding of the digital-to-analog converter is increased, and the decoding workload is increased. 3. The change in voltage of each resistor in the second resistor string is related to the selected resistor in the first resistor string. For example: when the first resistor string is switched to the resistor Ra2 from the resistor Ra1, the top voltage of the resistor Rb3 of the second resistor string is unchanged, but the bottom voltage of the resistor Rb1 is increased; when the first resistor string is switched from the resistor Ra2 to the resistor Ra3, the top voltage of the resistor Rb3 of the second resistor string 230 rises, but the bottom voltage of the resistor Rb1 does not change. Under the same 1LSB change, due to the difference of the selected resistors in the first resistor string 210, the voltage changes at the head end and the tail end of the second resistor string 230 change, so that the output of the digital-to-analog converter may change differently under different codes, thereby affecting the output voltage value and the conversion accuracy of the digital-to-analog conversion.

Fig. 4 is a schematic structural diagram of a digital-to-analog converter 300 according to an embodiment of the present invention. The digital-to-analog converter 300 is used to convert the digital signal of N bits into an analog signal. The digital-to-analog converter 300 may be implemented by an integrated circuit as a stand-alone module or in combination with other modules.

The periphery of the digital-to-analog converter 300 comprises a first reference input 16, a second reference input 17 and an analog signal output 18. The first reference input terminal 16 is for receiving a reference voltage Vref and the second reference input terminal 17 is for receiving an analog ground signal. The reference voltage Vref enables the digital-to-analog converter 300 to produce an analog output according to a reference frame.

As shown in fig. 4, the digital-to-analog converter 300 includes a first resistor string 310, a first switch network 320, a second resistor string 340, a second switch network 350, and a decoding module 360. Wherein the first resistor string 310 includes 2 connected in series^N/2A second resistor string 340 comprising series-connected (2)^N/2-1) resistors, N being an even number greater than 0. In the present embodiment, the digital-to-analog converter 300 converts a 4-bit digital signal as an example, so the first resistor string 310 includes 4 resistors connected in series, and the second resistor string includes 3 resistors connected in series.

The decoding module 360 is configured to obtain M control signals according to the received digital signal, where the M control signals are divided into a first control signal and a second control signal. For example, in the present embodiment, the decode module 360 derives the first control signals C0-C4 and the second control signals D0-D3 from the four-bit numbers I4, I3, I2, and I1. Wherein I4 and I3 represent the Most Significant Bits (MSBs), and the first control signals C0-C4 are, for example, higher-order control signals; i1 and I2 represent the Least Significant Bits (LSBs), and the second control signals D0-D3 are, for example, low-order Bit control signals.

Specifically, the decode module 360 includes a first decode circuit 361 and a second decode circuit 362, the first decode circuit 361 for generating a first control signal C0-C4 from two most significant bits I4 and I3 of the four-bit digital signals I4, I3, I2, I1. In the present embodiment, the first decoding circuit 361 is implemented using, for example, a decoder that performs decoding by using a gray code.

The second decoding circuit 362 is used for generating second control signals D0-D3 according to two least significant bits I2 and I1 in four-bit digital signals I4, I3, I2 and I1. The second decoding circuit 362 is implemented using, for example, a decoder, and performs decoding by using a gray code.

The first resistor string 310 includes resistors Ra4-Ra1 connected in series between a reference voltage Vref and ground. The resistors Ra1-Ra4 are equal in resistance. It is noted that the two ends of the resistors Ra1, Ra2, Ra3 and Ra4 respectively have connection terminals, such as: the resistor Ra1 has a terminal T1 and a terminal T2 at both ends thereof, the resistor Ra2 has a terminal T2 and a terminal T3, the resistor Ra3 has a terminal T3 and a terminal T4, and the resistor Ra4 has a terminal T4 and a terminal T5, as shown in fig. 4. Resistors Ra1-Ra4 in the first resistor string 310 generate voltages at terminals T1-T5 in response to current fed by the reference voltage Vref.

The second resistor string 340 includes resistors Rb1, Rb2 and Rb3 connected in series between the first input terminal 26 and the second input terminal 28 of the second resistor string 340, and the resistances of the resistors Rb1, Rb2 and Rb3 are substantially equal. Likewise, the two ends of the resistors Rb1, Rb2, and Rb3 have connection terminals, respectively, such as: resistor Rb1 has terminals Q1 and Q2, resistor Rb2 has terminals Q2 and Q3, and resistor Rb3 has terminals Q3 and Q4, respectively, as shown in fig. 4. The terminal Q3 is connected to the first input 26 of the second resistor string 340 and the terminal Q0 is connected to the second input 28 of the second resistor string 340.

The first switching network 320 includes (2)^N/2+1) switches, N being an even number greater than 0, which are connected to the plurality of connection terminals in the first resistor string 310 correspondingly. For example, in the present embodiment, the first switch network 320 includes switches SM1-SM5, as shown in fig. 4, the first path terminals of the switches SM1, SM2, SM3, SM4, and SM5 are connected to terminals T1, T2, T3, T4, and T5, respectively. The second pass terminals of the even-numbered switches SM2 and SM4 are connected to the first output terminal 36 of the first switching network 320; the second pass terminals of the odd-numbered switches SM1, SM3, and SM5 are connected to the second output terminal 38 of the first switching network 320. Of course, in other embodiments of the present invention, the second pass terminals of the odd-numbered switches SM2 and SM4 are connected to the first output terminal 36 of the first switch network 320; the second pass terminals of the even-numbered switches SM1, SM3, and SM5 are connected to the second output terminal 38 of the first switching network 320. The invention is not so limited and may be selected by those skilled in the art depending on the particular circumstances.

Further, the closed and open states of the switches SM1, SM2, SM3, SM4, and SM5 are controlled by the first control signals C0-C4, respectively.

The second switching network 350 includes 2^N/2And a plurality of switches, N being an even number greater than 0, which are correspondingly connected to the plurality of connection terminals in the second resistor string 340. For example, as shown in fig. 4, the second switching network 350 includes switches SL1, SL2, SL3, and SL 4. The first path terminals of the switches SL1, SL2, SL3, SL4 are connected to terminals Q1, Q2, Q3, and Q4, respectively. The second path terminals of the switches SL1, SL2, SL3, SL4 are connected to the analog signal output terminal 18. The closed and open states of the switches SL1, SL2, SL3, SL4 are controlled by the second control signals D0-D3.

The digital-to-analog converter 300 further includes a third switching network 330, the third switching network 330 being used to provide a current path from the first switching network 320 to the second resistor string 340. The third switching network 330 includes a first switching circuit and a second switching circuit, both of which include switches SH1 and SH 2. A first path terminal of the first switch circuit is connected to the first output terminal 36 of the first switch network 320, and a second path terminal of the first switch circuit is connected to the first input terminal 26 and the second input terminal 28 of the second resistor string 340. A first path terminal of the second switching circuit is connected to the second output terminal 38 of the first switching network 320, and a second path terminal of the second switching circuit is connected to the first input terminal 26 and the second input terminal 28 of the second resistor string 340. Specifically, the first path terminals of the switches SH1 and SH2 of the first switch circuit are connected to the first output terminal 36 of the first switch network 320, the second path terminal of the switch SH1 is connected to the first input terminal 26 of the second resistor string 340, and the second path terminal of the switch SH2 is connected to the second input terminal 28 of the second resistor string 340. The first path terminals of the switches SH1 and SH2 of the second switch circuit are connected to the second output terminal 38 of the first switch network 320, the second path terminal of the switch SH1 is connected to the second input terminal 28 of the second resistor string 340, and the second path terminal of the switch SH2 is connected to the first input terminal of the second resistor string 340.

The first switching network 320 is configured to select one of the resistors Ra1-Ra4 of the first resistor string 310 according to the most significant bits I4 and I3 of the digital signal, and the third switching network 330 is configured to couple two ends of the selected resistor to the first input terminal 26 and the second input terminal 28 of the second resistor string 340. The resistors Rb1-Rb4 in the second resistor string 340 generate voltages at the terminals Q1-Q4 in response to current flowing between the first resistor string 310 and the second resistor string 340 through the first switching network 320 and the third switching network 330. The second switching network 350 is used to select one of the resistances Rb1-Rb3 of the second resistor string 340 and to couple the voltage developed at its terminals to the analog signal output terminal 18 of the digital-to-analog converter 300.

Fig. 5 shows the relationship between the bits of the four-bit digital signal I4I3I2I1 and the closed/open states of the switches SM1-SM5, SH1 and SH2 and SL1-SL 4.

In actual operation, as shown in fig. 5, when the selected resistor in the first resistor string 310 is an odd number of resistors, the switch SH1 in the third switch network 330 is closed; when the selected resistance in the first resistor string 310 is the even number of resistances, the switch SH2 in the third switch network 330 is closed. Based on this, the switching sequence of the second switching network 350 always follows the bit of the digital signal I4I3I2I1 from small to large, being switched in sequence by the switches SL1-SL 4. Therefore, the logic switching of the second switch network 350 and the switching logic of the first switch network 320 are independent from each other, and finally the first control signal and the second control signal are independent from each other, so that the decoding complexity is greatly reduced, the working efficiency is improved, and the power consumption is reduced.

In addition, as a first example, when the input digital signal is 0000, the switch SM1 and the switch SM2 are closed in the first switching network 320, the switch SH1 is closed in the third switching network 330, and the switch SL1 is closed in the second switching network 350. The terminal T2 of the resistor Ra1 is coupled to the first input terminal 26 of the second resistor string 340 through the switch SM2 and the switch SH1 of the first switching circuit in the third switching network 330, as indicated by the dashed line 61 in fig. 6. The terminal T1 of the resistor Ra1 is coupled to the second input 28 of the second resistor string 340 through the switch SM1 and the switch SH1 of the second switch circuit in the third switch network 330, as indicated by the dashed line 62 in fig. 6.

When the input is 0100, switches SM2 and SM3 are closed in the first switching network 320, switch SH2 is closed in the third switching network 330, and switch SL1 is closed in the second switching network 350. The terminal T3 of the resistor Ra2 is coupled to the first input 26 of the second resistor string 340 through the switch SM3 and the switch SH2 of the second switch circuit in the third switch network 330, as indicated by the dashed line 71 in fig. 7. The terminal T2 of the resistor Ra2 is coupled to the second input 28 of the second resistor string 340 through the switch SM2 and the switch SH2 of the first switching circuit in the third switching network 330, as indicated by the dashed line 72 in fig. 7.

According to the two specific examples, it can be seen that, in the embodiment of the present invention, when the resistance of the first resistor string 310 is switched, the first input terminal 26 and the second input terminal 28 of the second resistor string 340 are switched simultaneously. Thus, when the resistance on the first resistor string 310 is switched, the first input terminal 26 and the second input terminal 28 of the second resistor string 340 are raised to the same voltage with respect to ground. For example: when the first resistor string 310 switches from Ra1 to resistor Ra2, the voltage to ground across each resistor on the second resistor string 340 rises to 1/4 Vref; when the first resistor string 310 is switched from resistor Ra2 to resistor Ra3, the voltage raised to ground across each resistor on the second resistor string 340 is also 1/4 Vref. Therefore, the voltages at two ends of the resistor in the second resistor string 340 change uniformly each time the first resistor string 310 is switched, so that the conversion accuracy of digital-to-analog conversion is not affected by the difference of the output analog signals caused by the difference of the codes.

The "resistance" mentioned in the above embodiments may be a single physical resistor or a resistance element, or may be a combination of a plurality of physical resistors or resistance elements. In other words, the resistance type digital-to-analog converter shown in the present invention is applicable to various types of impedance elements, each impedance element having an impedance corresponding to a required resistance. Thus, reference herein to "resistance" is further to any number of different types of resistive elements according to circuit layout, such as precision thin film resistors formed of SiCr or other material, or in the case of integrated circuits, polysilicon (doped p-or n-). It will also be appreciated that a "resistor" as described herein may include any circuit element that can generate a voltage across its terminals that is proportional to the current passing through it.

In the above embodiments, the invention has been described in detail by taking a 4-bit digital-to-analog converter as an example, but as known to those skilled in the art, the digital-to-analog converter disclosed in the present invention is also applicable to converting digital signals of other bits, and the present invention is not limited thereto.

Meanwhile, the switches SH1 and SH2 in the third switch network are switched sequentially only along with the selection sequence of the resistors of the first resistor string, so that the complexity is not high. Therefore, the digital-to-analog converter of the invention has higher conversion efficiency and smaller area under high bit.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A digital-to-analog converter comprising:

a first resistor string including a plurality of first resistors connected between a reference voltage and a reference ground;

a second resistor string including a plurality of second resistors connected between the first input terminal and the second input terminal;

a first switching network for selecting at least one first resistor in the first resistor string according to a first significant bit of an input digital signal;

a second switching network for selecting at least one second resistor in the second resistor string according to a second significant bit of the input digital signal,

wherein the digital-to-analog converter further comprises a third switching network for providing a current path from the first switching network to the second resistor string.

2. The digital-to-analog converter of claim 1, wherein the two ends of the first resistor comprise first terminals and the two ends of the second resistor comprise second terminals.

3. The digital to analog converter of claim 2, wherein adjacent ones of said first resistors in said first resistor string share said first terminal and adjacent ones of said second resistors in said second resistor string share said second terminal.

4. The digital-to-analog converter according to claim 2, wherein the first switch network comprises a plurality of first switches, first path terminals of the plurality of first switches are correspondingly connected with the first terminals, and second path terminals of the plurality of first switches are connected with output terminals of the first switch network;

the second switch network comprises a plurality of second switches, a first path end of each second switch is correspondingly connected with the corresponding second terminal, a second path end of each second switch is connected with an output end of the second switch network, and the output end of the second switch network is used for outputting an analog signal corresponding to the digital signal.

5. A digital to analog converter according to claim 4, wherein the first switching network comprises a first output and a second output,

the second path ends of the even-numbered first switches are connected with the first output end, and the second path ends of the odd-numbered first switches are connected with the second output end.

6. A digital to analog converter according to claim 4, wherein the first switching network comprises a first output and a second output,

the second path ends of the odd-numbered first switches are connected with the first output end, and the second path ends of the even-numbered first switches are connected with the second output end.

7. A digital to analogue converter according to claim 5 or 6, wherein the third switching network comprises a first switching circuit and a second switching circuit, both comprising a third switch and a fourth switch,

wherein a first pass end of the third switch in the first switch circuit is connected to the first output terminal, a second pass end is connected to the first input terminal, a first pass end of the fourth switch is connected to the first output terminal, and a second pass end is connected to the second input terminal,

and in the second switch circuit, a first pass end of the third switch is connected with the second output end, a second pass end is connected with the second input end, a first pass end of the fourth switch is connected with the second output end, and a second pass end is connected with the first input end.

8. The digital-to-analog converter of claim 4, further comprising:

a first decoding circuit, configured to obtain a first control signal according to the first valid bit of the digital signal, where the first control signal is used to control on/off states of the plurality of first switches;

and the second decoding circuit is used for obtaining a second control signal according to the second effective bit of the digital signal, and the second control signal is used for controlling the on/off states of the plurality of second switches.

9. The digital to analog converter of claim 7, wherein the first control signal and the second control signal are independent of each other.

10. The digital to analog converter of claim 1, wherein the first significant bit is a most significant bit and the second significant bit is a least significant bit.