CN110718612B - Light emitting diode epitaxial wafer and manufacturing method thereof - Google Patents
Light emitting diode epitaxial wafer and manufacturing method thereof Download PDFInfo
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- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
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- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
- H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials
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Abstract
The invention discloses a light-emitting diode epitaxial wafer and a manufacturing method thereof, and belongs to the technical field of semiconductors. Each quantum well layer of a multi-quantum well layer of the light-emitting diode epitaxial wafer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, wherein the In/Ga ratio of the second quantum well sub-layer is larger than or equal to that of the first quantum well sub-layer and that of the third quantum well sub-layer; si is doped in the first quantum well sublayer; each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked; the Si/Ga ratio of the second quantum barrier layer is larger than or equal to the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer. The light-emitting diode epitaxial wafer can improve the energy band inclination phenomenon in a multi-quantum well layer, increase the overlapping degree of wave functions of electrons and holes on spatial distribution and improve the internal quantum efficiency of an LED.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a light-emitting diode epitaxial wafer and a manufacturing method thereof.
Background
GaN (gallium nitride) is one of materials for manufacturing LED (Light Emitting Diode) epitaxial wafers, and is an extremely stable compound, a hard high-melting-point material, and a direct transition wide-bandgap semiconductor material, and has good physical and chemical properties and a high electron saturation rate. The material has the characteristics of good thermal conductivity, large broadband forbidden degree, small dielectric constant and the like, and strong irradiation resistance, and can be used for preparing high-power devices with good stability, long service life, corrosion resistance and high temperature resistance.
Generally, GaN-based LEDs are epitaxially grown on a sapphire substrate. The traditional GaN-based LED epitaxial structure generally adopts an InGaN/GaN superlattice structure to act as a multi-quantum well layer. However, a large lattice mismatch exists between the InGaN layer and the GaN layer, resulting in a large compressive stress between the InGaN layer and the GaN layer. The piezoelectric polarization electric field is generated by the compressive stress, so that the overlapping of electron and hole wave functions is reduced, the energy band of the multiple quantum well layer is inclined, the internal quantum efficiency is reduced, and the light emitting efficiency of the LED is influenced.
Disclosure of Invention
The embodiment of the invention provides a light emitting diode epitaxial wafer and a manufacturing method thereof, which can improve the energy band inclination phenomenon in a multi-quantum well layer, increase the overlapping degree of wave functions of electrons and holes on spatial distribution and improve the internal quantum efficiency of an LED. The technical scheme is as follows:
in one aspect, a light emitting diode epitaxial wafer is provided, the light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electron blocking layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the multi-quantum well layer comprises a quantum well layer and a quantum barrier layer which are alternately grown,
each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are all InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than or equal to that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 1017cm-3～3*1017cm-3；
Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3(ii) a The Si/Ga ratio of the second quantum barrier layer is larger than or equal to the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer.
Further, the thickness ratio of the first quantum well sublayer to the second quantum well sublayer to the third quantum well sublayer is 1: m: m is more than or equal to 1 and 4 and less than or equal to 6, and m is a positive integer.
Further, the thickness ratio of the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer is 1: n: n is more than or equal to 1 and 4 and less than or equal to 6, and n is a positive integer.
Further, the Si/Ga ratio of the first quantum barrier layer gradually increases with the increase of the thickness, the Si/Ga ratio of the second quantum barrier layer is constant, and the Si/Ga ratio of the third quantum barrier layer gradually decreases with the increase of the thickness.
Further, the Si/Ga ratio of the first quantum well sublayer gradually decreases with increasing thickness.
Furthermore, the maximum value of the Si/Ga ratio of the first quantum well sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, the minimum value of the Si/Ga ratio of the first quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, and the minimum value of the Si/Ga ratio of the third quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer.
In another aspect, a method for manufacturing a light emitting diode epitaxial wafer is provided, the method comprising:
providing a substrate;
growing a low-temperature buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer on the substrate in sequence;
the multiple quantum well layer comprises quantum well layers and quantum barrier layers which are alternately grown, each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 1017cm-3～3*1017cm-3；
Each instituteThe quantum barrier layers comprise a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3(ii) a The Si/Ga ratio of the second quantum barrier layer is greater than the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer.
Furthermore, the growth temperature of the first quantum well sub-layer and the growth temperature of the third quantum well sub-layer are both greater than or equal to the growth temperature of the second quantum well sub-layer.
Furthermore, the growth temperature of the first quantum barrier layer and the growth temperature of the third quantum barrier layer are both less than or equal to the growth temperature of the second quantum barrier layer.
Further, the Si/Ga ratio of the first quantum well sublayer gradually decreases with increasing thickness.
The technical scheme provided by the embodiment of the invention has the following beneficial effects:
by dividing each quantum well layer into three sub-layers and enabling the In/Ga ratio of the second quantum well sub-layer to be larger than or equal to the In/Ga ratios of the first quantum well sub-layer and the third quantum well sub-layer, the In content In the second quantum well sub-layer is high, and the second quantum well sub-layer can be used as a main light emitting layer to guarantee the light emitting efficiency of the LED. The In content In the first quantum well sub-layer and the third quantum well sub-layer is low, and the first quantum well sub-layer and the third quantum well sub-layer are In contact with the quantum barrier layer, so that lattice mismatch between the quantum well layer and the quantum barrier layer can be reduced, and compressive stress is reduced. Meanwhile, a small amount of Si is doped in the first quantum well sub-layer, so that the electron concentration in the quantum well layer can be increased, the energy band tilt phenomenon of a multi-quantum well layer is improved, the overlapping degree of wave functions of electrons and holes in spatial distribution is increased, and the internal quantum efficiency of the LED is improved. And because Si is an impurity, the crystal quality of the well layer can be influenced by doping Si in the quantum well layer, and the first quantum well sub-layer is not a main light-emitting layer, so that the influence of Si impurity doping on the crystal quality of the well layer can be reduced by doping Si in the first quantum well sub-layer, and the light-emitting efficiency of the well layer is ensured. Furthermore, the quantum barrier layer is divided into three sub-layers, and the Si/Ga ratio of the second quantum barrier layer is larger than or equal to the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer, namely the doping concentration of Si in the first quantum barrier layer and the third quantum barrier layer which are in contact with the quantum well layer is low, so that the crystal quality of the first quantum barrier layer and the third quantum barrier layer can be ensured, the interface quality between the well barriers is improved, and the luminous efficiency of the LED can be further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a multiple quantum well layer provided by an embodiment of the present invention;
fig. 3 is a flowchart of a method for manufacturing an epitaxial wafer of a light emitting diode according to an embodiment of the present invention;
fig. 4 is a schematic energy band diagram of a conventional multiple quantum well layer;
fig. 5 is an energy band diagram of a multiple quantum well layer provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an led epitaxial wafer according to an embodiment of the present invention, and as shown in fig. 1, the led epitaxial wafer includes a substrate 1, and a buffer layer 2, an undoped GaN layer 3, an N-type layer 4, a multiple quantum well layer 5, a low-temperature P-type layer 6, an electron blocking layer 7, a high-temperature P-type layer 8, and a P-type contact layer 9 sequentially stacked on the substrate 1.
Fig. 2 is a schematic structural diagram of a multiple quantum well layer according to an embodiment of the present invention, and as shown in fig. 2, the multiple quantum well layer 5 includes a plurality of quantum well layers 51 and a plurality of quantum barrier layers 52 that are alternately grown.
Each quantum well layer 51 includes a first quantum well sub-layer 511, a second quantum well sub-layer 512, and a third quantum well sub-layer 513, which are sequentially stacked. The first quantum well sublayer 511, the second quantum well sublayer 512, and the third quantum well sublayer 513 are all InGaN layers. The In/Ga ratio of the second quantum well sublayer 512 is equal to or greater than the In/Ga ratio of the first quantum well sublayer 511 and the third quantum well sublayer 513. The first quantum well sublayer 511 is doped with Si, and the doping concentration of Si in the first quantum well sublayer 511 is 1 × 1017cm-3～3*1017cm-3。
Each quantum barrier layer 52 comprises a first quantum barrier layer 521, a second quantum barrier layer 522 and a third quantum barrier layer 523 which are sequentially stacked, the first quantum barrier layer 521, the second quantum barrier layer 522 and the third quantum barrier layer 523 are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3(ii) a The Si/Ga ratio of the second quantum barrier layer 522 is equal to or higher than the Si/Ga ratio of the first quantum barrier layer 521 and the third quantum barrier layer 523.
The In/Ga ratio represents a ratio of an In doping concentration to a Ga doping concentration, and the Si/Ga ratio represents a ratio of an Si doping concentration to a Ga doping concentration. In the present embodiment, the doping concentrations of Ga in each quantum well sublayer and each quantum barrier sublayer are equal.
In the present embodiment, the multiple quantum well layer 5 may include 8 to 15 quantum well layers 51 and 8 to 15 quantum barrier layers 52 alternately grown.
Further, the thickness ratio of the first quantum well sublayer 511, the second quantum well sublayer 512, and the third quantum well sublayer 513 is 1: m: m is more than or equal to 1 and 4 and less than or equal to 6, and m is a positive integer. The second quantum well sub-layer is a main light emitting layer, so that the thickness of the second quantum well sub-layer is set to be thicker, and the light emitting brightness of each quantum well layer can be ensured. Meanwhile, the first quantum well sub-layer is arranged to be thin, so that Si impurities can be prevented from being doped in the first quantum well sub-layer, and the influence on the crystal quality of the whole well layer can be prevented.
It should be noted that the specific thickness ratio of the first quantum well sublayer 511, the second quantum well sublayer 512 and the third quantum well sublayer 513 may be selected according to the light emitting wavelength of the desired LED device. The longer the emission wavelength, the more quantum well layer In amount is required, and the thicker the thickness of the second quantum well sublayer can be set. The longer and shorter the light emission, the less the total amount of In of the quantum well layer is required, and the thinner the thickness of the second quantum well sub-layer can be set.
Illustratively, when the emission wavelength of the desired LED device is 460nm to 470nm, the thickness ratio of the first, second, and third sub-layers 511, 512, and 513 may be set to 1: 4: 1. when the emission wavelength of the desired LED device is 515nm to 525nm, the thickness ratio of the first sublayer 511, the second sublayer 512, and the third sublayer 513 may be set to 1: 5: 1. when the emission wavelength of the desired LED device is 520nm to 530nm, the thickness ratio of the first sublayer 511, the second sublayer 512, and the third sublayer 513 may be set to 1: 6: 1.
alternatively, the total thickness of each quantum well layer 51 may be 2 to 3 nm. If the thickness of the quantum well layer 51 is less than 2nm, recombination light emission of electrons and holes in the quantum well layer 51 may be affected due to too small thickness of the quantum well layer 51, reducing the light emission efficiency of the LED. If the thickness of the quantum well layer 51 is greater than 3nm, more stress may be generated in the quantum well layer 51 due to too large thickness of the quantum well layer 51, affecting the crystal quality of the quantum well layer 51 and thus affecting the light emission efficiency of the LED.
Further, the thickness ratio of the first, second and third quantum barrier layers 521, 522 and 523 is 1: n: n is more than or equal to 1 and 4 and less than or equal to 6, and n is a positive integer. Since the doping concentration of Si in the second quantum barrier layer is the highest, the second quantum barrier layer can be used as a main barrier layer to block electron overflow. Therefore, the thickness of the second quantum barrier layer is set to be thick, and electron overflow can be reduced.
Optionally, the total thickness of each quantum barrier layer 52 may be 9-20 nm. If the thickness of quantum barrier layer 52 is less than 9nm, the effect of blocking the overflow of electrons may not be achieved due to the too small thickness of quantum barrier layer 52. If the thickness of the quantum barrier layer 52 is greater than 20nm, normal migration of carriers is easily affected, a blocking effect on recombination of electrons and holes is achieved, and the luminous efficiency of the LED is reduced.
Further, the Si/Ga ratio of the first quantum barrier layer 521 gradually increases with the increase in thickness, the Si/Ga ratio of the second quantum barrier layer 522 is constant, and the Si/Ga ratio of the third quantum barrier layer 523 gradually decreases with the increase in thickness. The doping concentration of the Si in the first quantum barrier layer is gradually increased, and the doping concentration of the Si in the part of the first quantum barrier layer, which is in contact with the quantum well layer, is less, so that the interface quality between the well barriers is improved. Similarly, the doping concentration of Si in the portion of the third quantum barrier layer in contact with the quantum well layer is gradually reduced, which is beneficial to improving the interface quality between the well barriers.
In the present embodiment, the Si/Ga ratio of the first quantum barrier layer 521 gradually increases to the Si/Ga ratio of the second quantum barrier layer 522, and the Si/Ga ratio of the third quantum barrier layer 523 gradually decreases from the Si/Ga ratio of the second quantum barrier layer to form a smooth transition.
Further, the Si/Ga ratio of the first quantum well sublayer 511 gradually decreases with increasing thickness. The doping concentration of Si in the portion of the first quantum well sublayer 511 close to the second quantum well sublayer 512 is low, so that the influence of the doped Si impurities on the second quantum well sublayer 512 can be reduced.
Optionally, the maximum value of the Si/Ga ratio of the first quantum well sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer. If the doping concentration of Si in the first quantum well sublayer is too low, the effect of improving the band tilt of the well layer is not achieved, and if the doping concentration of Si in the first quantum well sublayer is too high, the crystal quality of the quantum well layer is affected.
Furthermore, the minimum value of the Si/Ga ratio of the first quantum barrier layer is 20-30% of the Si/Ga ratio of the second quantum barrier layer, and the minimum value of the Si/Ga ratio of the third quantum barrier layer is 20-30% of the Si/Ga ratio of the second quantum barrier layer. At the moment, the quantum barrier layer can be ensured to play a role in blocking electron overflow, and the interface quality between the well barriers can be ensured.
Alternatively, the substrate 1 may be a sapphire substrate.
Alternatively, the buffer layer 2 may be an AlN layer with a thickness of 15 to 35 nm.
Optionally, the thickness of the undoped GaN layer 3 is 1-3 um.
Optionally, the N-type layer 4 can be a Si-doped GaN layer with a thickness of 1-5 um.
Optionally, the low-temperature P-type layer 6 can be a GaN layer doped with Mg, and the thickness is 10-40 nm.
Optionally, the electron blocking layer 7 may be an AlGaN layer doped with Mg, the thickness of the AlGaN layer is 20 to 30nm, and the doping concentration of Mg is less than 1 × 1019cm-3。
Optionally, the P-type layer 8 may be a Mg-doped GaN layer with a thickness of 10-30 nm, and a Mg doping concentration greater than or equal to 1 × 1020cm-3。
Optionally, the P-type contact layer 9 may be a heavily doped Mg GaN layer with a thickness of 30-50 nm and a Mg doping concentration greater than or equal to 1 × 1020cm-3，
An embodiment of the present invention provides a method for manufacturing an led epitaxial wafer, which is used to manufacture an led epitaxial wafer provided in the first embodiment of the present invention, and fig. 3 is a flowchart of a method for manufacturing an led epitaxial wafer provided in the first embodiment of the present invention, as shown in fig. 3, the method includes:
In this embodiment, the substrate is sapphire, and the substrate may be placed on a graphite tray and fed into the reaction chamber for epitaxial material growth.
Step 301 further comprises:
and controlling the temperature of the reaction chamber to 1050 ℃ and the pressure to 200-500 Torr, annealing the sapphire substrate in a pure hydrogen atmosphere for 5-6 min, and then nitriding the sapphire substrate.
The invention uses Veeco EPIK700 MOCVD to grow the high-brightness GaN-based LED epitaxial wafer. High-purity H2 or high-purity N2 or the mixed gas of high-purity H2 and high-purity N2 is used as carrier gas, high-purity NH3 is used as N source, trimethyl gallium (TMGa) and triethylGallium (TEGa) as a gallium source, trimethylindium (TMIn) as an indium source, silane (SiH4) as an N-type dopant, trimethylaluminum (TMAl) as an aluminum source, magnesium dicylocene (CP)2Mg) as a P-type dopant, the substrate is (0001) plane sapphire, and the chamber pressure is between 50torr and 600 torr.
Wherein the buffer layer is an AlN layer.
Specifically, the substrate is placed in a reaction chamber of a PVD (Physical Vapor Deposition) apparatus, and an AlN buffer layer is grown by a PVD method, including: adjusting the temperature in a reaction cavity of the PVD equipment to 400-700 ℃, adjusting the sputtering power to 3000-5000W, adjusting the pressure to 1-10 mtorr, and growing an AlN buffer layer with the thickness of 15-35 nm.
The undoped GaN layer, the N-type layer, the multi-quantum well layer, the low-temperature P-type layer, the electron blocking layer, the P-type layer, and the P-type contact layer in the epitaxial layer may be grown by the MOCVD (Metal-organic Chemical Vapor Deposition) method. In particular implementation, the substrate is generally placed on a graphite tray and fed into the reaction chamber of the MOCVD equipment to carry out the growth of the epitaxial material, so that the temperature and pressure controlled in the growth process actually refer to the temperature and pressure in the reaction chamber. Specifically, trimethyl gallium or trimethyl ethyl is used as a gallium source, triethyl boron is used as a boron source, high-purity ammonia gas is used as a nitrogen source, trimethyl indium is used as an indium source, trimethyl aluminum is used as an aluminum source, an N-type dopant is selected from silane, and a P-type dopant is selected from magnesium cyclopentadienyl.
Illustratively, the temperature of the reaction chamber is controlled to be 1000-1200 ℃, the pressure is controlled to be 100-500 torr, and an undoped GaN layer with the thickness of 1-3 um is grown.
Wherein the N-type layer is a Si-doped GaN layer, and the doping concentration of Si can be 1018cm-3～1019cm-3。
Illustratively, the temperature of the reaction chamber is controlled to be 1000-1200 ℃, the pressure is controlled to be 100-300 torr, and the N-type GaN layer with the thickness of 1-5 um is grown.
In the present embodiment, the multiple quantum well layer 5 may include 8 to 15 quantum well layers and 8 to 15 quantum barrier layers alternately grown.
Each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked. The first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are all InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than or equal to that of the first quantum well sub-layer and the third quantum well sub-layer. The first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 1017cm-3～3*1017cm-3。
Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked. The first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3. The Si/Ga ratio of the second quantum barrier layer is larger than or equal to the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer.
The In/Ga ratio represents a ratio of an In doping concentration to a Ga doping concentration, and the Si/Ga ratio represents a ratio of an Si doping concentration to a Ga doping concentration. In the present embodiment, the doping concentrations of Ga in each quantum well sublayer and each quantum barrier sublayer are equal.
Further, the thickness ratio of the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer is 1: m: m is more than or equal to 1 and 4 and less than or equal to 6, and m is a positive integer.
Alternatively, the total thickness of each quantum well layer may be 2 to 3 nm.
It should be noted that the specific thickness ratio of the first quantum well sublayer, the second quantum well sublayer and the third quantum well sublayer may be selected according to the size of the light emitting wavelength of the desired LED device.
Further, the thickness ratio of the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer is 1: n: n is more than or equal to 1 and 4 and less than or equal to 6, and n is a positive integer.
Optionally, the total thickness of each quantum barrier layer can be 9-20 nm.
Further, the Si/Ga ratio of the first quantum barrier layer gradually increases with the increase of the thickness, the Si/Ga ratio of the second quantum barrier layer is constant, and the Si/Ga ratio of the third quantum barrier layer gradually decreases with the increase of the thickness.
Further, the Si/Ga ratio of the first quantum well sub-layer gradually decreases with increasing thickness.
Furthermore, the maximum value of the Si/Ga ratio of the first quantum well sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, the minimum value of the Si/Ga ratio of the first quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, and the minimum value of the Si/Ga ratio of the third quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer.
Optionally, the growth temperature of each of the first quantum well sublayer and the third quantum well sublayer is greater than or equal to the growth temperature of the second quantum well sublayer. Because the low temperature is favorable for In incorporation, the growth temperature of the second quantum well sub-layer is set to be lower, and the In/Ga ratio of the second quantum well sub-layer can be favorably improved, so that the half-wave width of light emission of the LED device is favorably reduced, and the light emission concentration and the light emission intensity of the LED device are improved.
In this embodiment, the growth temperature of the first quantum well sublayer is gradually reduced to the growth temperature of the second quantum well sublayer, the second quantum well sublayer grows at a constant temperature, and the growth temperature of the third quantum well sublayer is gradually increased from the growth temperature of the second quantum well sublayer to form a smooth transition.
Optionally, the maximum value of the growth temperature of the first quantum well sub-layer is 30-50 ℃ higher than the growth temperature of the second quantum well sub-layer, and the maximum value of the growth temperature of the third quantum well sub-layer is 30-50 ℃ higher than the growth temperature of the second quantum well sub-layer.
Illustratively, the growth temperature of the first quantum well sub-layer is gradually reduced to 790-800 ℃ from 830-840 ℃, the growth temperature of the second quantum well sub-layer is 790-800 ℃, and the growth temperature of the third quantum well sub-layer is gradually increased to 830-840 ℃ from 790-800 ℃.
Optionally, the growth temperature of each of the first quantum well sublayer and the third quantum well sublayer is greater than or equal to the growth temperature of the second quantum well sublayer. Because the low temperature is favorable for In incorporation, the growth temperature of the second quantum well sub-layer is set to be lower, and the In/Ga ratio of the second quantum well sub-layer can be favorably improved, so that the half-wave width of light emission of the LED device is favorably reduced, and the light emission concentration and the light emission intensity of the LED device are improved.
In this embodiment, the growth temperature of the first quantum barrier layer is gradually increased to the growth temperature of the second quantum barrier layer, the second quantum barrier layer grows at a constant temperature, and the growth temperature of the third quantum barrier layer is gradually decreased from the growth temperature of the second quantum barrier layer to form a smooth transition.
Optionally, the maximum value of the growth temperature of the first quantum barrier layer is 20-30 ℃ lower than the growth temperature of the second quantum barrier layer, and the maximum value of the growth temperature of the third quantum barrier layer is 30-30 ℃ lower than the growth temperature of the second quantum barrier layer.
Illustratively, the growth temperature of the first quantum barrier layer is gradually increased from 830-840 ℃ to 850-870 ℃, the growth temperature of the second quantum barrier layer is 850-870 ℃, and the growth temperature of the third quantum barrier layer is gradually decreased from 850-870 ℃ to 830-840 ℃.
At the moment, the temperature difference between the contact parts of the quantum well layer and the quantum barrier layer is small, so that the phenomenon that the growth temperature of the quantum barrier layer is high to damage the crystal quality of the quantum well layer can be prevented, and the effect of protecting the quantum well is achieved. And meanwhile, the precipitation of In the quantum well can be reduced, and the luminous intensity of the LED device is improved.
Optionally, the growth pressure of the quantum well layer and the growth pressure of the quantum barrier layer are both 100-300 Torr.
And step 306, growing a low-temperature P-type layer on the multi-quantum well layer.
Wherein, the low temperature P type layer can be a GaN layer doped with Mg, and the thickness is 10-40 um.
Illustratively, the temperature of the reaction chamber is controlled to be 700-800 ℃, the pressure is controlled to be 100-600 Torr, and a low-temperature P-type layer with the thickness of 10-40 um is grown.
Wherein the electron blocking layer is an AlGaN layer doped with Mg, and the doping concentration of Mg in the electron blocking layer is less than 1019cm-3。
Exemplarily, the temperature of the reaction chamber is controlled to be 900-1000 ℃, the pressure is controlled to be 100-300 Torr, and the electron blocking layer with the thickness of 20-30 nm is grown.
Wherein the P-type layer is a GaN layer doped with Mg, and the doping concentration of Mg in the P-type layer is greater than or equal to 1020cm-3
Illustratively, the temperature of the reaction chamber is controlled to be 900-980 ℃, the pressure is controlled to be 300-600 Torr, and a P-type layer with the thickness of 10-30 nm is grown.
Step 309 grows a P-type contact layer on the P-type layer.
Wherein the P-type contact layer can be a heavily doped Mg GaN layer, and the doping concentration of Mg is greater than or equal to 1 x 1020cm-3。
Illustratively, the temperature of the reaction chamber is controlled to be 850-1050 ℃, the pressure is controlled to be 100-600 Torr, and a P-type contact layer with the thickness of 30-50 nm is grown.
After the steps are completed, the temperature of the reaction chamber is reduced to 650-850 ℃, annealing treatment is carried out for 5-15 min in a nitrogen atmosphere, then the temperature is gradually reduced to the room temperature, and the epitaxial growth of the light emitting diode is finished.
Fig. 4 is a schematic energy band diagram of a conventional mqw layer, and fig. 5 is a schematic energy band diagram of an mqw layer according to an embodiment of the present invention, and as shown in fig. 4 and 5, the present invention provides an mqw layer having an improved energy band inclination compared to the conventional mqw layer, and an overlapping region of wave functions of electrons and holes in spatial distribution is increased.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A light emitting diode epitaxial wafer comprises a substrate, and a buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer which are sequentially laminated on the substrate, wherein the multi-quantum well layer comprises a quantum well layer and a quantum barrier layer which are alternately grown,
each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are all InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 1017cm-3～3*1017cm-3；
Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3(ii) a The Si/Ga ratio of the second quantum barrier layer is greater than the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer;
the Si/Ga ratio of the first quantum barrier layer is gradually increased along with the increase of the thickness, the Si/Ga ratio of the second quantum barrier layer is constant, and the Si/Ga ratio of the third quantum barrier layer is gradually reduced along with the increase of the thickness.
2. The light emitting diode epitaxial wafer of claim 1, wherein the thickness ratio of the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer is 1: m: m is more than or equal to 1 and 4 and less than or equal to 6, and m is a positive integer.
3. The light emitting diode epitaxial wafer of claim 1, wherein the thickness ratio of the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer is 1: n: n is more than or equal to 1 and 4 and less than or equal to 6, and n is a positive integer.
4. The light emitting diode epitaxial wafer of claim 1, wherein the Si/Ga ratio of the first quantum well sub-layer gradually decreases with increasing thickness.
5. The light-emitting diode epitaxial wafer according to claim 1, wherein the maximum value of the Si/Ga ratio of the first quantum well sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, the minimum value of the Si/Ga ratio of the first quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer, and the minimum value of the Si/Ga ratio of the third quantum barrier sub-layer is 20-30% of the Si/Ga ratio of the second quantum barrier sub-layer.
6. A manufacturing method of a light emitting diode epitaxial wafer is characterized by comprising the following steps:
providing a substrate;
growing a low-temperature buffer layer, an undoped GaN layer, an N-type layer, a multi-quantum well layer, an electronic barrier layer, a P-type layer and a P-type contact layer on the substrate in sequence;
the multiple quantum well layer comprises quantum well layers and quantum barrier layers which are alternately grown, each quantum well layer comprises a first quantum well sub-layer, a second quantum well sub-layer and a third quantum well sub-layer which are sequentially stacked, the first quantum well sub-layer, the second quantum well sub-layer and the third quantum well sub-layer are InGaN layers, and the In/Ga ratio of the second quantum well sub-layer is larger than that of the first quantum well sub-layer and that of the third quantum well sub-layer; the first quantum well sub-layer is doped with Si, and the doping concentration of Si in the first quantum well sub-layer is 1 x 1017cm-3～3*1017cm-3；
Each quantum barrier layer comprises a first quantum barrier layer, a second quantum barrier layer and a third quantum barrier layer which are sequentially stacked, the first quantum barrier layer, the second quantum barrier layer and the third quantum barrier layer are all Si-doped GaN layers, and the doping concentration of Si in the quantum barrier layers is 3 x 1017cm-3～5*1017cm-3(ii) a The Si/Ga ratio of the second quantum barrier layer is greater than the Si/Ga ratio of the first quantum barrier layer and the third quantum barrier layer;
the Si/Ga ratio of the first quantum barrier layer is gradually increased along with the increase of the thickness, the Si/Ga ratio of the second quantum barrier layer is constant, and the Si/Ga ratio of the third quantum barrier layer is gradually reduced along with the increase of the thickness.
7. The manufacturing method according to claim 6, wherein the growth temperature of each of the first quantum well sub-layer and the third quantum well sub-layer is equal to or higher than the growth temperature of the second quantum well sub-layer.
8. The manufacturing method according to claim 6, wherein the growth temperature of each of the first quantum barrier layer and the third quantum barrier layer is equal to or lower than the growth temperature of the second quantum barrier layer.
9. The method of claim 6, wherein the Si/Ga ratio of the first quantum well sublayer decreases gradually with increasing thickness.
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