CN110689913B

CN110689913B - Nonvolatile memory device

Info

Publication number: CN110689913B
Application number: CN201810730072.XA
Authority: CN
Inventors: 朴起台; 吴贤实
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-07-05
Filing date: 2018-07-05
Publication date: 2024-07-26
Anticipated expiration: 2038-07-05
Also published as: CN110689913A

Abstract

There is provided a nonvolatile memory device including: a memory cell array including a plurality of memory cells arranged in word lines and bit lines; a voltage generator generating a program voltage pulse applied to a selected word line among the word lines, a first pass voltage applied to a first unselected word line adjacent to the selected word line among the word lines, and a second pass voltage applied to a second unselected word line not adjacent to the selected word line among the word lines; and control logic to iteratively increase the programming voltage pulse and to differently increase the first pass voltage and the second pass voltage according to an iteration of the increase of the programming voltage pulse.

Description

Nonvolatile memory device

Technical Field

The present inventive concept relates generally to nonvolatile memory devices. More particularly, the inventive concept relates to a nonvolatile memory device controlling a program voltage pulse.

Background

Examples of nonvolatile memory devices include flash memory devices and variable resistance memory devices. Current flash memory devices may be generally classified as NAND flash memory or NOR flash memory. NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines. NOR flash memory has the characteristic of fast (random) data access speed. In contrast, NAND flash requires only one contact per memory cell string because multiple memory cells are connected in series.

Flash memory, like other forms of non-volatile memory, retains stored data in the absence of applied power. Flash memory is widely used to store programming code and payload data in mobile devices such as cellular telephones, PDA digital cameras, portable game controllers, and MP3 players. Flash memory devices may also be used in home appliances such as HDTV, DVD, routers and GPS.

To further increase the data storage density, many conventional nonvolatile memory devices are configured to include an array of memory cells that includes a plurality of multi-bit memory cells, each multi-bit memory cell capable of storing more than one bit of data. Multi-bit memory cells are collectively referred to as multi-level cells (MLC), while single-level memory cells are referred to as single-level cells (SLC). As is well known in the art, MLCs operate to store data using two or more threshold voltage distributions.

Disclosure of Invention

Embodiments of the inventive concept provide a nonvolatile memory device capable of maintaining an increased program voltage in relation to a defined ISPP constant. Embodiments of the inventive concept also provide a nonvolatile memory device having improved pass voltage window characteristics with reduced possibility of over-programming of memory cells.

In one embodiment, the present inventive concept provides a memory device comprising: a memory cell array including a plurality of memory cells arranged in word lines and bit lines; a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines and a pass voltage applied to an unselected word line; and control logic configured to iteratively increase the level of the program voltage pulse and adjust the level of the pass voltage according to defined increments during a programming operation.

In another embodiment, the present inventive concept provides a nonvolatile memory device including: a memory cell array including a plurality of memory cells arranged in word lines and bit lines; a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines and at least one pass voltage applied to unselected word lines; and control logic configured to iteratively increase the programming voltage pulse and apply different pass voltages having different voltage levels to unselected word lines depending on their locations in the memory cell array, wherein the control logic is further configured to fix the pass voltages applied to unselected word lines adjacent to the selected word line at a constant level during a programming operation.

In another embodiment, the present inventive concept provides a nonvolatile memory device including: a memory cell array including a plurality of memory cells arranged in word lines and bit lines; a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines and at least one pass voltage applied to unselected word lines; and control logic configured to iteratively increase the programming voltage pulses during a programming operation, wherein the control logic is further configured to determine a location of the selected word line, and the voltage generator is further configured to control a level of the pass voltage during the programming operation in accordance with the location of the selected word line in the memory cell array.

In another embodiment, the present inventive concept provides a nonvolatile memory device including: a memory cell array including a plurality of memory cells arranged in word lines and bit lines; a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines and a pass voltage applied to an unselected word line; and control logic configured to control the voltage generator to iteratively increase the programming voltage in increments during a programming operation, wherein the control logic is further configured to determine a location of a selected word line in the memory cell array, the voltage generator further configured to control an initial voltage level of the programming voltage during the programming operation in accordance with the determined location of the selected word line.

Drawings

Embodiments of the inventive concept will be described with reference to the accompanying drawings. In the drawings:

Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concept;

Fig. 2 is a conceptual diagram further illustrating a string of memory cells in the memory cell array of fig. 1;

fig. 3 is a timing diagram illustrating Incremental Step Pulse Programming (ISPP) according to an embodiment of the inventive concept;

Fig. 4 is a conceptual cross-sectional view illustrating a memory cell string in the memory cell array of fig. 1;

FIG. 5 is a graph showing the ratio of threshold voltage to ISPP iteration number (#);

FIG. 6 is a timing diagram further illustrating the programming voltage pulses and associated pass voltages of FIG. 5;

FIG. 7 is a graph showing threshold voltage distributions of program voltage pulses according to FIG. 6;

FIG. 8 is a graph showing the number of ISPP iterations of the threshold voltage versus the programming voltage in FIG. 6;

fig. 9 is a timing diagram further illustrating programming voltages and associated pass voltages according to an embodiment of the inventive concept;

Fig. 10 is a conceptual diagram illustrating a memory cell string supplied with a program voltage and a pass voltage according to another embodiment of the inventive concept;

FIG. 11 is a timing diagram further illustrating the program voltage and pass voltage of FIG. 10;

FIG. 12 is a diagram showing memory cell strings provided with different pass voltages via word lines in respective word line regions;

Fig. 13 is a conceptual diagram illustrating a program voltage and application of a pass voltage according to another embodiment of the inventive concept.

Fig. 14 is a graph showing exemplary levels of the pass voltage of fig. 13;

FIG. 15 is a flow chart summarizing a method of providing the pass voltage of FIG. 13;

FIG. 16 is a graph illustrating exemplary programming voltages according to another embodiment of the inventive concept;

FIG. 17 is a flowchart summarizing a method of providing the programming voltages of FIG. 16;

fig. 18 is a graph showing the result of a program operation using the program voltages of fig. 14 and 16;

fig. 19 is a diagram showing another example of applying a voltage to a cell string;

FIG. 20 is a timing diagram illustrating an example of applying the program voltage, the first dynamic pass voltage, and the second dynamic pass voltage of FIG. 19;

fig. 21 is a diagram showing an example of a time when a program voltage is applied;

Fig. 22 is a diagram showing another example of the time at which the program voltage is applied;

Fig. 23 is a diagram showing another example of applying a voltage to a cell string;

FIG. 24 is a timing diagram illustrating an example of applying the second dynamic pass voltage and the third dynamic pass voltage of FIG. 23;

Fig. 25 is a diagram showing an example of one of the memory blocks of the memory cell array of fig. 1;

fig. 26 is a diagram showing an example of applying a voltage to a cell string having the structure described with reference to fig. 25;

Fig. 27 is a diagram showing another example of applying a voltage to a cell string having the structure described with reference to fig. 25;

Fig. 28 is a diagram showing another example of applying a voltage to a cell string having the structure described with reference to fig. 25;

fig. 29 is a diagram showing an example of another memory block among the memory blocks of the memory cell array of fig. 1;

fig. 30 is a diagram showing an example of another memory block among memory blocks of the memory cell array of fig. 1;

fig. 31 is a diagram showing an example of another memory block among memory blocks of the memory cell array of fig. 1;

FIG. 32 is a block diagram illustrating a computing system including a memory device in accordance with an embodiment of the inventive concept; and

Fig. 33 is a block diagram illustrating a memory-based storage device according to an embodiment of the inventive concept.

Detailed Description

Embodiments of the inventive concept will now be described in some additional detail with reference to the accompanying drawings. The inventive concept may, however, be embodied in different forms and should not be construed as being limited to only the illustrated embodiments. Rather, these embodiments are provided as teaching examples.

Since design rules of flash memory devices have been simplified for many years, the importance of defining and properly maintaining a so-called pass voltage (Vpass) window has become large. For example, in a program operation of a flash memory, a program voltage (Vpgm) is applied to a selected word line, and a pass voltage (Vpass) is applied to unselected word lines. Since the well-known program voltage disturbance may be caused by a low pass voltage, a program inhibit unit connected to a word line to which a program voltage is applied among a plurality of memory cells is programmed, thus causing a failure situation to occur. In contrast, when the pass voltage disturbance results from a high pass voltage, a cell to which the pass voltage is applied among memory cells connected to the same cell string is programmed and also causes a case in which a failure occurs. That is, the pass voltage window represents a pass voltage range in which neither pass voltage disturb nor program voltage disturb occurs. Thus, a larger pass voltage window may be utilized to enable the flash memory device to operate with higher reliability.

To improve the pass voltage window (e.g., maximize the pass voltage window), the corresponding pass voltage may be controlled during a programming operation in response to a programming voltage that increases according to a defined Incremental Step Pulse Programming (ISPP). Here, an increase in the program voltage is constantly maintained to perform an accurate program operation.

Fig. 1 is a block diagram illustrating a memory system according to an embodiment of the inventive concept. Referring to fig. 1, a memory system 100 generally includes a memory device 110 and a memory controller (or flash controller) 120.

For the purposes of the following description, memory device 110 is assumed to be a flash memory device. Alternatively, the memory device 110 may be a phase change random access memory (PRAM), a Magnetoresistive Random Access Memory (MRAM), or a Resistive Random Access Memory (RRAM).

In the illustrated embodiment of fig. 1, memory device 110 includes a memory cell array 111 capable of storing M bits of data per memory cell, where M is a positive integer. The memory cell array 111 may be divided into a plurality of areas, and various areas may be defined according to the type of data stored, for example, a general (payload) data area, a spare data area, and the like. The various regions of the memory cell array 111 may each include a plurality of memory blocks. Since the construction of the memory array into a plurality of memory blocks is well known to those skilled in the art, a description thereof will be omitted.

The memory device 110 also includes a page buffer 112, a decoder 113, a voltage generator (e.g., a high voltage generator) 114, control logic 115, and an input/output interface 116. The page buffer 112 may be configured to read data from the memory cell array 111/program data to the memory cell array 111 according to control of the control logic 115. Decoder 113 may be configured to be controlled by control logic 115 and to select a memory block of memory cell array 111 and a word line of the selected memory block. The selected word line may be driven by a word line voltage from voltage generator 114. The voltage generator 114 may be configured to be controlled by the control logic 115 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, and verify voltages) to supply to the memory cell array 111. Control logic 115 may be configured to control the overall operation of flash memory device 110.

Referring again to fig. 1, the memory controller 120 may be configured to control the memory device 110 in response to a request from an external (e.g., host). Although not shown, the memory controller 120 may include a processing unit such as a central processing unit or microprocessor, ECC, and buffer memory as is known in the art.

To improve the pass voltage window, the memory device 110 may increase the pass voltage in stages during a programming operation in response to a programming voltage that increases according to ISPP. These features will be described in detail with reference to fig. 2 and 3.

Fig. 2 is a conceptual diagram further illustrating a string (e.g., a cell string) of memory cells (hereinafter referred to as "string cells") in the memory cell array of fig. 1.

Referring to fig. 2, a program voltage Vpgm may be applied to a "middle memory cell" located at or near the center of a string cell. The dynamic pass voltage dynamic Vpass is applied to the word lines of other memory cells. The dynamic pass voltage (dynamic Vpass) represents the pass voltage that increases in a series of iterations according to the defined ISPP in order to improve the corresponding pass voltage window. The general purpose of ISPP is conventionally understood, and those skilled in the art will recognize that many different ISPPs may be used within embodiments of the inventive concept. Hereinafter, one possible ISPP will be described in some supplementary detail with reference to fig. 3 as an example of many other ISPPs that may be used.

Fig. 3 is a timing diagram illustrating an exemplary ISPP according to an embodiment of the inventive concept.

Referring to fig. 3, the pulse-shaped programming voltage (Vpgm) is stepped up over a series of iterations under the control of an exemplary ISPP. That is, in the example shown, the program voltage Vpgm is increased by a fixed increment value (Δispp) during each iteration to form a stepped-up program pulse waveform.

In order to improve the corresponding pass voltage window, a plurality of pass voltage groups are each applied differently. For example, a low programming voltage set may include lower programming pulses (e.g., P1 through P3), a medium programming voltage set may include relatively higher (or mid-range) programming pulses (e.g., pk-1 through Pk), and a high programming voltage set may include higher (or highest) programming pulses (e.g., pj-1 through Pj).

Accordingly, particular embodiments of the inventive concept may control the generation and provision of the pass voltage (Vpass) according to the defined ISPP. However, such control methods can result in an undesirable increase in the voltage potential of the floating gate associated with the selected memory cell. This phenomenon will be described in some additional detail with reference to fig. 4.

Fig. 4 is a diagram further illustrating a cell string of the memory cell array of fig. 1. Referring to fig. 4, a memory cell receiving a program voltage Vpgm is located between two memory cells receiving a pass voltage Vpass. Accordingly, parasitic capacitance "Cp" is generated between the floating gate of the memory cell receiving the program voltage Vpgm and the gate terminal of the adjacent memory cell. Although not shown in fig. 4, parasitic capacitance may be generated between all cell strings in the memory cell array. This parasitic capacitance has the greatest effect on the selected memory cell receiving the program voltage Vpgm when it is located adjacent to two unselected memory cells.

If the pass voltage Vpass increases according to ISPP, the parasitic capacitance increases the potential of the floating gate of the memory cell receiving the program voltage Vpgm. Therefore, in order to offset the effect of parasitic capacitance, the level of the program voltage should be carefully controlled. This requirement is further described with reference to fig. 5.

Fig. 5 is a graph showing the ratio of threshold voltage (Vth) to ISPP iterations.

Referring collectively to fig. 3-5, the horizontal axis of the graph is the number (#) of ISPP iterations and the vertical axis of the graph is the level of the threshold voltage Vth. The hypothetical slope of the ISPP delta is about 0.3. That is, the program voltage Vpgm pulse increases by about 0.3V during each increment. A coupling ratio of the parasitic capacitance Cp of about 0.1 is also assumed.

Under these assumptions, if the pass voltage Vpass applied to the adjacent word line increases by about 1.0V, the potential on the floating gate of the memory cell connected to the selected word line increases by about 0.2V. Thus, the slope of ISPP at the inflection point "t" further increases by about 0.2 for the pass voltage Vpass. The fluctuation of the programming voltage pulses caused by parasitic capacitances and the corresponding effects are further described with respect to fig. 6 and 7.

Fig. 6 is a timing diagram further illustrating the programming voltage pulses and associated pass voltages of fig. 5. The program voltage pulse is stepped up from a starting voltage of about 15V (Vpgm start) to a stopping voltage of about 25V (Vpgm stop) each iteration.

As described in fig. 2, the dynamic pass voltage (dynamic Vpass) represents a pass voltage that fluctuates according to ISPP. The dynamic pass voltage increases from about 8V to about 9V at point T1. The dynamic pass voltage then increases from about 9V to about 10V at point T2. The results of a programming operation using the exemplary programming voltage pulses and pass voltages are depicted in FIG. 7.

Fig. 7 is a graph illustrating a threshold voltage distribution defined by the program voltage pulse of fig. 6. That is, if the program voltage pulse described in fig. 6 is applied, the threshold voltage distribution shows an over-programming phenomenon (over-program phenomenon) due to an increase in the program voltage caused by parasitic capacitance. That is, as shown in fig. 7, the dynamic pass voltage ISPP may have a threshold voltage Vth wider than that of the conventional ISPP. In view of the foregoing, the increase in width of the ISPP must be carefully controlled. This requirement will be described in some additional detail with reference to fig. 8.

Fig. 8 is a graph further illustrating a relationship between a threshold voltage (Vth) and the ISPP iteration number in generating the program voltage illustrated in fig. 6.

Referring to fig. 8, the slope of the program voltage pulse is assumed to be about 0.3. That is, the programming voltage pulse is increased by about 0.3V. If the dynamic pass voltage increases from about 8V to about 9V at point T1, the potential of the floating gate of the memory cell connected to the selected word line will be raised by the parasitic capacitance Cp described in fig. 4.

For example, the coupling ratio of the parasitic capacitance Cp is assumed to be about 0.1. If the dynamic pass voltage increases from about 8V to about 9V, the potential of the floating gate of the memory cell connected to the selected word line increases by about 0.2V. Thus, the K-1 th programming voltage pulse Pk-1 may be increased by about 0.2V. And if the dynamic pass voltage increases from about 9V to about 10V at point T2, the potential of the floating gate of the memory cell connected to the selected word line is raised by the parasitic capacitance Cp described in fig. 4.

With the previous assumption, if the dynamic pass voltage increases from about 9V to about 10V, the potential of the floating gate of the memory cell connected to the selected word line increases by about 0.2V. Thus, the J-1 th programming voltage pulse Pj-1 may be increased by about 0.2V.

In a specific embodiment of the inventive concept, it is assumed that the level of the applied pass voltage fluctuates according to each program voltage pulse. In addition, the program voltage pulses according to ISPP may be divided into several program voltage pulse groups, and the level of the applied pass voltage may fluctuate according to each group.

During the application of the J-1 th and J-th programming voltage pulses Pj-1 and Pj, in which the occurrence of the programming voltage disturbance is most concentrated, the increase in the width of the programming voltage pulse is controlled.

To counteract the effect of parasitic capacitance, the increased width of the programming voltage pulse may be appropriately controlled upon fluctuation of the pass voltage applied to the unselected word lines. That is, the programming voltage pulse is controlled to increase while canceling the raised potential caused by the parasitic capacitance. This method will be described in some additional detail with reference to fig. 9.

Fig. 9 is a timing diagram illustrating a program voltage and a pass voltage according to an embodiment. Referring to fig. 9, the program voltage and the dynamic pass voltage will be described.

The programming voltage pulse increases in increments of about 0.3V from a starting voltage of about 15V to a stopping voltage of about 25V. However, the program voltage pulse (Vpgm pulse) is only increased by about 0.1V at the "control iteration" that occurs, for example, at points T1 and T2 of fig. 6. These control increments correspond to points where the pass voltage fluctuates under the influence of parasitic capacitance.

As noted previously, the dynamic pass voltage increases from about 8V to about 9V at point T1 and from about 9V to about 10V at point T2. The fluctuation of the dynamic pass voltage further increases the level of the program voltage pulse (Vpgm pulse) because this level is increased by the parasitic capacitance described in fig. 4. Thus, over-programming may occur as shown in fig. 7.

Thus, the programming voltage pulse is increased by counteracting the voltage level associated with parasitic capacitance Cp at points T1 and T2 where dynamic pass voltage fluctuations are expected. Thus, under the working assumption of the illustrated embodiment, the programming voltage pulse is increased by a "control increment" of only about 0.1V at the control iterations that occur at points T1 and T2. In addition, the programming voltage pulse increases from a 15V start voltage to a stop voltage in "normal increments" of about 0.3V.

To offset the effect of parasitic capacitance, the increased width of the program voltage pulse may be appropriately controlled when the pass voltage applied to the unselected word lines fluctuates. That is, the fluctuation of the program voltage under the influence of the parasitic capacitance may be offset according to embodiments of the inventive concept. Accordingly, the pass voltage applied to the unselected word lines adjacent to the selected word line can be constantly maintained. Other unselected word lines receive the dynamic pass voltage. This will be described in some additional detail with reference to fig. 10 and 11.

Fig. 10 is a diagram illustrating a cell string receiving a program voltage and a pass voltage according to another embodiment of the inventive concept.

As shown in fig. 10, it is assumed that parasitic capacitance is located between a memory cell receiving a program voltage (Vpgm) and an adjacent memory cell. To counteract the effect of parasitic capacitance, a pass voltage (constant Vpass) having a constant voltage level is applied to memory cells adjacent to the memory cell receiving the program voltage. The dynamic pass voltage (dynamic Vpass) is applied to other memory cells. In the illustrated embodiment, the dynamic pass voltage may be the same as the dynamic pass voltage described with respect to fig. 2. These control voltages and their various relationships will be further described in some additional detail with reference to fig. 11.

Fig. 11 is a timing diagram further illustrating the program voltage and pass voltage of fig. 10. As shown in fig. 11, a program voltage (Vpgm) and a constant pass voltage (constant Vpass) and a dynamic pass voltage (dynamic Vpass) according to a fluctuation of the program voltage are shown.

Similar to fig. 6, the program voltage increases from a start voltage of about 15V (Vpgm start) to a stop voltage of about 25V (Vpgm stop) in normal increments of about 0.3V. As depicted in fig. 2, the dynamic pass voltage represents the pass voltage that fluctuates according to ISPP defining the program voltage.

The dynamic pass voltage of the illustrated embodiment increases from about 8V to about 9V at a first control iteration (point T1) and from about 9V to about 10V at a second control iteration (point T2). If the voltage of the program voltage is constantly increased by the parasitic capacitance Cp described in fig. 4, the voltage of the program voltage may be further increased by the fluctuation of the voltage. Thus, over-programming may occur as described in fig. 7.

The memory cells connected to the selected word line receive a program voltage. Among the memory cells connected to the unselected word lines, the memory cells adjacent to the selected memory cell receiving the program voltage receive a constant pass voltage. In the illustrated embodiment, the constant pass voltage is about 9V. Other (non-adjacent) memory cells connected to the unselected word lines receive the dynamic pass voltage.

The parasitic capacitance of the memory cell adjacent to the selected memory cell has the greatest effect on the selected memory cell. Accordingly, the pass voltages applied to adjacent memory cells are maintained constant to offset the effect of parasitic capacitance.

Hereinafter, a method of preventing an over-program condition potentially caused by parasitic capacitance when different pass voltages are applied to various word lines is described.

Fig. 12 is a conceptual diagram illustrating memory cells in a cell string that receive different pass voltages via associated word lines according to the locations of the memory cells within the cell string.

As shown in fig. 12, the cell string is divided into a first region (region 1), a second region (region 2), and a third region (region 3), each including a plurality of word lines connected to memory cells in the cell string. For example, assuming that 64 word lines are arranged in parallel to access data from a corresponding numbered memory cell of the memory cells forming the cell string, a first region may include word lines 0 through 19, a second region may include word lines 20 through 43, and a third region may include word lines 44 through 63. A pass voltage (Vpass) of about 8V is applied to the memory cells in the first region. A pass voltage of about 9V is applied to the memory cells in the second region and a pass voltage of about 10V is applied to the memory cells in the third region.

With these working assumptions, an exemplary method of applying a pass voltage to memory cells of a cell string according to an embodiment of the inventive concept will be described with reference to fig. 13 to 15.

Fig. 13 is a diagram illustrating a program voltage and an application of a pass voltage according to another embodiment of the inventive concept. Referring to fig. 13, the memory cell array 111 of fig. 1 includes a plurality of cell strings, only one of which is shown in fig. 13 as an example.

A program voltage (Vpgm) is applied to the selected word line. A constant pass voltage (constant Vpass) is applied to the word line adjacent to the selected word line. The dynamic pass voltage (dynamic Vpass) is applied to the other unselected word lines in each of the first through third regions (region 1 through region 3). The dynamic pass voltage may be the same as the dynamic pass voltage described with respect to fig. 12. For example, when the word line of region 1 is selected, the nearest neighbor word line receives 8V, the other word lines of region 1 receive 8V, the word line of region 2 receives 9V, and the word line of region 3 receives 10V. When the word line of region 2 is selected, the nearest neighbor word line receives 8V, the other word lines of region 2 receive 9V, the word line of region 1 receives 8V, and the word line of region 3 receives 10V. When the word line of region 3 is selected, the nearest neighbor word line receives 8V, the other word lines of region 3 receive 10V, the word line of region 1 receives 8V, and the word line of region 2 receives 9V. The pass voltages as applied throughout the various regions will be described in some additional detail with reference to fig. 14.

Fig. 14 is a graph illustrating a pass voltage applied in an embodiment of the inventive concept illustrated in fig. 13.

Referring to fig. 14, the horizontal axis of the graph indicates the locations of word lines within the cell string (WL 0 and WL63 are assumed to be the outermost (or top and bottom) word lines of the cell string), and the vertical axis of the graph is the level of pass voltage (Vpass). The indicated levels "a" and "B" of the pass voltages are applied to the memory cells connected to the unselected word lines. The "a" level pass voltage or constant pass voltage (constant Vpass) is applied to memory cells adjacent to the selected memory cell receiving the program voltage (Vpgm). The "B" level pass voltage Vpass or dynamic pass voltage is applied to all other unselected memory cells.

A constant pass voltage is applied to memory cells adjacent to the selected memory cell and maintained constant regardless of the locations of the memory cells within the first through third regions. In contrast, the pass voltages applied to the other unselected memory cells gradually increase from the first (or lower) region (region 1) to the third (or upper) region (region 3), and the second (or middle) region receives a pass voltage between the lower pass voltage applied to the first region and the higher pass voltage applied to the third region. For example, in a specific embodiment of the inventive concept, the pass voltage (Vpass) is about 8V for the first region, about 9V for the second region, and about 10V for the third region.

That is, as the programming operation proceeds from the first word line (e.g., word line 0) to the last word line (e.g., word line 63), the pass voltage applied to the memory cells adjacent to the selected word line is maintained at about 8V. However, a variable pass voltage is applied across multiple regions to non-adjacent unselected word lines. Accordingly, a constant pass voltage is applied to memory cells adjacent to the memory cells receiving the program voltage to prevent over-programming due to fluctuation of the pass voltage. The result of the programming operation according to the illustrated embodiment is further described in fig. 18.

Hereinafter, a method of applying a pass voltage according to an embodiment of the inventive concept will be described in some supplementary detail with reference to the flowchart of fig. 15. Fig. 15 is a flowchart summarizing a method of applying the pass voltage of fig. 13.

Referring to fig. 1 and 15 together, the control logic 115 determines whether the selected word line WL belongs to the first region (s11=yes), or whether the selected word line WL belongs to the second region (s11=no, and s13=yes), or whether the selected word line WL belongs to the third region (s11=no, and s13=no).

If the selected word line belongs to the first region, the voltage generator 114 applies a dynamic pass voltage according to the first region and applies a constant pass voltage to the word lines WL-1 and wl+1 adjacent to the selected Word Line (WL) (S12).

And if the selected word line belongs to the second region, the voltage generator 114 applies a dynamic pass voltage according to the second region and applies a constant pass voltage to the word lines WL-1 and wl+1 adjacent to the selected Word Line (WL) (S14).

And if the selected word line belongs to the third region, the voltage generator 114 applies a dynamic pass voltage according to the third region and applies a constant pass voltage to the word lines WL-1 and wl+1 adjacent to the selected Word Line (WL) (S15).

Then, the voltage generator 114 applies a program voltage (Vpgm) to the selected word line WL, and the control logic 115 performs a program operation (S16).

The pass voltage applied to the unselected word lines adjacent to the selected word line is always maintained constant for the programming operation. Accordingly, an influence due to fluctuation of a pass voltage applied to an unselected word line adjacent to a selected word line can be offset for a program operation, thereby improving over-programming.

Fig. 16 is a graph illustrating a program voltage according to another embodiment of the inventive concept.

Referring to fig. 16, the horizontal axis of the graph indicates the word line position within the cell string, and the vertical axis of the graph is the level of the program start voltage. The first program start voltage "a" is a start voltage of a program voltage that normally increases according to a defined ISPP. The second program start voltage "B" is a start voltage of a program voltage increased according to an embodiment of the inventive concept. That is, when the pass voltage Vpass fluctuates, the increased width of the second program start voltage "B" is controlled at the control iteration.

For example, assume again that the cell string is accessed by 64 word lines arranged in a first region including word lines 0 through 19, a second region including word lines 20 through 43, and a third region including word lines 44 through 63. As will be appreciated by those skilled in the art, this is just one example. As shown in fig. 18, the dynamic pass voltage (dynamic Vpass) is about 8V in the first region (region 1), about 9V in the second region (region 2), and about 10V in the third region (region 3).

In embodiments of the inventive concept that use different program start voltages for each memory cell region, a first start voltage of about 15V may be used.

Since the pass voltage of the second region fluctuates during programming of the memory cells connected to the word lines in the second region, the potential of the memory cells connected to the selected word line is raised by parasitic capacitance. Thus, the program start voltage may be adjusted to a different second start voltage in the second region. For example, the second start voltage may be reduced by the first start voltage by the voltage potential raised by the parasitic capacitance.

Similarly, since the pass voltage of the third region fluctuates during programming of the memory cells connected to the word lines in the third region, the potential of the memory cells connected to the selected word line is raised by parasitic capacitance. Thus, the third program start voltage may be adjusted for the third region (region 3). For example, the third start voltage may decrease the voltage potential raised by the parasitic capacitance from the second start voltage. The result of the program operation according to the program start voltage described in fig. 16 will be shown in fig. 18.

In addition, a method of applying a program voltage according to an embodiment will be described in detail with reference to a flowchart in fig. 17. Fig. 17 is a flowchart summarizing a method of applying the program voltage of fig. 16.

Referring to fig. 1, 16 and 17, the control logic 115 determines whether the selected word line WL belongs to the first area (S21). If so, operation S22 is performed. If not, operation S23 is performed.

The voltage generator 114 applies a dynamic pass voltage according to the first region (region 1) to the word line of the first region (S22). The voltage generator 114 starts to be applied to the selected word line WL according to the program start voltage Vpgm of the first region.

In addition, the control logic 115 determines whether the selected word line WL belongs to the second area (S23). If so, operation S24 is performed. If not, operation 25 is performed.

The voltage generator 114 applies a dynamic pass voltage according to the second region to the word line of the second region (S24). The voltage generator 114 starts to be applied to the selected word line WL according to the program start voltage Vpgm of the second region.

The voltage generator 114 applies a dynamic pass voltage according to the third region (region 3) to the word line of the third region (S25). The voltage generator 114 applies a program start voltage according to the third region to the selected word line.

The pass voltage applied to the unselected word lines adjacent to the selected word line is always maintained constant for the programming operation. Accordingly, an influence due to fluctuation of a pass voltage applied to an unselected word line adjacent to a selected word line can be canceled for a program operation, thereby reducing the occurrence of over-programming.

Fig. 18 is a graph showing the result of a program operation using the program voltages of fig. 14 and 16.

As shown in fig. 12, a pass voltage of about 8V is applied to the memory cells of the word lines in the first region. A pass voltage of about 9V is applied to the memory cells of the word line in the second region. A pass voltage of about 10V is applied to the memory cells of the word line in the third region.

As shown in fig. 18, when performing the programming operation according to the methods of fig. 14 and 16, all the memory cells in the first through third regions may be programmed to be within a target threshold voltage (target Vth).

Fig. 19 is a diagram showing another example of applying a voltage to a cell string. Referring to fig. 19, a program voltage Vpgm may be applied to "intermediate memory cells". The dynamic pass voltage dynamic Vpass may be applied to word lines of other memory cells.

For example, the first dynamic pass voltage DYANMIC VPASS may be applied to a word line of a memory cell (directly) adjacent to the memory cell to which the program voltage Vpgm is applied. The second dynamic pass voltage dynamic Vpass2 may be applied to the word lines of the remaining memory cells.

To reduce the effect of parasitic capacitance of adjacent memory cells, the increment of the first dynamic pass voltage dynamic Vpass1 may be smaller than the increment of the second dynamic pass voltage dynamic Vpass 2. In an embodiment, the first dynamic pass voltage dynamic Vpass1 applied to memory cells adjacent above/on (e.g., a String Selection Line (SSL) side) the memory cells to which the program voltage Vpgm is applied and the first dynamic pass voltage dynamic Vpass1 applied to memory cells adjacent below (e.g., a Ground Selection Line (GSL) side) the memory cells to which the program voltage Vpgm is applied may be the same as or different from each other.

In an embodiment, the point at which the first dynamic pass voltage dynamic Vpass1 increases may be different from or the same as the point at which the second dynamic pass voltage dynamic Vpass2 increases.

Fig. 20 is a timing diagram illustrating an example of applying the program voltage Vpgm, the first dynamic pass voltage dynamic Vpass1, and the second dynamic pass voltage dynamic Vpass2 of fig. 19. As described with reference to fig. 9, the program voltage Vpgm may be gradually increased from a start voltage Vpgm of about 15V to a stop voltage Vpgm of about 25V.

The first dynamic pass voltage dynamic Vpass1 may increase from 8V to 8.5V at the first point T1. In contrast, the second dynamic pass voltage dynamic Vpass2 may increase from 8V to 9V at the first point T1. The first dynamic pass voltage dynamic Vpass1 may increase from 8.5V to 9V at the second point T2. In contrast, the second dynamic pass voltage dynamic Vpass2 may increase from 9V to 10V at the second point T2.

At a control iteration of the first point T1 and the second point T2 where the first dynamic pass voltage dynamic Vpass1 or the second dynamic pass voltage dynamic Vpass2 increases, the program voltage Vpgm may increase by about 0.2V. At the remaining iterations except for the control iteration, the program voltage Vpgm may be increased by about 0.3V. The effect of parasitic capacitance can be offset by adjusting the increment of the program voltage Vpgm of the control iteration to be smaller than the increment of the program voltage Vpgm of the remaining iterations.

In an embodiment, if the increment of the first dynamic pass voltage dynamic Vpass1 is smaller than the increment of the second dynamic pass voltage dynamic Vpass2, the influence of parasitic capacitance of the first dynamic pass voltage dynamic Vpass1 may be reduced. Accordingly, the influence of the parasitic capacitance of the first dynamic pass voltage dynamic Vpass1 may be ignored, and the control iteration may be omitted. That is, the program voltage Vpgm may be increased by the same increment (e.g., 0.3V) at each iteration from the start voltage to the stop voltage.

The timing described as the increase of the first dynamic pass voltage dynamic Vpass1 and the second dynamic pass voltage dynamic Vpass2 given in fig. 20 are identical to each other. However, the timings of the first dynamic pass voltage dynamic Vpass1 and the second dynamic pass voltage dynamic Vpass2 may be differently set.

Fig. 21 is a diagram showing an example of a time when the program voltage Vpgm is applied. At the first time T1 of fig. 21, the time for applying the program voltage Vpgm may be increased as compared to the first point T1 of fig. 9. Since the application time of the program voltage Vpgm increases, the dynamic pass voltage dynamic Vpass may be increased.

For example, the dynamic pass voltage dynamic Vpass is increased by 1V at the first point T1 of fig. 9. In contrast, the dynamic pass voltage dynamic Vpass is increased by 2V at the first point T1 of fig. 21. That is, since the application time of the program voltage Vpgm increases, the dynamic pass voltage dynamic Vpass may further increase based on the increase of the application time in addition to the original increment.

Fig. 22 is a diagram showing another example of a time when the program voltage Vpgm is applied. The application time of the program voltage Vpgm may be increased at the second point T2 as compared to the application time of fig. 21. For example, when the program voltage Vpgm increases from the start voltage to the stop voltage, the application time of the program voltage Vpgm may increase at the last point of adjusting the dynamic pass voltage.

Because the application time of the program voltage Vpgm increases at the second point T2, the dynamic pass voltage dynamic Vpass may increase from 9V to 11V. For example, the dynamic pass voltage dynamic Vpass may be further increased based on an increase in the application time in addition to the original delta.

The application time, depicted in fig. 21 and 22 as the program voltage Vpgm, increases at the control iteration. However, the application time of the program voltage Vpgm may increase at a timing that does not overlap with the control iteration. At the control iteration, the dynamic pass voltage dynamic Vpass may increase at a timing at which the application time of the program voltage Vpgm increases.

In an embodiment, the application time of the program voltage Vpgm may increase in the last program loop. The reliability of data stored in slow cells whose programming speed is slow can be further improved by increasing the application time of the program voltage Vpgm in the last program loop.

The application time described as the program voltage Vpgm given in fig. 21 and 22 increases when a program operation is performed. However, the application time of the program voltage Vpgm may be reduced when a program operation is performed. The dynamic pass voltage dynamic Vpass may be lowered if the application time of the program voltage Vpgm is reduced.

As described with reference to fig. 10 or 13, the constant pass voltage constant Vpass may be applied to memory cells adjacent to the memory cells to which the program voltage Vpgm is applied. In this case, the control iteration at the increment of the adjustment program voltage Vpgm may be omitted.

If the control iteration is omitted, the dynamic pass voltage dynamic Vpass may be increased at a preset point and as the application time of the program voltage Vpgm increases.

As described with reference to fig. 19 and 20, the dynamic pass voltage dynamic Vpass (e.g., the first dynamic pass voltage dynamic Vpass 1) applied to the word lines of the adjacent memory cells may have an increment or an increase point that is different from the dynamic pass voltage dynamic Vpass (e.g., the second dynamic pass voltage dynamic Vpass 2) applied to the word lines of the other memory cells. The first dynamic pass voltage dynamic Vpass1 and the second dynamic pass voltage dynamic Vpass2 may increase at a preset point (e.g., a control iteration) and as the application time of the program voltage Vpgm increases.

For example, in order to reduce the influence of parasitic capacitance, the increment of the first dynamic pass voltage dynamic Vpass1 may be the same as or smaller than the increment of the second dynamic pass voltage dynamic Vpass 2.

Fig. 23 is a diagram showing another example of applying a voltage to a cell string. Referring to fig. 23, a program voltage Vpgm may be applied to "intermediate memory cells". The dynamic pass voltage dynamic Vpass may be applied to word lines of other memory cells.

For example, the third dynamic pass voltage dynamic Vpass3 may be applied to the word line of at least one memory cell located at an edge of an upper portion of the cell string (e.g., a String Select Line (SSL) side) and the word line of at least one memory cell located at an edge of a lower portion of the cell string (e.g., a Ground Select Line (GSL) side). The second dynamic pass voltage dynamic Vpass2 may be applied to the word lines of the remaining memory cells.

The increment of the third dynamic pass voltage dynamic Vpass3 may be different from the increment of the second dynamic pass voltage dynamic Vpass 2. For example, as described with reference to fig. 19 and 20, the increment of the third dynamic pass voltage dynamic Vpass3 may be smaller than the increment of the second dynamic pass voltage dynamic Vpass 2.

In an embodiment, a first dynamic pass voltage dynamic Vpass1 applied to memory cells adjacent above/on (e.g., a String Selection Line (SSL) side) the memory cells to which the program voltage Vpgm is applied and a second dynamic pass voltage dynamic Vpass2 applied to memory cells adjacent below (e.g., a Ground Selection Line (GSL) side) the memory cells to which the program voltage Vpgm is supplied may be the same as or different from each other.

In an embodiment, the point at which the second dynamic pass voltage dynamic Vpass2 increases may be different from or the same as the point at which the third dynamic pass voltage dynamic Vpass3 increases.

As described with reference to fig. 10 or 13, the constant pass voltage constant Vpass may be applied to memory cells adjacent to the memory cells to which the program voltage Vpgm is applied.

As described with reference to fig. 19 and 20, the second dynamic pass voltage dynamic Vpass2 applied to the word lines of the adjacent memory cells may have an increment or an increase point, which is different from the second dynamic pass voltage dynamic Vpass2 applied to the word lines of the other memory cells.

As described with reference to fig. 21 and 22, the application time of the program voltage Vpgm may be increased when a program operation is performed. As the application time of the program voltage Vpgm increases, a dynamic pass voltage (e.g., dynamic Vpass1, dynamic Vpass2, or dynamic Vpass 3) may be increased.

Fig. 24 is a timing diagram illustrating an example of applying the second dynamic pass voltage dynamic Vpass2 and the third dynamic pass voltage dynamic Vpass3 of fig. 23. Referring to fig. 24, the point at which the second dynamic pass voltage dynamic Vpass2 is applied may be the same as the point at which the third dynamic pass voltage dynamic Vpass3 is applied, but is not limited thereto.

For example, the third dynamic pass voltage dynamic Vpass3 may be controlled (or increased) after or before the second dynamic pass voltage dynamic Vpass2 is controlled (or increased). The increment of the third dynamic pass voltage dynamic Vpass3 may be smaller or larger than the increment of the second dynamic pass voltage dynamic Vpass 2.

Fig. 25 is a diagram showing an example of one memory block BLK1 among memory blocks of the memory cell array 111 of fig. 1. Referring to fig. 25, a plurality of cell strings CS may be disposed on a substrate SUB in rows and columns. The plurality of cell strings CS may be commonly connected to a common source line CSL formed on (or in) the substrate SUB. In fig. 25, an exemplary position of the substrate SUB is shown to help understand the structure of the memory block BLK 1.

An example shown in fig. 25 is that the common source line CSL is connected to the lower end of the cell string CS. However, it is sufficient that the common source line CSL is electrically connected to the lower end of the cell string CS, and the inventive concept is not limited to the case where the common source line CSL is physically located at the lower end of the cell string CS. The example shown in fig. 25 is that the cell strings CS are arranged in a matrix of four by four. However, the memory block BLK1 may include fewer or more cell strings CS.

The cell strings CS of each row may be commonly connected to the ground selection line GSL and to a corresponding one of the first to fourth string selection lines SSL1 to SSL 4. The cell string CS of each column may be connected to a corresponding bit line of the first to fourth bit lines BL1 to BL 4. For ease of explanation, the cell strings CS connected to the second string selection line SSL2 and the third string selection line SSL3 are depicted as blurred.

Each cell string CS may include at least one ground selection transistor GST connected to the ground selection line GSL, first to fourth dummy memory cells DMC1 connected to the first to fourth dummy word lines WL1 to WL4, first to fourth memory cells MC1 to MC4 connected to the first to fourth word lines WL1 to WL4, respectively, second and third dummy memory cells DMC2 and DMC3 connected to the second and third dummy word lines DWL2 and DWL3, respectively, fifth to eighth memory cells MC5 to MC8 connected to the fifth to eighth word lines WL5 to WL8, respectively, fourth dummy memory cells DMC4 connected to the fourth dummy word line DWL4, and string selection transistors SST connected to the string selection lines SSL1, SSL2, SSL3 or SSL4, respectively.

In each cell string CS, the ground selection transistor GST, the first dummy memory cell DMC1, the first to fourth memory cells MC1 to MC4, the second and third dummy memory cells DMC2 and DMC3, the fifth to eighth memory cells MC5 to MC8, the fourth dummy memory cell DMC4, and the string selection transistor SST may be connected in series in a direction perpendicular to the substrate SUB and may be sequentially stacked in a direction perpendicular to the substrate SUB.

The example shown in fig. 25 is that eight memory cells MC1 to MC8 and four dummy memory cells DMC1 to DMC4 are arranged in each cell string CS. However, the inventive concept is not limited thereto. As described with reference to fig. 2, 10 and 13, the number of memory cells of each cell string CS may be less than 8 or may be greater than 8. In addition, the number of dummy memory cells per cell string CS may be less than 4 or may be greater than 4.

The dummy memory cells DMC1 through DMC4 may have the same structure as the memory cells MC1 through MC 8. The dummy memory cells DMC 1-DMC 4 may not be programmed (e.g., may be program inhibited) or may be programmed differently than the memory cells MC 1-MC 8.

For example, the memory cells MC1 through MC8 may be programmed to have various threshold voltages according to data, and the dummy memory cells DMC1 through DMC4 may be programmed to have threshold voltages within a specific range. As in the dummy memory cells DMC1 through DMC4, the string selection transistor SST and the ground selection transistor GST may not be programmed or may be programmed to have a threshold voltage within a specific range.

In an embodiment, memory cells at the same height and associated with one string select line SSL1, SSL2, SSL3, or SSL4 may form one physical page. Memory cells of one physical page may be connected to one sub-word line. Sub-word lines of a physical page located at the same height may be commonly connected to one word line.

In an embodiment, sub-word lines of a physical page at the same height may be connected to each other at a height where the sub-word lines are formed. In another embodiment, sub-word lines of a physical page at the same height may be indirectly connected to each other at a layer (such as a metal layer) different from the height at which the sub-word lines are formed.

The memory block BLK1 may be set as a 3D memory array. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells MC having active regions disposed above a silicon substrate and circuitry related to the operation of these memory cells MC. Circuitry related to the operation of memory cell MC may be located above or within such a substrate. The term "monolithic" means that each horizontal layer of the array is deposited directly on the horizontal layer below each of the 3D memory arrays.

In embodiments of the inventive concept, the 3D memory array includes a vertical cell string CS (or NAND string) positioned vertically such that at least one memory cell is located above another memory cell. At least one memory cell may include a charge trapping layer. Each cell string may further include at least one selection transistor located above the memory cell MC. The at least one selection transistor may have the same structure as the memory cell MC and may be formed in correspondence with the memory cell MC.

The following patent documents, incorporated herein by reference, describe suitable configurations for three-dimensional memory arrays in which the three-dimensional memory array is configured with a plurality of levels of word lines and/or bit lines shared between the levels: U.S. patent No. 7,679,133, U.S. patent No. 8,553,466, U.S. patent No. 8,654,587, U.S. patent No. 8,559,235, and U.S. patent publication No. 2011/023648.

In an embodiment, the first to fourth memory cells MC1 to MC4 may constitute a first sub-block, and the fifth to eighth memory cells MC5 to MC8 may constitute a second sub-block. The first sub-block and the second sub-block may be independently erased. For example, when the first SUB-block is erased, an erase voltage is supplied from the substrate SUB to the channel of the cell string CS. A low voltage similar to the ground voltage may be applied to the first to fourth word lines WL1 to WL4 of the first sub-block, and the first to fourth memory cells MC1 to MC4 may be erased.

The fifth word lines WL5 to WL8 of the second sub-block may be floated, and the second sub-block may not be erased. The dummy word lines DWL1 to DWL4, the ground selection line GSL, and the string selection line SSL, which are not targeted for the erase operation, connected to the dummy memory cells DMC1 to DMC4, the ground selection transistor GST, and the string selection transistor SST may also be floated.

Fig. 26 is a diagram showing an example in which a voltage is applied to a cell string having the structure described with reference to fig. 25. Referring to fig. 26, a program voltage Vpgm may be applied to a "specific memory cell". The dynamic pass voltage dynamic Vpass may be applied to word lines of other memory cells.

As described with reference to fig. 25, the first to fourth dummy memory cells DMC1 to DMC4 may be provided in a cell string. Dynamic dummy pass voltage dynamics Vdpass may be applied to the dummy word lines DWL1 to DWL4 of the first to fourth dummy memory cells DMC1 to DMC 4.

In an embodiment, the dynamic dummy pass voltage dynamics Vdpass may be controlled according to the same increment as the dynamic pass voltage dynamics Vpass. For example, when the dynamic pass voltage dynamic Vpass increases by 1V, the dynamic dummy pass voltage dynamic Vdpass may also increase by 1V.

In another embodiment, the dynamic dummy pass voltage dynamic Vdpass may be controlled according to a different increment than the dynamic pass voltage dynamic Vpass. Dynamic dummy pass voltage dynamic Vdpass may be controlled by using an increment that is less than or greater than the increment of dynamic pass voltage dynamic Vpass. For example, when the dynamic pass voltage dynamic Vpass increases by 1V, the dynamic dummy pass voltage dynamic Vdpass may increase by 0.5V or 1.5V.

The dynamic dummy pass voltage dynamic Vdpass may have the same increment or the same increase point as the dynamic pass voltage dynamic Vpass. Dynamic dummy pass voltage dynamic Vdpass may have a different increment or a different point of increase than dynamic pass voltage dynamic Vpass.

The dynamic dummy pass voltage dynamics Vdpass applied to the dummy memory cells DMC 1-DMC 4 may be the same as or different from each other. The increment or increase point of the dynamic dummy pass voltage dynamics Vdpass applied to the dummy memory cells DMC 1-DMC 4 may be the same or different from each other.

Fig. 27 is a diagram showing another example of applying a voltage to a cell string having the structure described with reference to fig. 25. Referring to fig. 27, a program voltage Vpgm may be applied to a "specific memory cell". As described with reference to fig. 10 or 13, in order to offset the influence of parasitic capacitance, a pass voltage constant Vpass having a constant voltage level may be applied to a word line (or word lines) of a memory cell (or memory cells) adjacent to a memory cell receiving a program voltage Vpgm. The dynamic pass voltage dynamic Vpass may be applied to other memory cells.

As described with reference to fig. 10, in order to offset the effect of parasitic capacitance, a dummy pass voltage constant Vdpass having a constant voltage level may be applied to a dummy word line of a dummy memory cell adjacent to a memory cell receiving the program voltage Vpgm. Dynamic dummy pass voltage dynamic Vdpass may be applied to other dummy memory cells. When the dummy memory cell is not adjacent to a memory cell receiving the program voltage Vpgm, the dynamic dummy pass voltage dynamic Vdpass may be applied to all the dummy word lines of the dummy memory cell.

As described with reference to fig. 21 and 22, the application time of the program voltage Vpgm may be increased when a program operation is performed. As the application time of the program voltage Vpgm increases, the dynamic pass voltage dynamic Vpass or the dynamic dummy pass voltage dynamic Vdpass may be increased.

As described with reference to fig. 23, the dynamic pass voltage dynamic Vpass applied to the word line of the memory cell located at the edge among the memory cells (e.g., the word line applied to the memory cell not adjacent to the memory cell applied with the program voltage Vpgm among WL1 and WL8 of fig. 25) may have a different increment or a different increase point than the dynamic pass voltage dynamic Vpass applied to the other word line (e.g., the word line applied to the memory cell not adjacent to the memory cell applied with the program voltage Vpgm among WL2 to WL7 of fig. 25).

The dynamic dummy pass voltage dynamics Vdpass applied to the dummy word line located at the edge (e.g., the dummy word line applied to the dummy memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among DWL1 and DWL4 of fig. 25) may have a different increment or a different increase point than the dynamic dummy pass voltage dynamics Vdpass applied to the other dummy word lines (e.g., the dummy word line applied to the dummy memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among DWL2 and DWL3 of fig. 25).

Fig. 28 is a diagram showing another example of applying a voltage to a cell string having the structure described with reference to fig. 25. Referring to fig. 28, as described with reference to fig. 19 and 20, the first dynamic pass voltage dynamic Vpass1 having a different increment or a different increase point from the second dynamic pass voltage dynamic Vpass2 may be applied to a word line (or word lines) of a memory cell (or memory cells) adjacent to a memory cell receiving the program voltage Vpgm. For example, the increment or the increase point of the first dynamic pass voltage dynamic Vpass1 and the second dynamic pass voltage dynamic Vpass2 may be the same or different from each other.

In addition, as described with reference to fig. 19 and 20, the first dynamic dummy pass voltage dynamic Vdpass1 having a different increment or different point of increase than the second dynamic dummy pass voltage dynamic Vdpass may be applied to the dummy word line of an adjacent dummy memory cell. For example, the increment or point of increase of the first dynamic dummy pass voltage dynamic Vdpass and the second dynamic dummy pass voltage dynamic Vdpass may be the same or different from each other.

As described with reference to fig. 21 and 22, the application time of the program voltage Vpgm may be increased when a program operation is performed. As the application time of the program voltage Vpgm increases, the dynamic pass voltage dynamic Vpass1 or dynamic Vpass2 or dynamic dummy pass voltage dynamic Vdpass or dynamic Vdpass may be increased.

As described with reference to fig. 23, the second dynamic pass voltage dynamic Vpass2 applied to the word line of the memory cell located at the edge among the memory cells (e.g., the word line applied to the memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among WL1 and WL8 of fig. 25) may have a different increment or a different increase point than the second dynamic pass voltage dynamic Vpass2 applied to the other word line (e.g., the word line applied to the memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among WL2 to WL7 of fig. 25).

The second dynamic dummy pass voltage dynamic Vdpass applied to the dummy word line located at the edge (e.g., the dummy word line applied to the dummy memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among DWL1 and DWL4 of fig. 25) may have a different increment or a different increase point than the second dynamic dummy pass voltage dynamic Vdpass2 applied to the other dummy word lines (e.g., the dummy word line applied to the dummy memory cell not adjacent to the memory cell to which the program voltage Vpgm is applied among DWL2 and DWL3 of fig. 25).

Fig. 29 is a diagram showing an example of another memory block BLK2 among the memory blocks of the memory cell array 111 of fig. 1. In comparison with the memory block BLK1 of fig. 25, in the memory block BLK2 of fig. 29, a ground selection transistor GST, a first dummy memory cell DMC1, first to fourth memory cells MC1 to MC4, a switch SW, fifth to eighth memory cells MC5 to MC8, a fourth dummy memory cell DMC4, and a string selection transistor SST may be provided in each cell string CS.

The switches SW of the cell strings CS may be commonly controlled through the select lines SL. The switch SW may connect the channel of the first sub-block and the channel of the second sub-block. The switch SW may not have a charge storage layer and thus is not programmed or erased. A switching voltage for controlling the switch SW may be applied to the select line SL.

For example, the switching voltage may be a constant voltage. As described with reference to fig. 1 to 28, the switching voltage may be a dynamic voltage controlled in the same manner as the dynamic pass voltage dynamic Vpass or the dynamic dummy pass voltage dynamic Vdpass.

Fig. 30 is a diagram showing an example of another memory block BLK3 among memory blocks of the memory cell array of fig. 1. In comparison with the memory block BLK1 of fig. 25, in the first sub-block of the memory block BLK3 of fig. 30, the first string selection transistor SST1 is disposed above/on the second dummy memory cell DMC2 of each cell string CS. The first string selection transistor SST1 is connected to an associated first string selection line SSL1.

In each cell string CS of the second sub-block, a second string selection transistor SST2 is disposed above/on the fourth dummy memory cell DMC 4. The second string selection transistor SST2 is connected to an associated second string selection line SSL2. That is, a string selection transistor may be provided in each sub-block.

Fig. 31 is a diagram showing an example of another memory block BLK4 among memory blocks of the memory cell array 111 of fig. 1. The second sub-block of the memory block BLK4 of fig. 31 may have a structure in which the second sub-block of the memory block BLK3 of fig. 30 is inverted in a direction perpendicular to the substrate.

In each cell string CS, a second string selection transistor SST2 may be disposed at the lowermost end of the second sub-block. In the second sub-block of each cell string CS, the second string selection transistor SST2, the fourth dummy memory cell DMC4, the fifth through eighth memory cells MC5 through MC8, the third dummy memory cell DMC3, and the second ground selection transistor GST2 may be sequentially stacked in a direction perpendicular to the substrate.

A bit line (one of BL1 to BL 4) may be connected between the first string selection transistor SST1 and the second string selection transistor SST2 of each cell string. The first ground selection transistor GST1 may be connected to the common source line CSL, and the second ground selection transistor GST2 may be connected to the source line SL.

FIG. 32 is a block diagram illustrating a computing system according to an embodiment.

Referring to fig. 32, the computing system 200 includes a central processing unit 220 electrically connected to a bus 210, a user interface 230, a modem 240, such as a baseband chipset, a memory controller 250, and a memory device 260. The memory controller 250 controls the memory device 260. The memory device 260 stores N-bit data processed or to be processed by the central processing unit 220 through the memory controller 250, where N is a positive integer.

When the computing system 200 is a mobile device, a battery 270 for supplying power to the computing system may additionally be provided. Although not shown in the figures, it will be apparent to those skilled in the art that an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further provided in the computing system 200.

As a preferred example, the memory device 260 may include the flash memory devices of fig. 1-18. Additionally, the memory controller 250 may include a flash memory controller that controls the flash memory device.

For example, memory device 260 and memory controller 250 may include a Solid State Drive (SSD) that uses non-volatile memory to store data. In addition, memory device 260 and memory controller 250 may include memory cards that use non-volatile memory to store data.

Fig. 33 is a block diagram illustrating a memory-based storage device according to an embodiment.

Referring to fig. 33, a memory-based storage system 300 includes a memory-based storage device 310 and a host 320 connected thereto. The memory-based storage device 310 may include a memory 311 and a memory controller 312 that controls the memory 311.

For example, the memory-based storage device 310 may be a flash memory card such as an SD card. In addition, the memory-based storage device 310 may include a SIM card or a USIM card. That is, the memory-based storage device 310 may be a card that meets certain industry standards for use of electronic devices such as digital cameras and personal computers.

As a preferred example, the memory 311 may include the flash memory device described in fig. 1 to 16. Additionally, the memory controller 312 may include a flash memory controller that controls the flash memory device.

The present disclosure describes dynamic changes in voltage as a function of time. In addition, the present disclosure describes dynamic changes in voltage as a function of location (e.g., area) and type of memory cell (e.g., memory cell or dummy memory cell). According to an embodiment, fluctuations of the program voltage Vpgm, which are affected by parasitic capacitance, may be cancelled out.

According to an embodiment, the pass voltage window may be improved by preventing over programming.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present inventive concepts. Thus, to the maximum extent allowed by law, the scope of the present inventive concept is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A non-volatile memory device, the non-volatile memory device comprising:

A memory cell array including a plurality of memory cells arranged in word lines and bit lines;

a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines, a first pass voltage applied to a first unselected word line adjacent to the selected word line among the word lines, and a second pass voltage applied to a second unselected word line not adjacent to the selected word line among the word lines; and

Control logic configured to iteratively increase the level of the programming voltage pulse and to differently increase the first pass voltage and the second pass voltage in accordance with the iteration of the increase of the programming voltage pulse,

Wherein the increment of the second pass voltage is larger than the increment of the first pass voltage.

2. The non-volatile memory device of claim 1, wherein the first pass voltage increases to the first predetermined level after being maintained at a constant level during a first predetermined number of cycles of the programming voltage pulse.

3. The non-volatile memory device of claim 2, wherein the control logic increases the first pass voltage at a first point in the increased iteration of the programming voltage pulse and increases the second pass voltage at a second point in the increased iteration of the programming voltage pulse that is different from the first point.

4. The non-volatile memory device of claim 1, wherein the control logic is further configured to increase the programming voltage pulse in accordance with a fluctuation of the first pass voltage.

5. The non-volatile memory device of claim 1, wherein the control logic increases the application time of the programming voltage pulse at a first point in an increasing iteration of the programming voltage pulse.

6. The non-volatile memory device of claim 5, wherein the control logic increases the first pass voltage and the second pass voltage at a first point in accordance with an increase in the application time of the program voltage pulse.

7. The non-volatile memory device of claim 1, wherein the voltage generator further generates a third pass voltage applied to an edge word line among the word lines, the control logic increasing the third pass voltage differently than the second pass voltage.

8. The non-volatile memory device of claim 1, wherein the control logic adjusts a first level of a first pass voltage applied to a first unselected word line between the selected word line and the string select line and a second level of a first pass voltage applied to a first unselected word line between the selected word line and the ground select line differently among unselected word lines adjacent to the selected word line.

9. A non-volatile memory device, the non-volatile memory device comprising:

A voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines and a pass voltage applied to an unselected word line; and

Control logic configured to iteratively increase the programming voltage pulse and adjust the pass voltage in accordance with the iteration of the increase of the programming voltage pulse,

Wherein the control logic is further configured to increase the application time of the programming voltage pulse at a first point in the iteration of the increase in the programming voltage pulse and increase the pass voltage applied to the at least one unselected word line at the first point in accordance with the increase in the application time of the programming voltage pulse.

10. The non-volatile memory device of claim 9, wherein the pass voltage applied to an unselected word line adjacent to the selected word line is a constant pass voltage.

11. The non-volatile memory device of claim 9, wherein the pass voltage applied to an edge word line among the word lines is a second pass voltage, the control logic increasing the second pass voltage differently than other pass voltages.

12. A non-volatile memory device, the non-volatile memory device comprising:

a voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines, a first pass voltage applied to at least one unselected non-edge word line, and a second pass voltage applied to the unselected edge word line; and

Control logic configured to iteratively increase the programming voltage pulses during a programming operation,

Wherein the control logic is further configured to increase the first pass voltage and the second pass voltage differently according to an iteration of the increase of the programming voltage pulse.

13. The non-volatile memory device of claim 12, wherein the voltage generator further generates a constant pass voltage applied to unselected word lines adjacent to the selected word line.

14. The non-volatile memory device of claim 12, wherein the control logic increases the first pass voltage and the second pass voltage at different points among iterations of the increase in the programming voltage pulse.

15. A non-volatile memory device, the non-volatile memory device comprising:

A memory cell array including a plurality of memory blocks, each memory block including a plurality of cell strings, each cell string including a first memory cell, a dummy memory cell, and a second memory cell sequentially stacked on a substrate in a direction perpendicular to the substrate, the first memory cell and the second memory cell being connected to a word line;

A voltage generator configured to generate a program voltage pulse applied to a selected word line among the word lines, a pass voltage applied to an unselected word line, and a dummy pass voltage applied to a dummy word line; and

Control logic configured to control the voltage generator to iteratively increase the programming voltage pulses in increments during a programming operation,

Wherein the control logic is further configured to adjust the pass voltage and the dummy pass voltage differently in accordance with an increase in the programming voltage pulse.

16. The non-volatile memory device of claim 15, wherein the control logic fixes the dummy pass voltage at a constant level during an increasing iteration of the programming voltage pulse when the dummy word line is adjacent to the selected word line.

17. The non-volatile memory device of claim 15, wherein when the dummy word line is not adjacent to the selected word line, the control logic increases the dummy pass voltage by a first increment at a first point in the increased iteration of the programming voltage pulse,

When the dummy word line is adjacent to the selected word line, the control logic increases the dummy pass voltage by a second increment at a second point in the increased iteration of the programming voltage pulse.

18. The non-volatile memory device of claim 15, wherein each cell string further comprises a second dummy memory cell located below the first memory cell and a third dummy memory cell located above the second memory cell,

The voltage generator also generates a second dummy pass voltage applied to one of the second dummy memory cell and the third dummy memory cell,

The control logic adjusts the second dummy pass voltage differently than the dummy pass voltage.

19. The non-volatile memory device of claim 15, wherein the control logic is further configured to increase the application time of the programming voltage pulse at a first point in the iteration of the increase in the programming voltage pulse and increase the pass voltage at the first point in accordance with the increase in the application time of the programming voltage pulse.