CN110531125B - Space transformer, probe card and manufacturing method thereof - Google Patents
Space transformer, probe card and manufacturing method thereof Download PDFInfo
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- CN110531125B CN110531125B CN201910435481.1A CN201910435481A CN110531125B CN 110531125 B CN110531125 B CN 110531125B CN 201910435481 A CN201910435481 A CN 201910435481A CN 110531125 B CN110531125 B CN 110531125B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
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- 239000010410 layer Substances 0.000 claims description 68
- 239000012792 core layer Substances 0.000 claims description 34
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06733—Geometry aspects
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
- G01R1/06755—Material aspects
- G01R1/06761—Material aspects related to layers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a space transformer, a probe card and a manufacturing method thereof. The space transformer and the probe card are suitable for detecting a wafer, the wafer comprises a plurality of crystal grains, each crystal grain and an integrated circuit carrier plate can be packaged into an integrated circuit chip, and a circuit layout is arranged between the upper surface and the lower surface of the integrated circuit carrier plate. The space transformer includes a thickening layer body and a first multilayer body. The thickening layer body comprises a plurality of intermediate connection blocks, and the first multilayer body is arranged on the lower surface of the thickening layer body. The first multilayer body comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, and each first upper contact area is electrically connected with each middle connection block respectively. A circuit layout is arranged between the first upper contact area and the first lower contact area which are opposite to each other, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier plate. In addition, two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, wherein D is n × W, and n is a positive integer greater than or equal to 2.
Description
Technical Field
The invention relates to a space transformer, a probe card and a manufacturing method thereof.
Background
The conventional method for manufacturing an integrated circuit chip includes forming a plurality of dies on a wafer, then cutting the wafer to form a plurality of independent dies, and then packaging the independent dies. The die itself can have different sizes according to different functions, the size of the die with complex functions is usually larger, and the number of contact points on the die is also larger, so the pitch of the contact points is usually very narrow. The less functionally simple die has fewer contact points, but because the die size is smaller, the contact points are also spaced more closely. Therefore, it is difficult to directly electrically connect the general die to the circuit board.
In order to allow electrical connection between the circuits in the die and the circuit board, the spatial distribution of the contacts on the die must be enlarged, which is referred to as space transform (space transform). Space conversion is typically accomplished by soldering dies to an integrated circuit carrier. The integrated circuit carrier plate is provided with an upper surface and a lower surface, the spatial distribution of upper contact points on the upper surface is the same as that of contact points of a corresponding crystal grain, the distribution of lower contact points on the lower surface is more abundant, and a circuit layout exists between the upper surface and the lower surface to electrically connect the upper contact points on the upper surface and the lower contact points on the lower surface. Thus, the spatial distribution of the contact points on the die can be enlarged by the integrated circuit carrier.
The die must typically undergo an inspection process, such as probing (bonding test) through a probe card, before being bonded to the ic carrier. In order to be able to probe the dies on the wafer, the distribution of probes on the probe card must be the same as the distribution of contact points on the dies, so the probes will also have a compact distribution. As mentioned above, the contact points on the die are difficult to be directly electrically connected to the circuit board due to the compact distribution, and the probes with compact distribution also have the problem of difficult direct electrical connection to the circuit board under test, so the probes must be also spatially converted by the "space converter" to be electrically connected to the circuit board under test.
The space transformer has an upper surface and a lower surface like an integrated circuit carrier, wherein the lower surface connected with the probes has a compact distribution of contact points same as the distribution of the probes, and the upper surface facing the test circuit board has a more spacious distribution of contact points. The upper surface and the lower surface of the space transformer are electrically connected with each other through a circuit layout.
When a conventional semiconductor tester performs space conversion of probe distribution, it only needs to consider that the probe distribution on the lower surface of the space transformer must be the same as the contact distribution on the die, and the contact distribution on the upper surface must be capable of electrically connecting with the test circuit board, and does not consider the influence of the circuit layout design between the upper and lower surfaces of the space transformer on the electrical test performance of the die. Because the die must be further connected to the ic carrier and then packaged into an ic chip, the electrical performance of the die during testing is not consistent with the electrical performance of the die after being packaged into an ic chip.
Disclosure of Invention
The present invention is directed to a space transformer for a probe card, which is suitable for probing a wafer including a plurality of dies. Each crystal grain and the integrated circuit carrier plate can be packaged into an integrated circuit chip, and a circuit layout is arranged between the upper surface and the lower surface of the integrated circuit carrier plate. The space transformer includes: a thickened layer body comprising a plurality of intermediate connection blocks; the first multilayer body is arranged on the lower surface of the thickened layer body and comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each middle connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, where D is n × W, and n is a positive integer greater than or equal to 2.
The present invention further provides a probe card, comprising: the above-mentioned space transformer; the circuit board is arranged on the upper surface of the thickened layer body; and a probe head electrically connected to the first lower contact region of each space transformation block of the first multilayer body.
The invention also provides a manufacturing method of the space transformer, the manufactured space transformer is suitable for a probe card, the probe card is suitable for detecting a wafer, the wafer comprises a plurality of crystal grains, each crystal grain can be packaged with an integrated circuit carrier plate to form an integrated circuit chip, a circuit layout is arranged between the upper surface and the lower surface of the integrated circuit carrier plate, and the manufacturing method of the probe card comprises the following steps: obtaining a circuit layout of an integrated circuit carrier plate; providing a core layer comprising a plurality of intermediate connection blocks; respectively forming a first multilayer body and a second multilayer body on two surfaces of the core layer body layer by using a multilayer organic process technology, wherein the first multilayer body comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each middle connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, wherein D is n multiplied by W, and n is a positive integer greater than or equal to 2; the second multilayer body comprises a plurality of extended electric connection blocks which are arranged at intervals, each extended electric connection block comprises a second upper contact area and a second lower contact area which are opposite to each other, and each second lower contact area is electrically connected with each middle connection block respectively.
The invention also provides a manufacturing method of the probe card, the manufactured probe card is suitable for detecting a wafer comprising a plurality of crystal grains, each crystal grain and an integrated circuit carrier plate can be packaged into an integrated circuit chip, a circuit layout is arranged between the upper surface and the lower surface of the integrated circuit carrier plate, and the manufacturing method of the probe card comprises the following steps: obtaining a circuit layout of an integrated circuit carrier plate; providing a core layer comprising a plurality of intermediate connection blocks; respectively forming a first multilayer body and a second multilayer body on two surfaces of the core layer body layer by using a multilayer organic process technology, wherein the first multilayer body comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each middle connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and the circuit layout of each space conversion block is the same as the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, wherein D is n multiplied by W, and n is a positive integer greater than or equal to 2; the second multilayer body comprises a plurality of extended electric connection blocks which are arranged at intervals, each extended electric connection block comprises a second upper contact area and a second lower contact area which are opposite to each other, and each second lower contact area is electrically connected with each middle connection block respectively; electrically connecting a circuit board to the second upper contact region of each extended electrical connection block of the second multilayer body; and a first lower contact area electrically connecting a probe head to each space transformation block of the first multilayer body.
Because the circuit layout of the space transformer is designed to be the same as the circuit layout of the integrated circuit carrier plate, the whole test condition is closer to the state when the crystal grains are packaged into the integrated circuit chip, the obtained test result is closer to the reality, and the reliability is higher.
The invention is described in detail below with reference to the drawings and specific examples, but the invention is not limited thereto.
Drawings
FIG. 1 is a schematic diagram of one embodiment of the present invention;
FIG. 2 is a schematic diagram of an embodiment of the present invention;
FIG. 3 is a bottom view of a space transformer in accordance with an embodiment of the present invention;
FIG. 4 is a top view of a space transformer according to an embodiment of the invention;
FIG. 5 is a schematic view of another embodiment of the present invention;
FIG. 6 is a schematic diagram (one) illustrating the distribution of the empty touch areas of the space transformer according to an embodiment of the present invention;
FIG. 7 is a schematic diagram (two) illustrating the distribution of the empty touch areas of the space transformer according to an embodiment of the present invention;
fig. 8 is a schematic diagram (iii) illustrating the distribution of the empty touch regions of the space transformer according to an embodiment of the present invention.
Wherein the reference numerals
10 Probe card 11 Circuit Board
112 electrical contact 115 dummy contact
13 space transformer 131 core layer body
1311 intermediate connection blocks 1311a electrically connect the vias
132 first multilayer 1321 spatial transform block
132a first upper contact area 132b first lower contact area
1322 lower contact 132L 1-4 base layer
133L1 ~ 4 base layer 133 second multilayer body
133a second upper contact region 133b second lower contact region
1331a contact points on electrical connection path 1332
135 air contact 138 reinforcement layer
139 circuit layout 15 probe head
151 probe 20 thickened layer body
23 space transformer 232b first lower contact area
233 second multilayer body 233a second upper contact region
233d dummy contact 2332
235 dummy contact 90 wafer
91 die D spacing
Width W
Detailed Description
The invention will be described in detail with reference to the following drawings, which are provided for illustration purposes and the like:
referring to fig. 1 and fig. 2, a first schematic view and a second schematic view of a probe card 10 according to an embodiment of the invention are respectively shown, which includes a circuit board 11, a space transformer 13 electrically connected to the circuit board 11, and a probe head 15 electrically connected to the space transformer 13. The various elements of the probe card 10 described above are not drawn to scale for ease of illustration of the structure of the space transformer 13. The thickness of the circuit board 11 is actually larger than that of the space transformer 13.
The probe card 10 is adapted to probe a plurality of dies 91 on a wafer 90. After the wafer 90 is diced to obtain individual dies 91, each die 91 may be further packaged together with a matching ic carrier (not shown) to form an ic chip. The integrated circuit carrier itself used in conjunction with the die 91 has a circuit layout for electrically connecting the contacts on the upper surface of the integrated circuit carrier to the contacts on the lower surface. When the die 91 is soldered on the upper surface of the ic carrier, the die 91 can be electrically connected to the external circuit board by the contact points on the lower surface of the ic carrier with wider spatial distribution through the spatial transformation of the ic carrier.
The space transformer 13 includes a thickening layer 20 and a first multilayer body 132. The thickened layer 20 of the embodiment includes the core layer 131 and the second multi-layer 133, but in another embodiment, the thickened layer 20 itself may include only the core layer 131 without the second multi-layer 133. The core layer 131 is a substrate having hardness, and the hardness of the core layer 131 is greater than that of the first multilayer body 132. The core layer 131 includes a plurality of interposer blocks 1311, and each interposer block 1311 includes a plurality of electrical vias 1311a formed by mechanical drilling.
The first multilayer body 132 includes a plurality of space transformation blocks 1321 arranged at intervals, and each space transformation block 1321 includes a first upper contact region 132a and a first lower contact region 132b opposite to each other. Each of the first upper contact areas 132a is electrically connected to each of the intermediate connection blocks 1311 of the core layer 131, a circuit layout 139 is disposed between the first upper contact areas 132a and the first lower contact areas 132b, which are opposite to each other, and the circuit layout 139 of each of the space transformation blocks 1321 is the same as the circuit layout of the ic carrier. In another embodiment, at least 70% of the circuit layout 139 of each space transformer 1321 is equal to the circuit layout of the ic carrier. The difference (less than 30%) is because in this embodiment, the circuit layout 139 of the space transformation block 1321 can add circuits, such as a feedback (Loopback) test function, capacitors, etc.
The second multilayer body 133 of the thickening layer 20 is disposed on the upper surface of the core layer 131. The second multilayer body 133 includes a plurality of extended electrical connection blocks 1331 arranged at intervals, each extended electrical connection block 1331 includes a second upper contact region 133a and a second lower contact region 133b opposite to each other, and each second lower contact region 133b is electrically connected to each intermediate connection block 1311, respectively. In this embodiment, the upper surface of the second multilayer body 133 corresponds to the upper surface of the thickening layer body 20.
As described above, the specific structure of the space transformer 13 according to an embodiment of the present invention, if the circuit board 11 is electrically connected to the second upper contact areas 133a of the extended electrical connection blocks 1331 of the second multilayer body 133 and the probe head 15 is electrically connected to the first lower contact areas 132b of the space transformer blocks 1321 of the first multilayer body 132, the probe card 10 capable of performing probing on the plurality of dies 91 of the wafer 90 is formed.
Referring to fig. 3 and 4, a bottom view and a top view of the space transformer 13 according to an embodiment of the invention are shown, respectively. As shown in fig. 3, two adjacent first lower contact regions 132b of the space transformer 13 have a distance D along an axial direction (e.g., the X-axis direction), each first lower contact region 132b has a width W along the X-axis direction, and a scribe line width between each Device Under Test (DUT) on the wafer Under Test is C (not shown), where D is n × W + (n +1) C, and n is a positive integer. When n is 1, the distance D is a width W of one DUT (corresponding to the width of the first lower contact region 132b in the X axis direction) plus a width C of two dicing lanes on both sides of the DUT in the X axis direction; when n is 2, the spacing D is the width of two DUTs plus the width C of three dicing lanes on either side of the DUT along the X axis, and so on. Fig. 3 illustrates an embodiment where n is 2. The reason why the distance D between two adjacent first lower contact regions 132b is defined as n × W + (n +1) C is to take a test method of skipping dut (device Under test) because the probe arrangement density has inherent limitation when the arrangement of the dies (or devices) to be tested on the wafer to be tested is very dense. That is, two consecutive adjacent dies to be tested (even more than three consecutive adjacent dies) located on the same axial direction are tested by the test probe card in the same testing step. Furthermore, the inherent limitation of the probe arrangement density means that the space transformer 13 has inherent limitation, the lower contact 1322 of the first lower contact region 132b is electrically connected to the circuit board 11 through the upper contact 1332 of the second upper contact region 133a after space transformation, and therefore, each first lower contact region 132b needs to be matched with a corresponding second upper contact region 133a, and when the space transformer 13 is corresponding to a range of a die to be tested, a space transformation block 1321 should be used as a space transformation block, so the space transformer 13 must adopt a space layout mode of jumping DUTs on the lower surface.
In summary, the width W of the DUT in a particular axis direction can be known from the dimensions of the first lower contact region 132b, if viewed alone with respect to the space transformer 13 itself. However, if the DUT pattern of the wafer to be tested corresponding to the space transformer 13 is not known, the width C of the scribe line on the two sides of the DUT along the specific axis cannot be known, that is, only D ═ nxw, n >1 can be observed, but it can be known that when the DUT pattern of the wafer to be tested corresponding to the space transformer 13 is known to be known to those skilled in the art, D will satisfy D ═ nxw + (n +1) C, and n is a positive integer.
In the above-mentioned specific structure of the space transformer 13 according to an embodiment of the present invention, if a circuit board 11 is electrically connected to the upper surface of the thickened layer 20 of the space transformer 13 and a probe head 15 is electrically connected to the lower surface of the space transformer 13, the probe card 10 for probing the dies 91 of the wafer 90 can be formed. As shown in fig. 1 and 2, the surface of the circuit board 11 facing the space transformer 13 is provided with a plurality of electrical contacts 112 opposite to the upper contact points 1332 of the second upper contact 133a and empty contact points 115 opposite to the empty contact points 135 of the second upper contact 133 a. The corresponding upper contact 1332 and the electrical contact 112 may be electrically connected by a solder ball. Similarly, the plurality of probes 151 on the probe head 15 may be electrically connected to the corresponding lower contacts 1322 of the first multilayer body 132 by solder balls.
It should be particularly emphasized that the first multilayer body 132 and the second multilayer body 133 of the space transformer 13 of the present embodiment are fabricated by MLO process, and the circuit layout 139 of the first multilayer body 132 is the same as the circuit layout of the ic carrier board to which the die 91 to be tested is applied. Therefore, the overall test condition can be closer to the state of the die 91 packaged into an integrated circuit chip, and the obtained test result is closer to reality, thereby increasing the reliability of the test result.
Fig. 5 is a schematic view of another embodiment of the present invention. In another embodiment of the present invention, the first multilayer body 132 and the second multilayer body 133 each include four base layers, the number of layers being the same, wherein the first multilayer body 132 includes four base layers 132L 1-132L 4, and the second multilayer body 133 includes four base layers 133L 1-133L 4. If the first multi-layer body 132 and the second multi-layer body 133 have different layers, the space transformer 13 is prone to warpage, and the upper contact point 1332 on the upper surface or the lower contact point 1322 on the lower surface are not coplanar, which may result in poor yield or reduced lifetime of the probe card 10. In addition, the surface of the second multi-layer body 133 of the space transformer 13 facing the core layer 131 may be further provided with a strengthening layer 138, which may increase the strength of the space transformer 13 as a whole. When the stiffener layer 138 is itself made of copper or other conductive material, it may also serve as a ground plane or power plane for the circuit as a whole. In addition, the strengthening layer 138 may be disposed on the surface facing away from the core layer 131, or on both the surface facing the core layer 131 and the surface facing away from the core layer 131, or even between any two base layers of the second multilayer body 133. The core layer 131 is made of glass fiber as a backbone and filled with glue, and thus has a thickness greater than one of the four base layers 132L 1-132L 4 of the first multi-layer body 132.
In the present embodiment, the upper contact points 1332 of the second multilayer body 133 of the space transformer 13 define an upper contact point spatial distribution, and the lower contact points 1322 of the first multilayer body 132 of the space transformer 13 define a lower contact point spatial distribution, wherein the lower contact points spatial distribution is denser than the upper contact points spatial distribution. The term "denser" means that the number of contact points per unit area is large, or the distance between two adjacent contact points is short, that is, the spatial distribution of the upper contact points of the space transformer 13 is spatially transformed into the spatial distribution of the lower contact points in the internal circuit of the space transformer 13. In this embodiment, the electrical connection channel 1331a of the second multilayer body 133 and the electrical connection channel 1311a of the core layer body 131 of the space transformer 13 are both vertically perforated, which indicates that the space transformer is not present in the second multilayer body 133 and the core layer body 131, and the layout of the space transformer is only generated in the first multilayer body 132.
Referring to fig. 4, a space 133c is provided around the second upper contact region 133a or between two adjacent second upper contact regions 133a of the probe card 10 of the present embodiment. A dummy contact 135 may be further provided in the space interval region 133 c. The dummy contacts 135 of the present embodiment are not electrically connected to the test circuit of the probe card 10, and one purpose of the dummy contacts 135 is to provide a support structure for the solder balls on the dummy contacts 135 when the circuit board 11 and the space transformer 13 are connected together by a reflow process using solder balls, i.e. to increase the support strength of the connection interface between the space transformer 13 and the circuit board 11. In addition, the stress can be distributed evenly to each solder ball, so as to avoid the occurrence of solder ball cracking caused by singly and excessively bearing stress in the area of the upper contact point 1332. In one embodiment, the spacing regions 133c can also define at least one electronic component placing region to place an IC chip, in addition to the dummy contacts 135. In addition, the electrical contacts between the IC chip and the second multilayer body 133 may also include more than one dummy contact 135.
Referring to FIG. 6, an exemplary distribution of the dummy contact regions 233d of the space transformer 23 on the top surface of the second multilayer body 233 is illustrated. The second multilayer body 233 includes four second upper contact regions 233a corresponding to the four first lower contact regions 232b, respectively. In this embodiment, the upper surface of the second multilayer body 233 includes a plurality of (five in the drawing) dummy contact regions 233d, and each of the dummy contact regions 233d includes a plurality of dummy contact points 235. As shown in fig. 6, the empty contact regions 233d are located at four corners and the center of gravity of the upper surface of the second multilayer body 233, respectively.
Referring to fig. 7, the dummy contact regions 233d of the second multilayer body 233 may be individually disposed at the center of gravity of the upper surface of the second multilayer body 233 and at four blocks extending in the X-axis direction and the Y-axis direction with respect to the center of gravity and intersecting with the edge of the upper surface of the second multilayer body 233, and the connection lines of the dummy contact regions 233d may form two mutually orthogonal straight lines. In addition, in the present embodiment, the spacing of the dummy contacts 235 of the dummy contact region 233d is the same as the spacing of the upper contacts 2332 of the second upper contact region 233 a.
Referring to fig. 8, the empty contact regions 233d of the second multi-layer body 233 may be disposed at four regions extending to the edge of the upper surface of the second multi-layer body 233 in the X and Y axial directions with reference to the center of gravity of the upper surface of the second multi-layer body 233 in addition to the four corners and the center of gravity of the upper surface of the second multi-layer body 233.
In one embodiment, the sum of the thicknesses of the core layer 131 and the second multilayer body 133 may be greater than 0.3mm to achieve a specific structural strength. In one embodiment, the number of spatial conversion blocks 1321 of the first multilayer body 132 is even.
Another embodiment of the present invention is a method for manufacturing the space transformer 13, wherein the method for manufacturing the space transformer 13 includes the following steps, but is not limited to the following steps, which are required to be performed in the following sequence.
First, the circuit layout of the IC carrier board used by the chip to be tested is obtained. The core layer 131 of fig. 1 is then provided, which includes a plurality of interposer blocks 1311, wherein the interposer blocks 1311 include a plurality of electrical vias 1311a formed by mechanical drilling. Referring to fig. 5, a Multi-layer Organic process (MLO) is used to form a sub-layer 132L1 of the first Multi-layer 132 and a sub-layer 133L1 of the second Multi-layer 133 on two surfaces of the core layer 131, respectively. A plurality of through holes are then formed by laser light at positions prepared as the space transformation blocks 1321 on the sub-layer 132L1 of the first multilayer body 132, and at positions prepared as the extended electrical connection blocks 1331 on the sub-layer 133L1 of the second multilayer body 133. Then, the MLO process is continued to form the sub-layer 132L2 and the sub-layer 133L 2; similarly, it is also necessary to form a through hole on the sub-layer 132L2 at a position prepared as the space transformer 1321 and form a plurality of through holes on the sub-layer 133L2 at positions prepared as the extended electrical connection blocks 1331 by laser. And so on until the number of layers of the first multilayer body 132 satisfies the requirement (e.g., having four sub-layers 132L 1-132L 4) and the number of layers of the second multilayer body 133 satisfies the requirement (e.g., having four sub-layers 133L 1-133L 4). The through holes of the sub-layers 132L 1-132L 4 of the first multi-layer body 132 are connected to each other, so that conductive traces can be formed by forming conductive material (such as copper or silver) in the through holes, and all the conductive traces of each space transformation block 1321 form the circuit layout 139. Similarly, each extended electrical connection block 1331 also has a plurality of conductive traces, and each conductive trace is respectively connected to each electrical connection channel 1311a of the middle connection block 1311.
Accordingly, the manufactured first multilayer body 132 includes a plurality of space transformation blocks 1321 arranged at intervals, each space transformation block 1321 includes a first upper contact region 132a and a first lower contact region 132b opposite to each other, and each first upper contact region 132a is electrically connected to each intermediate connection block 1311 of the core layer body 131 respectively. A circuit layout 139 is disposed between the first upper contact region 132a and the first lower contact region 132b opposite to each other. As shown in fig. 3, two adjacent first lower contact regions 132b have a distance D along an axial direction (e.g., x-axis), and each first lower contact region 132b has a width W along the same axial direction, where D is n × W, and n must be a positive integer greater than or equal to 2. In addition, the circuit layout 139 of each space transformation block 1321 must be substantially the same or at least equal to 70% or more of the circuit layout of the ic carrier used by the chip under test. The circuit layouts are the same, and the customer provides the circuit layout of the ic carrier, and can perform fine adjustment on impedance line matching, such as line width and line distance, according to the difference between the materials used for the space transformer 13 and the ic carrier.
Another embodiment of the present invention is a method for manufacturing a probe card 10, wherein the method for manufacturing the probe card 10 further includes steps of electrically connecting a circuit board 11 to the second upper contact areas 133a of the extending electrical connection blocks 1331 of the second multilayer body 133 of the space transformer 13, and electrically connecting a probe head 15 to the first lower contact areas 132b of the space transformation blocks 1321 of the first multilayer body 132, in addition to the steps of the method for manufacturing the space transformer 13.
The above embodiments include the following common features: two adjacent first lower contact areas 132b of the space transformer 13 have a distance D along an axial direction, and each first lower contact area 132b has a width W along the same axial direction, where D is n × W, and n is a positive integer greater than or equal to 2; and (ii) the circuit layout 139 of each space transformer block 1321 must be the same as the circuit layout of the ic carrier used by the die 91 to be tested. The third experiment shows that simply using the first multilayer body 132 as a space transformer results in poor flatness once bonded to the circuit board 11 by the BGA process. By combining the first multilayer body 132 with the thickened layer body 20, the overall strength is greatly increased, and poor flatness does not occur even after the first multilayer body is combined with the circuit board 11 by the reflow process.
The present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof, and it should be understood that various changes and modifications can be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (14)
1. A space transformer, adapted for use in a probe card, the probe card adapted for probing a wafer, the probe card comprising a circuit board and a probe head, the space transformer disposed between the circuit board and the probe head, the wafer comprising a plurality of dies, each die being capable of being packaged with an integrated circuit carrier into an integrated circuit chip, the integrated circuit carrier having a circuit layout between an upper surface and a lower surface thereof, the space transformer comprising:
a thickened layer body comprising a plurality of intermediate connection blocks;
a first multilayer body formed on the lower surface of the thickened layer body by using a multilayer organic process technology, and comprising a plurality of space conversion blocks arranged at intervals, wherein each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each intermediate connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and at least 70% of the circuit layout of each space conversion block is equal to the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, where D is n × W, and n is greater than 1; and
the thickening layer body comprises a core layer body and a second multilayer body, a plurality of middle connection blocks are located on the core layer body, the first multilayer body is formed on the lower surface of the core layer body, the second multilayer body is formed on the upper surface of the core layer body by utilizing a multilayer organic process technology and comprises a plurality of extending electric connection blocks which are arranged at intervals, each extending electric connection block comprises a second upper contact area and a second lower contact area which are opposite to each other, and each second lower contact area is electrically connected to each middle connection block respectively.
2. The space transformer of claim 1, further comprising a strengthening layer disposed on a surface of the second multilayer body facing the core layer or a surface facing away from the core layer.
3. The space transformer of claim 1, further comprising a plurality of dummy contacts disposed around each of the plurality of second upper contact areas.
4. The space transformer of claim 3, wherein the area between two adjacent second upper contact regions is a space interval region, and the plurality of dummy contacts are disposed in the space interval region.
5. The space transformer of claim 4, wherein the space-separating region further has an electronic component placing region.
6. The space transformer of claim 1, wherein the total thickness of the core layer body and the second multilayer body is greater than 0.3 mm.
7. The space transformer of claim 1, wherein the number of the plurality of space transformation blocks is even.
8. The space transformer of claim 7, further comprising a plurality of empty contact areas, each empty contact area comprising a plurality of empty contact points, wherein the upper surface of the second multi-layer body has a rectangular shape, and the empty contact areas are disposed at four corners and the center of gravity of the upper surface of the second multi-layer body.
9. The space transformer of claim 7, further comprising a plurality of dummy contact areas, each of the dummy contact areas comprising a plurality of dummy contact points, wherein the upper surface of the second multi-layer body has a rectangular shape, and the plurality of dummy contact areas are arranged at the center of gravity of the upper surface of the second multi-layer body and four blocks extending in an X-axis direction and a Y-axis direction with respect to the center of gravity and meeting the periphery of the upper surface of the second multi-layer body.
10. The space transformer of claim 7, further comprising a plurality of dummy contact regions, each of the dummy contact regions comprising a plurality of dummy contact points, wherein the upper surface of the second multi-layer body has a rectangular shape, and the plurality of dummy contact regions are disposed at four corners of the upper surface of the second multi-layer body, at the center of gravity, and at four blocks extending along an X-axis direction and a Y-axis direction with reference to the center of gravity to meet the periphery of the upper surface of the second multi-layer body.
11. The space transformer of claim 1, wherein the contact points of the first lower contact area of each space transformation block are distributed more densely than the contact points of the first upper contact area.
12. A probe card, comprising:
the space transformer of any one of claims 1 to 11;
the circuit board is arranged on the upper surface of the thickened layer body; and
and the probe head is electrically connected with the first lower contact area of each space conversion block of the first multilayer body.
13. A method of fabricating a space transformer, the space transformer being adapted for use in a probe card, the probe card being adapted for probing a wafer, the wafer comprising a plurality of dies, each die being capable of being packaged with an ic carrier into an ic chip, the ic carrier having a circuit layout between an upper surface and a lower surface thereof, the method comprising:
obtaining a circuit layout of the integrated circuit carrier plate;
providing a core layer body comprising a plurality of intermediate connection blocks; and
respectively forming a first multilayer body and a second multilayer body on two surfaces of the core layer body layer by using a multilayer organic process technology, wherein the first multilayer body comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each middle connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and at least 70% of the circuit layout of each space conversion block is equal to the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, where D is n × W, and n is greater than 1; the second multilayer body comprises a plurality of extending electric connection blocks which are arranged at intervals, each extending electric connection block comprises a second upper contact area and a second lower contact area which are opposite to each other, and each second lower contact area is electrically connected with each middle connection block.
14. A method for manufacturing a probe card, the manufactured probe card being suitable for probing a wafer, the wafer comprising a plurality of dies, each die being capable of being packaged with an ic carrier into an ic chip, the ic carrier having a circuit layout between an upper surface and a lower surface thereof, the method comprising:
obtaining a circuit layout of the integrated circuit carrier plate;
providing a core layer comprising a plurality of intermediate connection blocks;
respectively forming a first multilayer body and a second multilayer body on two surfaces of the core layer body layer by using a multilayer organic process technology, wherein the first multilayer body comprises a plurality of space conversion blocks which are arranged at intervals, each space conversion block comprises a first upper contact area and a first lower contact area which are opposite to each other, each first upper contact area is electrically connected with each middle connection block, a circuit layout is arranged between the first upper contact areas and the first lower contact areas which are opposite to each other, and at least 70% of the circuit layout of each space conversion block is equal to the circuit layout of the integrated circuit carrier plate; two adjacent first lower contact areas have a distance D along an axial direction, and each first lower contact area has a width W along the axial direction, where D is n × W, and n is greater than 1; the second multilayer body comprises a plurality of extended electric connection blocks which are arranged at intervals, each extended electric connection block comprises a second upper contact area and a second lower contact area which are opposite to each other, and each second lower contact area is electrically connected with each middle connection block;
electrically connecting a circuit board to the second upper contact region of each extended electrical connection block of the second multilayer body; and
and electrically connecting a probe head to the first lower contact area of each space transformation block of the first multilayer body.
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| TW107117637 | 2018-05-23 | ||
| TW107117637 | 2018-05-23 | ||
| TW108116979 | 2019-05-16 | ||
| TW108116979A TWI721424B (en) | 2018-05-23 | 2019-05-16 | Space transformer, probe card, and manufacturing methods thereof |
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| CN110531125A CN110531125A (en) | 2019-12-03 |
| CN110531125B true CN110531125B (en) | 2022-05-17 |
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| CN111366839B (en) * | 2020-03-28 | 2022-04-12 | 深圳中科系统集成技术有限公司 | Probe adapter plate for wafer test and manufacturing method thereof |
| KR102228317B1 (en) * | 2020-10-26 | 2021-03-16 | 주식회사 프로이천 | Probe card for testing wafer |
| CN115754388B (en) * | 2022-10-19 | 2023-09-29 | 深圳锐盟半导体有限公司 | Probe card, chip testing method, tester and storage medium |
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