CN110212866A - A kind of low-power consumption three-stage operational amplifier driving heavy load capacitor - Google Patents
A kind of low-power consumption three-stage operational amplifier driving heavy load capacitor Download PDFInfo
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- CN110212866A CN110212866A CN201910357478.2A CN201910357478A CN110212866A CN 110212866 A CN110212866 A CN 110212866A CN 201910357478 A CN201910357478 A CN 201910357478A CN 110212866 A CN110212866 A CN 110212866A
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/301—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in MOSFET amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/34—Negative-feedback-circuit arrangements with or without positive feedback
- H03F1/342—Negative-feedback-circuit arrangements with or without positive feedback in field-effect transistor amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G2201/00—Indexing scheme relating to subclass H03G
- H03G2201/40—Combined gain and bias control
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Abstract
The invention discloses the low-power consumption three-stage operational amplifiers that one kind can drive heavy load capacitor, including biasing circuit, input stage circuit, intergrade circuit, output-stage circuit and compensating electric capacity, wherein, biasing circuit connects input stage circuit, for providing reference voltage for input stage circuit；Input stage circuit connects intergrade circuit, for receiving reference signal and amplifying；Intergrade circuit connection output-stage circuit, for receiving signal and the amplification of input stage circuit output；Output-stage circuit is used to amplify the signal of intergrade circuit output and drives external load circuit；Compensating electric capacity is connected between the output of input stage circuit and the output of output-stage circuit, for carrying out frequency compensation to the operational amplifier.The operational amplifier is the three-stage operational amplifier of Differential Input Single-end output, and the working characteristics using metal-oxide-semiconductor in sub-threshold region realizes low-power consumption, and solves the problems, such as that the amplifier gain to work in sub-threshold region is low.
Description
Technical field
The invention belongs to electronic circuit technology fields, and in particular to one kind can drive the low-power consumption three-level of heavy load capacitor to transport
Calculate amplifier.
Background technique
With the widely available of portable device and rapidly develop, more difficult in the raising of unit volume battery capacity
Under background, the cruising ability for improving equipment just needs to reduce the power consumption of circuit.And operational amplifier is as the most heavy of analog circuit
Most basic unit is wanted, is widely used among simulation system and mixed-signal system, the low-power consumption in Analogous Integrated Electronic Circuits
Also just it is heavily dependent on the power consumption of operational amplifier.Common operational amplifier includes single stage operational amplifier, two-stage
Operational amplifier and three-stage operational amplifier.Three-stage operational amplifier has obtained extensively because of its high-gain and wide output voltage swing
Application.
With the widely available of portable device and rapidly develop, more difficult in the raising of unit volume battery capacity
Under background, the cruising ability for improving equipment just needs to reduce the power consumption of circuit.And operational amplifier is as the most heavy of analog circuit
Most basic unit is wanted, the low-power consumption in Analogous Integrated Electronic Circuits is also just heavily dependent on the power consumption of operational amplifier.And
For DC/DC converter (DC-DC converter) and LDO (low dropout regulator, low pressure difference linear voltage regulator)
Equal electric power management circuits, the performance of operational amplifier directly determine the performance of electric power management circuit.Therefore, how function is being reduced
Guarantee that the gain of error amplifier becomes urgent problem to be solved in electric power management circuit under the premise of consumption.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides one kind can drive the low of heavy load capacitor
Power consumption three-stage operational amplifier.The technical problem to be solved in the present invention is achieved through the following technical solutions:
The low-power consumption three-stage operational amplifier of heavy load capacitor can be driven the present invention provides one kind, including biasing circuit,
Input stage circuit, intergrade circuit, output-stage circuit and compensating electric capacity, wherein
The biasing circuit connects input stage circuit, for providing reference voltage for the input stage circuit；
The input stage circuit connects the intergrade circuit, for receiving the reference signal and amplifying；
Output-stage circuit described in the intergrade circuit connection, for receiving the signal of the input stage circuit output and putting
Greatly；
The output-stage circuit is used to amplify the signal of the intergrade circuit output and drives external load circuit；
The compensating electric capacity is connected between the output of the input stage circuit and the output of the output-stage circuit, is used for
Improve the DC current gain of the operational amplifier.
In one embodiment of the invention, the biasing circuit include current source, the first PMOS tube, the first NMOS tube,
Second NMOS tube, third NMOS tube, the 4th NMOS tube, wherein
The current source is connected between power end and the drain electrode of first NMOS tube；
The source electrode of first PMOS tube connects the power end, drain electrode connect simultaneously the drain electrode of the third NMOS tube with
The grid of the grid of first PMOS tube, first PMOS tube is also connected with the input stage circuit；
The grid of first NMOS tube connects the grid of the third NMOS tube and the leakage of first NMOS tube simultaneously
Pole, the source electrode of first NMOS tube connect drain electrode and the grid of second NMOS tube of second NMOS tube simultaneously；
The grid of second NMOS tube connects the grid of the 4th NMOS tube, the source electrode connection of the third NMOS tube
The drain electrode of 4th NMOS tube；
The source electrode of second NMOS tube and the source electrode of the 4th NMOS tube are all connected with ground terminal.
In one embodiment of the invention, the input stage circuit includes the second PMOS tube, third PMOS tube, the 4th
PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 5th NMOS tube, the 6th NMOS tube, the 7th NMOS tube and the 8th NMOS tube,
In,
The source electrode of the source electrode of second PMOS tube, the source electrode of the 5th PMOS tube and the 6th PMOS tube is all connected with
The power end；
The grid of second PMOS tube connects the grid of first PMOS tube, the drain electrode connection of second PMOS tube
The source electrode of the source electrode of the third PMOS tube and the 4th PMOS tube；
The grid of the third PMOS tube connects positive input, and drain electrode connects the drain electrode of the 8th NMOS tube；
The grid of 4th PMOS tube connects reverse input end, and drain electrode connects the drain electrode of the 7th NMOS tube；
The grid of 5th PMOS tube connects the grid of the 6th PMOS tube and the drain electrode of the 5th PMOS tube, institute
The drain electrode for stating the 5th PMOS tube connects the drain electrode of the 5th NMOS tube；
The drain electrode of 6th PMOS tube connects the drain electrode of the 6th NMOS tube, and the drain electrode of the 6th NMOS tube is simultaneously
Connect the 8th NMOS tube drain electrode and the intergrade circuit；
The grid of 5th NMOS tube connects the grid of the 6th NMOS tube, and source electrode connects the 7th NMOS tube
Drain electrode；
The source electrode of 6th NMOS tube connects the drain electrode of the 8th NMOS tube, the grid connection of the 7th NMOS tube
The grid of 8th NMOS tube, the source electrode of the 7th NMOS tube and the source electrode of the 8th NMOS tube are all connected with the ground connection
End；
The grid of 5th NMOS tube is connected to the grid of first NMOS tube and the grid of the third NMOS tube
Between node at；
The grid of 7th NMOS tube is connected to the grid of second NMOS tube and the grid of the 4th NMOS tube
Between node at.
In one embodiment of the invention, the intergrade circuit includes the 7th PMOS tube, the 7th PMOS tube, the 9th
NMOS tube and the tenth NMOS tube, wherein
The source electrode of 7th PMOS tube and the source electrode of the 8th PMOS tube are all connected with the power end；
The grid of 7th PMOS tube connects the drain electrode of the 6th NMOS tube, the drain electrode connection of the 7th PMOS tube
The drain electrode of 9th NMOS tube；
The grid of 8th PMOS tube connects the grid of the 6th NMOS tube, the drain electrode connection of the 8th PMOS tube
The drain electrode of tenth NMOS tube and the output-stage circuit；
The grid of 9th NMOS tube connects the grid of the tenth NMOS tube and the leakage of the 9th NMOS tube simultaneously
Pole, the source electrode of the 9th NMOS tube and the source electrode of the tenth NMOS tube are all connected with the ground terminal.
In one embodiment of the invention, the output-stage circuit includes the 9th PMOS tube and the 11st NMOS tube,
In,
The source electrode of 9th PMOS tube connects the power end, the grid connection the described 7th of the 9th PMOS tube
The grid of PMOS tube, the drain electrode of the 9th PMOS tube while drain electrode and the output end for connecting the 11st NMOS tube；
The grid of 11st NMOS tube connects the drain electrode of the tenth NMOS tube, the source electrode of the 11st NMOS tube
Connect the ground terminal.
In one embodiment of the invention, one end of the compensating electric capacity is connected to the grid of the 7th PMOS tube,
The other end is connected to the drain electrode of the 9th PMOS tube.
In one embodiment of the invention, the capacitance size of the compensating electric capacity is 0.4-0.6pF.
Compared with prior art, the beneficial effects of the present invention are:
1, the low-power consumption three-stage operational amplifier for driving heavy load capacitor of the invention is Differential Input Single-end output three
Grade operational amplifier, input stage use folded cascode configuration, and intergrade is made of positive amplifying circuit, and output stage is using altogether
Source electrode export structure improves output voltage swing, and the working characteristics using metal-oxide-semiconductor in sub-threshold region realizes the low-power consumption of circuit, and leads to
It crosses using three-level amplifier structure and solves the problems, such as that subthreshold value amplifier gain is low.
2, biasing circuit of the invention is common-source common-gate current mirror, can both inhibit the influence of channel-length modulation,
Bias voltage is provided for input stage circuit again, not only avoids increase other biasing branch to increase power consumption in this way, but also save
Chip area.
3, the method that three-stage operational amplifier of the invention has used single capacitor to compensate, this structure pass through a very little
Compensating electric capacity just may make three-level amplifier system to reach stable, it is not necessary to very big using complicated compensation circuit and chip occupying area
Resistance just obtain higher phase margin, while reducing power consumption, reduce chip area.
The present invention is described in further details below with reference to accompanying drawings and embodiments.
Detailed description of the invention
Fig. 1 is the mould for the low-power consumption three-stage operational amplifier that one kind provided in an embodiment of the present invention can drive heavy load capacitor
Block schematic diagram；
Fig. 2 is the tool for the low-power consumption three-stage operational amplifier that one kind provided in an embodiment of the present invention can drive heavy load capacitor
Body circuit diagram；
Fig. 3 is a kind of simulation waveform of low-power consumption three-stage operational amplifier provided in an embodiment of the present invention；
Fig. 4 is a kind of low-power consumption three-stage operational amplifier provided in an embodiment of the present invention when driving 10pF load capacitance
Open-loop frequency response curve.
Specific embodiment
In order to which the present invention is further explained to reach the technical means and efficacy that predetermined goal of the invention is taken, below in conjunction with
The drawings and the specific embodiments can drive the low-power consumption three-stage operational of heavy load capacitor to amplify one kind proposed according to the present invention
Device is described in detail.
For the present invention aforementioned and other technology contents, feature and effect, in the specific embodiment party of following cooperation attached drawing
Formula can be clearly presented in being described in detail.By the explanation of specific embodiment, predetermined purpose institute can be reached to the present invention
The technical means and efficacy taken more understand deeply and specifically, however appended attached drawing be only to provide reference and description it
With, not be used to technical solution of the present invention is limited.
It should be noted that herein, relational terms such as first and second and the like are used merely to a reality
Body or operation are distinguished with another entity or operation, are deposited without necessarily requiring or implying between these entities or operation
In any actual relationship or order or sequence.Moreover, the terms "include", "comprise" or any other variant be intended to it is non-
It is exclusive to include, so that article or equipment including a series of elements not only include those elements, but also including
Other elements that are not explicitly listed.In the absence of more restrictions, the element limited by sentence "including a ...",
Be not precluded include the element article or equipment in there is also other identical elements.
Embodiment one
Referring to Figure 1, Fig. 1 is the low-power consumption three-stage operational that one kind provided in an embodiment of the present invention can drive heavy load capacitor
The module diagram of amplifier.The three-stage operational amplifier includes biasing circuit 101, input stage circuit 102, intergrade circuit
103, output-stage circuit 104 and compensating electric capacity Cm, wherein biasing circuit 101 connects input stage circuit 102, for being input stage
Circuit 102 provides reference voltage；Input stage circuit 102 connects intergrade circuit 103, for receiving reference signal and amplifying；In
Intercaste circuit 103 connects output-stage circuit 104, for receiving signal and the amplification of the output of input stage circuit 102；Output-stage circuit
104 for amplifying the signal of the output of intergrade circuit 103 and driving external load circuit；Compensating electric capacity Cm is connected to input stage electricity
Between the output on road 102 and the output of output-stage circuit 104, for improving the DC current gain of operational amplifier.
Specifically, biasing circuit 101 provides reference voltage for entire three-stage operational amplifier.In the present embodiment, it biases
Circuit 101 can both inhibit the influence of channel-length modulation for source source common-gate current mirror, common-source common-gate current mirror altogether,
With it bias voltage is provided for input stage circuit simultaneously again, avoids the other biasing branch of increase both in this way to increase power consumption,
Chip area is saved again.
The operational amplifier of the present embodiment can be the three-stage operational amplifier of Differential Input Single-end output, that is, include two
Input terminal and an output end, wherein input stage circuit 102 uses folded cascode configuration, and intergrade circuit 103 is by forward direction
Amplifying circuit is constituted, and output-stage circuit 104 uses common source export structure, to improve output voltage swing.
The method that the operational amplifier of the present embodiment uses single capacitor to compensate, compensating electric capacity Cm are connected across input stage circuit
Between 102 output end and the output end of output-stage circuit 104, which just may make three by the compensating electric capacity of a very little
Grade amplifier system reaches stable.
Further, Fig. 2 is referred to, Fig. 2 is the low function that one kind provided in an embodiment of the present invention can drive heavy load capacitor
Consume the physical circuit figure of three-stage operational amplifier.The biasing circuit 101 of the present embodiment include current source Is, the first PMOS tube PM1,
First NMOS tube NM1, the second NMOS tube NM2, third NMOS tube NM3, the 4th NMOS tube NM4, wherein current source Is is connected to electricity
Between source VCC and the drain electrode of the first NMOS tube NM1；The source electrode of first PMOS tube PM1 connects power end VCC, drains while connecting
Drain electrode and the grid of the first PMOS tube PM1 of third NMOS tube NM3 are connect, the grid of the first PMOS tube PM1 is also connected with input stage electricity
Road 102；The grid of first NMOS tube NM1 connects the drain electrode of the grid and the first NMOS tube NM1 of third NMOS tube NM3 simultaneously, the
The source electrode of one NMOS tube NM1 connects the drain electrode of the second NMOS tube NM2 and the grid of the second NMOS tube NM2 simultaneously；Second NMOS tube
The grid of NM2 connects the grid of the 4th NMOS tube NM4, and the source electrode of third NMOS tube NM3 connects the drain electrode of the 4th NMOS tube NM4；
The source electrode of second NMOS tube NM2 and the source electrode of the 4th NMOS tube NM4 are all connected with ground terminal GND.
Further, the input stage circuit 102 of the present embodiment includes the second PMOS tube PM2, third PMOS tube PM3, the 4th
PMOS tube PM4, the 5th PMOS tube PM5, the 6th PMOS tube PM6, the 5th NMOS tube NM5, the 6th NMOS tube NM6, the 7th NMOS tube
NM7 and the 8th NMOS tube NM8, wherein the source electrode and the 6th PMOS tube of the source electrode of the second PMOS tube PM2, the 5th PMOS tube PM5
The source electrode of PM6 is all connected with power end VCC；The grid of second PMOS tube PM2 connects the grid of the first PMOS tube PM1, the 2nd PMOS
The source electrode of the drain electrode connection third PMOS tube PM3 of pipe PM2 and the source electrode of the 4th PMOS tube PM4；The grid of third PMOS tube PM3 connects
Connect positive input Vin+, the drain electrode of the 8th NMOS tube NM8 of drain electrode connection；The reversed input of grid connection of 4th PMOS tube PM4
Hold Vin-, the drain electrode of the 7th NMOS tube NM7 of drain electrode connection；The grid of 5th PMOS tube PM5 connects the grid of the 6th PMOS tube PM6
With the drain electrode of the 5th PMOS tube PM5, the drain electrode of the 5th NMOS tube NM5 of drain electrode connection of the 5th PMOS tube PM5；6th PMOS tube
The drain electrode of the 6th NMOS tube NM6 of drain electrode connection of PM6, the drain electrode of the 6th NMOS tube NM6 while the leakage for connecting the 8th NMOS tube NM8
Pole and intergrade circuit 103；The grid of 5th NMOS tube NM5 connects the grid of the 6th NMOS tube NM6, and source electrode connects the 7th NMOS
The drain electrode of pipe NM7；The source electrode of 6th NMOS tube NM6 connects the drain electrode of the 8th NMOS tube NM8, and the grid of the 7th NMOS tube NM7 connects
The grid of the 8th NMOS tube NM8 is connect, the source electrode of the 7th NMOS tube NM7 and the source electrode of the 8th NMOS tube NM8 are all connected with ground terminal
GND；The grid of 5th NMOS tube NM5 is connected to the section between the grid of the first NMOS tube NM1 and the grid of third NMOS tube NM3
At point；The grid of 7th NMOS tube NM7 is connected between the grid of the second NMOS tube NM2 and the grid of the 4th NMOS tube NM4
At node.
Further, the intergrade circuit 103 of the present embodiment includes the 7th PMOS tube PM7, the 7th PMOS tube PM8, the 9th
NMOS tube NM9 and the tenth NMOS tube NM10, wherein the source electrode of the 7th PMOS tube PM7 and the source electrode of the 8th PMOS tube PM8 are all connected with
Power end VCC；The grid of 7th PMOS tube PM7 connects the drain electrode of the 6th NMOS tube NM6, the drain electrode connection of the 7th PMOS tube PM7
The drain electrode of 9th NMOS tube NM9；The grid of 8th PMOS tube PM8 connects the grid of the 6th NMOS tube NM6, the 8th PMOS tube PM8
Drain electrode connection the tenth NMOS tube NM10 drain electrode and output-stage circuit 104；The grid of 9th NMOS tube NM9 connects the tenth simultaneously
The drain electrode of the grid of NMOS tube NM10 and the 9th NMOS tube NM9, the source electrode of the 9th NMOS tube NM9 and the source of the tenth NMOS tube NM10
Pole is all connected with ground terminal GND.
Further, the output-stage circuit 104 of the present embodiment includes the 9th PMOS tube PM9 and the 11st NMOS tube NM11,
Wherein, the source electrode of the 9th PMOS tube PM9 connects power end VCC, and the grid of the 9th PMOS tube PM9 connects the 7th PMOS tube PM7's
Grid, the drain electrode of the 9th PMOS tube PM9 while drain electrode and the output end vo ut for connecting the 11st NMOS tube NM11；11st NMOS
The grid of pipe NM11 connects the drain electrode of the tenth NMOS tube NM10, and the source electrode of the 11st NMOS tube NM11 connects ground terminal GND.
Further, one end of compensating electric capacity Cm is connected to the grid of the 7th PMOS tube PM7, and the other end is connected to the 9th
The drain electrode of PMOS tube PM9.In addition, the capacitance size of compensating electric capacity Cm is 0.4-0.6pF.
Table 1 is referred to, table 1 is the dimensional parameters of each metal-oxide-semiconductor in the three-stage operational amplifier of the present embodiment.
Each device size parameter of three-stage operational amplifier of table 1, the present embodiment
* wide (μm)/long (μm) × metal-oxide-semiconductor number
Common circuit structure is all that metal-oxide-semiconductor (including PMOS tube and NMOS tube) is biased in saturation region.In fact, working as
When the gate source voltage of metal-oxide-semiconductor is slightly less than its threshold voltage, the electric leakage of the metal-oxide-semiconductor with the presence of source-drain current in metal-oxide-semiconductor, and at this time
Exponential relationship is presented in stream and gate source voltage, and biggish gain still can be obtained under the electric current of very little.The present embodiment is utilized
All PMOS tube and NMOS tube are biased in sub-threshold region, the sub-threshold region by biasing circuit 101 by this characteristic of metal-oxide-semiconductor
It is the region for instigating the grid voltage of PMOS tube and NMOS tube to be slightly less than threshold voltage.
The method that metal-oxide-semiconductor is biased in sub-threshold region is had and reduces leakage current and increases two methods of breadth length ratio, but is increased
The method effect of breadth length ratio is limited and will increase chip area, therefore the present embodiment controls MOS using the method for reducing leakage current
Pipe works in sub-threshold region.In the present embodiment, the electricity of a 300nA is inputted to biasing circuit 101 by normalized current source Is
Then stream gives this electric current to the second PMOS tube by the first PMOS tube mirror image；Pass through the second NMOS tube NM2 and the 4th NMOS tube
NM4 mirror image gives the 7th NMOS tube NM7 and the 8th NMOS tube NM8, while the biasing circuit 101 is also the 5th NMOS tube NM5 and the
Six NMOS tube NM6 provide bias voltage Vb1.The electric current and that 7th NMOS tube NM7 and the 8th NMOS tube NM8 come mirror image
Three PMOS tube PM3 and the 4th PMOS tube PM4 branch current are converged in folding point, flow through the 5th PMOS tube PM5 and the 5th NMOS tube
Branch and the 6th PMOS tube PM6 and the 6th NMOS tube NM6 branch；5th PMOS tube PM5 and the 6th PMOS tube PM6 is by current mirror
One branch of two branches and output-stage circuit 104 to intergrade circuit 103, intergrade circuit 103 and output-stage circuit
The similar transistor npn npn 1:1 exact matching of 104 three branches, avoids because the factors such as technique cause transistor operationg region to become
Change.Make all to be enough to ensure that crystal plumber by the leakage current of each transistor by the gradually mirror image to reference current in this way
Make in sub-threshold region.
The three-stage operational amplifier of the present embodiment is Differential Input Single-end output three-stage operational amplifier, and input stage is using folding
Folded cascode structure, intergrade are made of positive amplifying circuit, and the third level improves output voltage swing using common source export structure,
Working characteristics using metal-oxide-semiconductor in sub-threshold region realizes low-power consumption, greatly reduces the power consumption of circuit, and transport by using three-level
Structure is put to solve the problems, such as that subthreshold value amplifier gain is low.
Fig. 3 and Fig. 4 are referred to, Fig. 3 is a kind of emulation of low-power consumption three-stage operational amplifier provided in an embodiment of the present invention
Waveform diagram, Fig. 4 are a kind of low-power consumption three-stage operational amplifiers provided in an embodiment of the present invention when driving 10pF load capacitance
Open-loop frequency response curve.Due to the metal-oxide-semiconductor leakage current very little to work in sub-threshold region, also band while bringing low-power consumption advantage
The problem of gain deficiency is carried out.The present embodiment solves the problems, such as this by three-level amplifier technology, gradually in particular by three-level
Amplification improves the gain of amplifier, and input stage circuit 102 realizes high-gain using folded cascode configuration, has 48dB or so
Gain；Intergrade circuit 103 is a positive gain stage, is responsible for keeping the negative-feedback characteristic of each node, passes through the 7th PMOS tube
The amplification (the tenth NMOS tube NM10 provides most of gain) of PM7 and the tenth NMOS tube NM10, ultimately provides the left side 30dB
Right gain；Output-stage circuit 104 again provides 30dB's or so by the 11st NMOS tube NM11 using common source configuration
Gain, while the output voltage swing also to improve amplifier.Gain is stepped up by three-level amplifier.In the load capacitance of 10pF
Under, the unity gain bandwidth of gain and 7MHz or more of the amplifier with 104dB or more, and DC power only has 3.2uW.
However, the multilevel structure of multilevel amplifiers and big capacitive load will affect the stability of operational amplifier, this implementation
Example improves the stability of amplifier using the method for single capacitor compensation.Under heavy load capacitive conditions, output stage pole frequency is lower,
To keep system to stablize, the present invention separates the pole of input stage and output stage by single compensating electric capacity Cm, and intergrade is made
At pole by increasing the mutual conductance and the appropriate size for reducing the 11st NMOS tube NM11 of intergrade, be moved into unit increasing
Outside beneficial bandwidth.Compensating electric capacity Cm can also generate feedforward path in high frequency while separating pole and introduce zero point.The present embodiment
The 9th PMOS tube PM9 by being connected to the output end of input stage and the output end of output stage eliminates its feedforward path, avoid by
The frequency characteristic of zero point deterioration amplifier is caused in compensating electric capacity Cm.
The circuit structure compares general operational amplifier, and all metal-oxide-semiconductors work in sub-threshold region, utilizes metal-oxide-semiconductor
Sub-threshold region working characteristics to realize low-power consumption, and high-gain is realized by three-level amplifier technology, is mended using single capacitor
The technology of repaying solves the stability problem of multilevel amplifiers.The three-stage operational amplifier under low-power consumption heavy load capacitive conditions still
Realize very high gain bandwidth product and system stability.
As shown in figure 4, reaching the amplifier under conditions of low-power consumption heavy load capacitor by above method
The gain of 100dB or more, and phase margin is made to have reached requirement.Further, as shown in figure 3, the circuit is in the negative of 10pF
It carries under capacitor, the compensating electric capacity by 0.49pF is that the phase margin of system may make to be greater than 62 °.
The biasing circuit that the present embodiment uses can both inhibit channel-length modulation for a common-source common-gate current mirror
It influences, and provides bias voltage with it simultaneously for input stage circuit.It both avoids in this way and increases other biasing branch to increase
Add power consumption, and saves chip area.In addition, the low-power consumption three-stage operational amplifier for driving heavy load capacitor of the present embodiment
The method for having used single capacitor to compensate, this structure just may make three-level amplifier system to reach by the compensating electric capacity of a very little
Stablize, it is not necessary to just obtain higher phase margin using the very big resistance of complicated compensation circuit and chip occupying area, together
When reduce power consumption again, reduce chip area.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (7)
1. the low-power consumption three-stage operational amplifier that one kind can drive heavy load capacitor, which is characterized in that including biasing circuit
(101), input stage circuit (102), intergrade circuit (103), output-stage circuit (104) and compensating electric capacity (Cm), wherein
The biasing circuit (101) connects input stage circuit (102), for providing benchmark electricity for the input stage circuit (102)
Pressure；
The input stage circuit (102) connects the intergrade circuit (103), for receiving the reference signal and amplifying；
The intergrade circuit (103) connects the output-stage circuit (104), defeated for receiving the input stage circuit (102)
Signal and amplification out；
The output-stage circuit (104) is used to amplify the signal of intergrade circuit (103) output and drives external loading electric
Road；
The compensating electric capacity (Cm) is connected to the defeated of the output of the input stage circuit (102) and the output-stage circuit (104)
Between out, for improving the DC current gain of the operational amplifier.
2. one kind according to claim 1 can drive the low-power consumption three-stage operational amplifier of heavy load capacitor, feature exists
In the biasing circuit (101) includes current source (Is), the first PMOS tube (PM1), the first NMOS tube (NM1), the second NMOS tube
(NM2), third NMOS tube (NM3), the 4th NMOS tube (NM4), wherein
The current source (Is) is connected between power end (VCC) and the drain electrode of first NMOS tube (NM1)；
The source electrode of first PMOS tube (PM1) connects the power end (VCC), drains while connecting the third NMOS tube
(NM3) grid of drain electrode and first PMOS tube (PM1), the grid of first PMOS tube (PM1) are also connected with described defeated
Enter a grade circuit (102)；
The grid of first NMOS tube (NM1) connects the grid and the first NMOS of the third NMOS tube (NM3) simultaneously
The drain electrode of (NM1) is managed, the source electrode of first NMOS tube (NM1) connects drain electrode and the institute of second NMOS tube (NM2) simultaneously
State the grid of the second NMOS tube (NM2)；
The grid of second NMOS tube (NM2) connects the grid of the 4th NMOS tube (NM4), the third NMOS tube
(NM3) source electrode connects the drain electrode of the 4th NMOS tube (NM4)；
The source electrode of second NMOS tube (NM2) and the source electrode of the 4th NMOS tube (NM4) are all connected with ground terminal (GND).
3. one kind according to claim 2 can drive the low-power consumption three-stage operational amplifier of heavy load capacitor, feature exists
In, the input stage circuit (102) include the second PMOS tube (PM2), third PMOS tube (PM3), the 4th PMOS tube (PM4), the
Five PMOS tube (PM5), the 6th PMOS tube (PM6), the 5th NMOS tube (NM5), the 6th NMOS tube (NM6), the 7th NMOS tube (NM7)
With the 8th NMOS tube (NM8), wherein
The source electrode of second PMOS tube (PM2), the source electrode of the 5th PMOS tube (PM5) and the 6th PMOS tube (PM6)
Source electrode be all connected with the power end (VCC)；
The grid of second PMOS tube (PM2) connects the grid of first PMOS tube (PM1), second PMOS tube
(PM2) drain electrode connects the source electrode of the third PMOS tube (PM3) and the source electrode of the 4th PMOS tube (PM4)；
The grid of the third PMOS tube (PM3) connects positive input (Vin+), and drain electrode connects the 8th NMOS tube (NM8)
Drain electrode；
The grid of 4th PMOS tube (PM4) connects reverse input end (Vin-), and drain electrode connects the 7th NMOS tube (NM7)
Drain electrode；
The grid of grid connection the 6th PMOS tube (PM6) of 5th PMOS tube (PM5) and the 5th PMOS tube
(PM5) drain electrode, the drain electrode of the 5th PMOS tube (PM5) connect the drain electrode of the 5th NMOS tube (NM5)；
The drain electrode of 6th PMOS tube (PM6) connects the drain electrode of the 6th NMOS tube (NM6), the 6th NMOS tube
(NM6) drain electrode connects drain electrode and the intergrade circuit (103) of the 8th NMOS tube (NM8) simultaneously；
The grid of 5th NMOS tube (NM5) connects the grid of the 6th NMOS tube (NM6), source electrode connection the described 7th
The drain electrode of NMOS tube (NM7)；
The source electrode of 6th NMOS tube (NM6) connects the drain electrode of the 8th NMOS tube (NM8), the 7th NMOS tube
(NM7) grid connects the grid of the 8th NMOS tube (NM8), the source electrode and the described 8th of the 7th NMOS tube (NM7)
The source electrode of NMOS tube (NM8) is all connected with the ground terminal (GND)；
The grid of 5th NMOS tube (NM5) be connected to first NMOS tube (NM1) grid and the third NMOS tube
(NM3) at the node between grid；
The grid of 7th NMOS tube (NM7) be connected to second NMOS tube (NM2) grid and the 4th NMOS tube
(NM4) at the node between grid.
4. one kind according to claim 3 can drive the low-power consumption three-stage operational amplifier of heavy load capacitor, feature exists
In, the intergrade circuit (103) include the 7th PMOS tube (PM7), the 7th PMOS tube (PM8), the 9th NMOS tube (NM9) and the
Ten NMOS tubes (NM10), wherein
The source electrode of 7th PMOS tube (PM7) and the source electrode of the 8th PMOS tube (PM8) are all connected with the power end
(VCC)；
The grid of 7th PMOS tube (PM7) connects the drain electrode of the 6th NMOS tube (NM6), the 7th PMOS tube
(PM7) drain electrode connects the drain electrode of the 9th NMOS tube (NM9)；
The grid of 8th PMOS tube (PM8) connects the grid of the 6th NMOS tube (NM6), the 8th PMOS tube
(PM8) drain electrode connects drain electrode and the output-stage circuit (104) of the tenth NMOS tube (NM10)；
The grid of 9th NMOS tube (NM9) connects the grid and the 9th NMOS of the tenth NMOS tube (NM10) simultaneously
The drain electrode of (NM9) is managed, the source electrode of the 9th NMOS tube (NM9) and the source electrode of the tenth NMOS tube (NM10) are all connected with described
Ground terminal (GND).
5. one kind according to claim 4 can drive the low-power consumption three-stage operational amplifier of heavy load capacitor, feature exists
In the output-stage circuit (104) includes the 9th PMOS tube (PM9) and the 11st NMOS tube (NM11), wherein
The source electrode of 9th PMOS tube (PM9) connects the power end (VCC), and the grid of the 9th PMOS tube (PM9) connects
The grid of the 7th PMOS tube (PM7) is connect, the drain electrode of the 9th PMOS tube (PM9) connects the 11st NMOS tube simultaneously
(NM11) drain electrode and output end (Vout)；
The grid of 11st NMOS tube (NM11) connects the drain electrode of the tenth NMOS tube (NM10), the 11st NMOS
The source electrode for managing (NM11) connects the ground terminal (GND).
6. one kind according to claim 5 can drive the low-power consumption three-stage operational amplifier of heavy load capacitor, feature exists
In one end of the compensating electric capacity (Cm) is connected to the grid of the 7th PMOS tube (PM7), and the other end is connected to the described 9th
The drain electrode of PMOS tube (PM9).
7. one kind according to any one of claim 1 to 6 can drive the low-power consumption three-stage operational of heavy load capacitor to amplify
Device, which is characterized in that the capacitance size of the compensating electric capacity (Cm) is 0.4-0.6pF.
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| CN110649893A (en) * | 2019-10-18 | 2020-01-03 | 中国电子科技集团公司第十四研究所 | Low-power-consumption rail-to-rail driving amplifier circuit |
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| CN111628772B (en) * | 2020-05-13 | 2023-09-29 | 西安电子科技大学 | High-speed high-precision time domain analog-to-digital converter |
| CN113419594A (en) * | 2021-07-02 | 2021-09-21 | 合肥睿普康集成电路有限公司 | Quiescent current control circuit capable of being used for operational amplifier |
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