CN109638153A - A kind of gating tube material, gating tube device and preparation method thereof - Google Patents
A kind of gating tube material, gating tube device and preparation method thereof Download PDFInfo
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- 239000000463 material Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title claims abstract description 26
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- 239000002184 metal Substances 0.000 claims abstract description 92
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 18
- 229910052787 antimony Inorganic materials 0.000 claims abstract description 12
- 229910052796 boron Inorganic materials 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 229910052797 bismuth Inorganic materials 0.000 claims abstract description 10
- 239000007772 electrode material Substances 0.000 claims description 12
- 239000011148 porous material Substances 0.000 claims description 11
- 239000000126 substance Substances 0.000 claims description 8
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052718 tin Inorganic materials 0.000 claims description 7
- 229910008599 TiW Inorganic materials 0.000 claims description 6
- HTXDPTMKBJXEOW-UHFFFAOYSA-N iridium(IV) oxide Inorganic materials O=[Ir]=O HTXDPTMKBJXEOW-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
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- 229910000765 intermetallic Inorganic materials 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 238000004549 pulsed laser deposition Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
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- RTZKZFJDLAIYFH-UHFFFAOYSA-N Diethyl ether Chemical compound CCOCC RTZKZFJDLAIYFH-UHFFFAOYSA-N 0.000 description 2
- 229910005900 GeTe Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
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Abstract
The invention belongs to wiener electronic technology fields, more particularly to a kind of gating material, gating tube device and preparation method thereof.The gating tube device includes: the gating layer among the first metal electrode layer, the second metal electrode layer and above-mentioned two electrode layer.The gating layer materials chemistry general formula can be illustrated as GexTeyA100‑x‑y: in A generation, refers to one of Elements C, B, Si, Al, Sb, Bi in above-mentioned formula, and x, y are the atomic percent and 10≤x < 60 of element, 40 < y < 90,0 100-x-y≤25 <.Gate tube provided by the invention has the advantages that preparation is simple, can drive superelevation on-state current (> 11mA), low off-state current, high on-off ratio, high switching speed and low open voltage.
Description
Technical field
The invention belongs to wiener electronic technology fields, more particularly to a kind of gating material, gating tube device and its preparation
Method.
Background technique
Semiconductor storage unit is one of pillar of information age.Follow-on novel nonvolatile storage such as phase change memory
Erasable and writing speed that the devices such as device, resistance-variable storing device are exceedingly fast due to it, splendid miniature performance, can be three-dimensional stacked etc. characteristics become and work as
Preceding most popular next-generation memory.It increasingly fails in Moore's Law current, in order to further increase storage density, three-dimensional heap
Folded storage unit becomes a very effective scheme.Gate tube is exactly to realize that high density large scale array is integrated, reduces operation
Power consumption and the core devices for reducing effective cellar area；Wherein, two ends gating tube device can be with storage unit Vertical collection
Realize that memory device is three-dimensional stacked, so that effective cellar area is reduced, to increase substantially storage density；In addition, gate tube
High-impedance state can effectively inhibit leakage current, reduce operation power consumption.
When gate tube is that storage unit integrates, original storage unit performance should not be influenced: as switching speed is wanted
Far below the low value state that the erasable time of storage unit, the ON resistance of memory will be far below storage unit.Meanwhile in order to mention
The scale of highly integrated array, gate tube to be able to bear storage unit it is erasable when huge current flow, while effectively inhibiting not gated
The leakage current of unit.In addition, in order to reduce the power consumption of storage array, (high resistant occurs for the open voltage of gate tube to when low-resistance transformation
Voltage) can not ether it is high, on-off ratio needs sufficiently large.Finally, in order to the three-dimensional stacked knot that further increases storage density
Structure adapts to, and back segment preparation process requires the preparation temperature of gate tube unsuitable excessively high, and the gate tube of low temperature preparation ensure that memory
Part has three-dimensional stacked ability.
Current more valuable gating tube device has: ovonic threshold switch (OTS) device (Ovonic Threshold
Switch, OTS), metal-insulator transition device (Metal Insulator Transition, MIT), mixed electronic ion lead
Electrical part (Mixed Ionic and Electronic Conductor, MIEC) and the threshold switching device based on conductive filament.
Current MIT gate tube on-off ratio is relatively small.For MIEC device still in conceptual phase, there is no disclose its specific material.Base
Although there is bigger on-off ratio in the threshold switching device of conductive filament, but its switching speed is very slow, and is difficult to bear ratio
Biggish on-state current, stability is not high.The switching speed of OTS gate tube has nanosecond far faster than other types gate tube
Other switching speed, and it is capable of providing the on-state current of milliampere rank, but its on-off ratio needs to be further increased.
It is current it has been reported that OTS gate tube have the shortcomings that it is many: first, preparation process too complex, such as by Wu
Good ability et al. application patent (publication number CN106601907A) in be previously mentioned based on GexTeySezAs100-x-y-zGate tube,
It needs the ratio of four kinds of elements in preparation process and needs ion implantation technique complicated for operation, this is undoubtedly considerably increased
Technology difficulty；In addition, arsenic (As) is the chemical element of severe toxicity, this undoubtedly reduces the safety and reliability of technique.Second, device
The deficiency of part performance, including on-off ratio is small, open voltage is too big, stability is poor, can driving current it is insufficient the problems such as.Equally with Wu Liang
For the material that ability et al. is announced, open voltage is up to 1.7V, switchs smaller and can not drive biggish electric current.Compare again
" the Te-based chalcogenide materials for selector delivered such as Velea A et al.
Applications ", wherein the GeTe announced6、GeTe4, doping Si the fret switches such as GeTe than being just slightly greater than 103, open electricity
Pressure is also up to 1.6V~2.4V, and the open voltage that these materials can drive is also only only proximate to 100uA.
Therefore, that there is an urgent need to a kind of threshold voltages at present is suitable, switching speed is fast, high on-off ratio, high on-state current, low pass
State leakage current, can low temperature preparation and the gating tube device compatible with three-dimensional stacking structure.
Summary of the invention
Aiming at the above defects or improvement requirements of the prior art, the present invention provides a kind of gating tube materials, gate tube device
Part and preparation method thereof sufficiently combines the characteristics of gating material and demand, in GexTeyIt is middle to be introduced into C, B, Si, Al, Sb, Bi
A kind of element, the gating tube material that a kind of stability is high, switching speed is fast is accordingly obtained, made of the gating tube material
Gating tube device is simple with preparation, superelevation on-state current (> 11mA), low off-state current, high on-off ratio, high switch can be driven fast
The advantages of degree and low open voltage.Thus solve existing gate tube threshold voltage is too high, on-off ratio is low, ON state can carry electric current deficiency
The high technical problem with OFF leakage current.
To achieve the above object, according to one aspect of the present invention, a kind of gating tube material is provided, the gating tube material
Chemical general formula be expressed as GexTeyA100-x-y, wherein in A generation, refers to one of Elements C, B, Si, Al, Sb and Bi, and x, y are element
Atomic percent, and 10≤x < 60,40 < y < 90,0 100-x-y≤25 <.
Preferably, GexTeyA100-x-yIn, 20≤x < 45,55 < y≤70,0 100-x-y≤15 <.
Preferably, the gating tube material can be realized high-impedance state to low resistance state instantaneous variation, and when electric signal be lower than one
Determine size or remove after electric signal can automatic returning to initial high-impedance state.
Preferably, which returns to low resistance state or returns to required for high-impedance state from low resistance state and turn from high-impedance state
Become the time between 0.01~10ns.
Other side according to the invention provides the gating tube device list of gating tube material production described in one kind
Member, the gate tube device cell include:
First metal electrode layer；
Second metal electrode layer；
Gating layer between first metal electrode layer and second metal electrode layer, the gating layer use
Material be the gating tube material.
Preferably, first metal electrode layer and second metal electrode layer are all made of inert electrode material, and institute
Stating inert electrode material is W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO and IZO it is one or more and described
First metal electrode layer and the second metal electrode layer are with a thickness of 10nm to 200nm.
Preferably, the gating layer side is contacted with first metal electrode layer or second metal electrode layer, and
The other side of the gating layer is contacted with another metal electrode layer.
Preferably, the gating layer with a thickness of 1nm to 200nm.
Other side according to the invention provides the preparation method of gate tube device cell described in one kind, including
Following steps:
(1) the first metal electrode layer is prepared on substrate；
(2) insulating layer is prepared on first metal electrode layer, processing is patterned to the insulating layer, obtains hole
Structure, and expose by the pore structure the first metal electrode layer of section bottom；
(3) gating layer is prepared on the first metal electrode layer exposed, fills the pore structure, the gating layer uses
Material be gating tube material as described in Claims 1-4 any one；
(4) the second metal electrode layer is prepared on the insulating layer for be filled with pore structure, make first metal electrode layer and
Second metal electrode layer is connected to by gating layer, obtains the gate tube device cell.
In general, through the invention it is contemplated above technical scheme is compared with the prior art, can obtain down and show
Beneficial effect:
Firstly, gating tube material of the present invention passes through in GexTeyOne of middle introducing C, B, Si, Al, Sb, Bi member
Element, effectively increases the stability of gating tube material, and realizes cracking switching speed.
Secondly, OTS device can be significantly reduced using the gating tube device of gating tube material preparation of the present invention
Open voltage reduces storage unit read-write operation power consumption.And while carrying great on-state current, it can effectively inhibit to leak
Electric current effectively improves the on-off ratio of device.Gating tube device of the present invention can be realized Mass storage array,
And the erasable and writing speed of storage unit is not interfered with.
Finally, device cell preparation process described in this patent does not need, high-temperature technology, the cellular construction be simple, cost
It is cheap.Simultaneously because the device is two-terminal device, and can vertical stacking, so being capable of perfect compatible three-dimensional stacking structure.
Detailed description of the invention
Fig. 1 (a) to Fig. 1 (e) is a kind of gate tube device fabrication process that present example provides；
Fig. 2 is the DC voltage-current curve measured drawing for the gating tube device that present example 4 provides；
Fig. 3 is the pulse real-time response test chart for the gating tube device that present example 4 provides；
Fig. 4 is the DC voltage-current curve measured drawing for the gating tube device that present example 5 provides.
In all the appended drawings, identical appended drawing reference is used to denote the same element or structure, in which:
1- substrate；The first metal electrode layer of 2-；3- insulating layer；The pore structure that 4- etching insulating layer obtains；5- gating layer；6-
Second metal electrode layer.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, with reference to the accompanying drawings and embodiments, right
The present invention is further elaborated.It should be appreciated that the specific embodiments described herein are merely illustrative of the present invention, and
It is not used in the restriction present invention.As long as in addition, technical characteristic involved in the various embodiments of the present invention described below
Not constituting a conflict with each other can be combined with each other.
The present invention provides a kind of gating tube material, the chemical general formula of the gating tube material is expressed as GexTeyA100-x-y,
In middle A generation, refers to one of Elements C, B, Si, Al, Sb and Bi, and x, y are the atomic percent of element, and 10≤x < 60,40 < y <
90,0 100-x-y≤25 <.In preferred embodiment, 20≤x < 45,55 < y≤70,0 100-x-y≤15 <.The gating tube material
Can be realized high-impedance state to low resistance state instantaneous variation, and when electric signal is lower than a certain size or remove can be automatic after electric signal
It revert to initial high-impedance state.And the gating tube material returns to low resistance state from high-impedance state or returns to needed for high-impedance state from low resistance state
The fringe time wanted is adjustable between 0.01~10ns.
According to the signal formula Ge of chemical general formulaxTeyA100-x-y(wherein, in A generation, refers to Elements C, one in B, Si, Al, Sb, Bi
Kind) in different elements proportion, using sputtering method, pulsed laser deposition, evaporation, chemical vapour deposition technique, plasma
Enhance chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, metallic compound vapour deposition process, molecular beam epitaxy, atom
Vapour deposition process, atomic layer deposition method prepare the gating tube material.
The present invention also provides a kind of gate tube device cell using the gating tube material production, the gate tube devices
Part unit includes:
First metal electrode layer；
Second metal electrode layer；
Gating layer between first metal electrode layer and second metal electrode layer, the gating layer use
Material be the gating tube material.
In some embodiments, first metal electrode layer and second metal electrode layer are all made of inert electrode material
Material, and the inert electrode material is W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO and IZO one kind or more
Kind, and first metal electrode layer and the second metal electrode layer are with a thickness of 10nm to 200nm.
In some embodiments, the gating layer side connects with first metal electrode layer or second metal electrode layer
Touching, and the other side of the gating layer is contacted with another metal electrode.
In some embodiments, the gating layer with a thickness of 1nm to 200nm.
The present invention provides a kind of preparation methods of above-mentioned gate tube device cell, include the following steps:
(1) the first metal electrode layer is prepared on substrate；
(2) insulating layer is prepared on first metal electrode layer, processing is patterned to the insulating layer, obtains hole
Structure, and expose by the pore structure the first metal electrode layer of section bottom；Ultraviolet photolithographic or electronics can be passed through
Beam photoetching (EBL) forms figure, then obtains figure of different shapes using conductive coupling plasma etching (ICP).
(3) gating layer is prepared on the first metal electrode layer exposed, fills the pore structure, the gating layer uses
Material be gating tube material as described above；
(4) the second metal electrode layer is prepared on the insulating layer for be filled with pore structure, make first metal electrode layer and
Second metal electrode layer is connected to by gating layer, obtains the gate tube device cell.
The present invention also provides a kind of gating tube device, includes the gate tube device cell described in several.
The following are embodiments:
Embodiment 1
This embodiment provides a kind of gating tube material, is characterized in: the gate tube materials chemistry general formula can be illustrated as
GexTeyA100-x-y(wherein A generation refer to one of Elements C, B, Si, Al, Sb, Bi), x, y be the atomic percent of element and 10≤
X < 60,40 < y < 90,0 100-x-y≤25 <.
Preferably, in the GexTeyA100-x-yIn (wherein in A generation, refers to one of Elements C, B, Si, Al, Sb, Bi), selection
Elements C constitutes GexTeyC100-x-y, and 10≤x < 60,40 < y < 90,0 100-x-y≤25 <.
It is further preferred that in the GexTeyA100-x-yIn (wherein in A generation, refers to one of Elements C, B, Si, Al, Sb, Bi),
Elements C is selected to constitute GexTeyC100-x-y, and 20≤x≤45,55 y≤70 <, 0 100-x-y≤15 <.
More specifically, the gate tube material thickness is 1~200nm.Preferably, in the implementation case, the gating
Tube material is with a thickness of 120nm；Naturally, in other case study on implementation, the gate tube material thickness can also be 5nm, 15nm,
25nm, 35nm, 45nm, 55nm, 65nm, 70nm, 80nm, 90nm or 110nm etc..
Specifically, the gating tube material can significantly reduce open voltage (voltage value of the high-impedance state to low resistance state when occurs).
In the implementation case, the open voltage of the gating tube material is 0.6V；Certainly, in other case study on implementation, according to selection
The difference of chemical general formula, open voltage can also be 0.1V, 0.2V, 0.3V, 0.4V, 0.5V, 0.7V or 0.8V etc..
Specifically, high-impedance state may be implemented to low resistance state under a certain size electric signal operation in the gating tube material
Instantaneous variation, and instantaneous automatic returning is to initial high-impedance state after electric signal is lower than a certain size (or removing electric signal).It is logical
The ratio for overregulating material each component returns to low resistance state from high-impedance state or is returned to when changing required for high-impedance state from low resistance state
Between can be adjusted between 0.01~10ns.
It is worth noting that, fringe time is different according to the difference of the chemical general formula of selection.Preferably, in the implementation
Fringe time is 0.01s in case.
Embodiment 2
The present embodiment also provides a kind of gating tube material production method as described in embodiment one, according to showing for chemical general formula
Italian type GexTeyA100-x-yThe proportion of different elements in (wherein, A generation refer to one of Elements C, B, Si, Al, Sb, Bi), using splashing
Penetrate method, pulsed laser deposition, evaporation, chemical vapour deposition technique, plasma enhanced chemical vapor deposition method, low pressure chemical
Vapour deposition process, metallic compound vapour deposition process, molecular beam epitaxy, atomic vapor deposition method, atomic layer deposition method preparation
The gating tube material.
Preferably, in the present embodiment, Elements C is selected to constitute GexTeyC100-x-yFilm, and prepared using magnetron co-sputtering
GexTeyC100-x-yFilm；It is further preferred that the GexTeyC100-x-yFilm is Ge20Te65C15Film.
Specifically: using Ge25Te75Alloys target, Ge50Te50Alloys target, C target co-sputtering deposition are certain thickness
Ge20Te65C15Film, technological parameter are as follows: being evacuated to background vacuum pressure is 1 × 10-7Pa, logical Ar gas, mobility size are when sputtering
10mTorr, pressure control is in 0.9Pa, Ge25Te75Alloy target power output is 40W, Ge50Te50Alloy target power output is 15W, the function of C target
Rate is 150W, is sputtered 40 minutes.
Specifically, it is described gating tube material with a thickness of 1~200nm.
Preferably, in the present embodiment, the gate tube material thickness is 120nm；Naturally, in other case study on implementation,
The gate tube material thickness can also be 5nm, 15nm, 25nm, 35nm, 45nm, 55nm, 65nm, 70nm, 80nm, 90nm or
Person 110nm etc..
Embodiment 3
As shown in Figure 1, this example provides a kind of gating tube device using gating tube material production described in embodiment 1,
The gating tube device includes:
First metal electrode layer 2；
Second metal electrode layer 6；
Gating layer 5 among above-mentioned two electrode layer.
Specifically, first metal electrode layer 1 and the second metal electrode layer 6 are inert electrode material, and described lazy
Property electrode material be the one or more of W, TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, IZO, and described first
Metal electrode layer and the second metal electrode layer are with a thickness of 10 to 200nm.
Preferably, in this example, first metal electrode layer 1 and the second metal electrode layer 6 are W electrode, and thick
Degree is 100nm.
Embodiment 4
This example provides a kind of preparation method using gating pipe unit described in embodiment 3, and the preparation method includes:
S1: first layer inert metal electrode 2 is prepared on substrate 1；
S2: insulating layer 3 is prepared on the first layer metal electrode 2, and the insulating layer is patterned and is led
Through-hole 4 simultaneously exposes hearth electrode 2；
S3: the gate tube material layer 5 is prepared on the hearth electrode 2 exposed；
S4: the second metal electrode layer 6 is prepared on the insulating layer for be filled with pore structure.
The preparation method for gating tube device described in the present embodiment below with reference to Fig. 1 is described in detail.
The first step prepares first layer inert metal electrode 2 as shown in Fig. 1 (a) on substrate 1.
Specifically, using sputtering method, pulsed laser deposition, evaporation, chemical vapour deposition technique, plasma enhancing
It is heavy to learn vapour deposition process, Low Pressure Chemical Vapor Deposition, metallic compound vapour deposition process, molecular beam epitaxy, atom gas phase
Any means in area method, atomic layer deposition method preparation prepare the first layer inert metal electrode 2.Preferably, this example is adopted
The first layer inert metal electrode 2 is prepared with sputtering method.
Specifically, first metal electrode layer 2 be inert electrode material, and the inert electrode material be W, TiW,
Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, IZO's is one or more, and first metal electrode layer 2 is with a thickness of 10
To 200nm.
Preferably, in this example, first metal electrode layer 2 is W electrode, and with a thickness of 100nm.
Second step prepares insulating layer 3 as shown in Fig. 1 (b) on first layer inert metal electrode 2.
Specifically, using sputtering method, pulsed laser deposition, evaporation, chemical vapour deposition technique, plasma enhancing
It is heavy to learn vapour deposition process, Low Pressure Chemical Vapor Deposition, metallic compound vapour deposition process, molecular beam epitaxy, atom gas phase
Any means in area method, atomic layer deposition method preparation prepare the insulating layer 3.Preferably, this example using plasma increases
Extensive chemical vapour deposition process (PECVD) prepares the insulating layer 3.
Specifically, the insulating layer 3 can be SiO2、SiNxOne of, and thickness is in 50nm~200nm.Preferably,
This example uses SiO2As insulating layer 3, and with a thickness of 100nm.
Third step obtains via hole 4 on the insulating layer 3 using lithography and etching as shown in Fig. 1 (c), exposes
One metal electrode layer 2.
4th step prepares gate tube material layer 5 on 2 surface of the first metal electrode layer as shown in Fig. 1 (d).
Specifically, according to the signal formula Ge of chemical general formulaxTeyA100-x-y(wherein, in A generation, refers to Elements C, B, Si, Al, Sb, Bi
One of) in different elements proportion, using sputtering method, pulsed laser deposition, evaporation, chemical vapour deposition technique, etc.
Gas ions enhance chemical vapour deposition technique, Low Pressure Chemical Vapor Deposition, metallic compound vapour deposition process, molecular beam epitaxy
Method, atomic vapor deposition method, atomic layer deposition method prepare the gating tube material 5.
Preferably, in the present embodiment, Elements C is selected to constitute GexTey C 100-x-yFilm, and use magnetic control co-sputtering legal system
Standby GexTey C 100-x-yFilm；It is further preferred that the GexTey C 100-x-yFilm is Ge20Te65C15Film.
Specifically: using Ge25Te75Alloys target, Ge50Te50Alloys target, C target co-sputtering deposition are certain thickness
Ge20Te65C15Film, technological parameter are as follows: being evacuated to background vacuum pressure is 1 × 10-7Pa, logical Ar gas, mobility size are when sputtering
10mTorr, pressure control is in 0.9Pa, Ge25Te75Alloy target power output is 40W, Ge50Te50Alloy target power output is 15W, the function of C target
Rate is 150W, is sputtered 40 minutes.
Specifically, it is described gating tube material 5 with a thickness of 1~200nm.
Preferably, in the present embodiment, the Ge20Te65C15Film with a thickness of 120nm；Naturally, other are implemented
In case, 5 thickness of gating tube material can also be 5nm, 15nm, 25nm, 35nm, 45nm, 55nm, 65nm, 70nm,
80nm, 90nm or 110nm etc..
5th step prepares other one layer of inert metal electrode 6 on the insulating layer 3 and gating tube material 5.
Specifically, using sputtering method, pulsed laser deposition, evaporation, chemical vapour deposition technique, plasma enhancing
It is heavy to learn vapour deposition process, Low Pressure Chemical Vapor Deposition, metallic compound vapour deposition process, molecular beam epitaxy, atom gas phase
Any means in area method, atomic layer deposition method preparation prepare the first layer inert metal electrode 6.Preferably, this example is adopted
Other one layer of inert metal electrode 6 is prepared with sputtering method.
Specifically, other one layer of inert metal electrode 6 be inert electrode material, and the inert electrode material be W,
TiW, Pt, Au, Ru, Al, TiN, Ta, TaN, IrO2, ITO, IZO's is one or more, and other one layer of inert metal electricity
200nm is arrived with a thickness of 10 in pole 6.
Preferably, in this example, other one layer of inert metal electrode 6 is W electrode, and with a thickness of 100nm.
After carrying out above-mentioned technique, obtained print is tested to obtain Fig. 2 and electrology characteristic curve shown in Fig. 3, it should
Shown in gate tube sample structure such as Fig. 1 (e), first layer inert metal electrode 2 is prepared on substrate 1, and institute is prepared using sputtering method
First layer inert metal electrode 2 is stated, the first metal electrode layer 2 is W electrode, and with a thickness of 100nm；Using SiO2As insulating layer
3, and with a thickness of 100nm；Gating layer is Ge20Te65C15Film, with a thickness of 120nm；Other one layer of inert metal electrode 6 is W electricity
Pole, and with a thickness of 100nm.
From figure 2 it can be seen that the threshold voltage of gate tube of the present invention is 0.6V, it is more excellent.In threshold value
Before voltage, with the increase for applying voltage to the gating tube device, the electric current of device is still very small, and device is in high resistant
State；Only when voltage reaches threshold voltage, the electric current of device can increase suddenly, that is, be changed into low resistance state.When voltage is low
After certain voltage, device can be restored immediately to high-impedance state, that is, gate tube is closed.
As can be seen from Figure 3: when applying 4V pulse, since voltage is greater than threshold voltage, gate tube is in ON state.It can reach
To very high on-state current (11.41mA)；After removing 4V voltage, gate tube is closed, and applies 0.5V voltage pulse again at this time,
Since voltage is less than open voltage, device is in OFF state, and electric current is very small.
Above-mentioned transition process is very rapidly, it is only necessary to 0.1~10ns.This is because material internal in switching process
The change (such as the variation such as phase transformation, metal insulator conversion) in any structure will not occur, so switching speed is significantly faster than
The types of devices such as phase-change memory cell, the threshold switching device based on conductive filament, metal-insulator transition device.Meanwhile it adjusting
The switching speed of the adjustable gate tube of component ratio.
Embodiment 5
A kind of gating tube material, consisting of Ge20Te70Sb10, one is made according to preparation method as described in Example 4
Gating layer, the gating unit as shown in Fig. 1 (e) are made using the gating tube material, the first metal electrode 2 is Pt, with a thickness of
100nm.Using SiO2As insulating layer 3, and with a thickness of 100nm；Gating layer is Ge20Te70Sb10Film, with a thickness of 100nm；Separately
Outer one layer of inert metal electrode 6 is TiN electrode, and with a thickness of 100nm.The gating unit is tested to obtain shown in Fig. 4
Electrology characteristic curve.The threshold voltage of gate tube described in the present embodiment is 0.55V as can be seen from Figure 4, is more excellent.?
Before threshold voltage, with the increase for applying voltage to the gating tube device, the electric current of device is still very small, and device is in
High-impedance state；Only when voltage reaches threshold voltage, the electric current of device can increase suddenly, that is, be changed into low resistance state.Work as electricity
It forces down after certain voltage, device can be restored immediately to high-impedance state, that is, gate tube is closed.
As it will be easily appreciated by one skilled in the art that the foregoing is merely illustrative of the preferred embodiments of the present invention, not to
The limitation present invention, any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should all include
Within protection scope of the present invention.
Claims (9)
1. a kind of gating tube material, which is characterized in that the chemical general formula of the gating tube material is expressed as GexTeyA100-x-y, wherein A
In generation, refers to one of Elements C, B, Si, Al, Sb and Bi, and x, y are the atomic percent of element, and 10≤x < 60,40 < y < 90,0
100-x-y≤25 <.
2. gating tube material as described in claim 1, which is characterized in that GexTeyA100-x-yIn, 20≤x < 45,55 < y≤
70,0 100-x-y≤15 <.
3. gating tube material as described in claim 1, which is characterized in that the gating tube material can be realized high-impedance state to low-resistance
The instantaneous variation of state, and when electric signal lower than a certain size or after remove electric signal can automatic returning to initial high-impedance state.
4. as described in claim 1 gating tube material, which is characterized in that the gating tube material from high-impedance state return to low resistance state or
Person returns to fringe time required for high-impedance state between 0.01~10ns from low resistance state.
5. a kind of gate tube device cell using the gating tube material production as described in Claims 1-4 any one, special
Sign is that the gate tube device cell includes:
First metal electrode layer；
Second metal electrode layer；
Gating layer between first metal electrode layer and second metal electrode layer, the material that the gating layer uses
Material is the gating tube material as described in Claims 1-4 any one.
6. gate tube device cell as claimed in claim 5, which is characterized in that first metal electrode layer and described second
Metal electrode layer is all made of inert electrode material, and the inert electrode material is W, TiW, Pt, Au, Ru, Al, TiN, Ta,
TaN、IrO2, ITO and IZO it is one or more, and first metal electrode layer and the second metal electrode layer are with a thickness of 10nm
To 200nm.
7. gate tube device cell as claimed in claim 5, which is characterized in that the gating layer side and first metal
Electrode layer or second metal electrode layer contact, and the other side of the gating layer is contacted with another metal electrode layer.
8. gate tube device cell as claimed in claim 5, which is characterized in that the gating layer arrives with a thickness of 1nm
200nm。
9. such as the preparation method of the described in any item gate tube device cells of claim 5 to 8, which is characterized in that including as follows
Step:
(1) the first metal electrode layer is prepared on substrate；
(2) insulating layer is prepared on first metal electrode layer, processing is patterned to the insulating layer, obtain hole knot
Structure, and expose by the pore structure the first metal electrode layer of section bottom；
(3) gating layer is prepared on the first metal electrode layer exposed, fills the pore structure, the material that the gating layer uses
Material is the gating tube material as described in Claims 1-4 any one；
(4) the second metal electrode layer is prepared on the insulating layer for be filled with pore structure, makes first metal electrode layer and described
Second metal electrode layer is connected to by gating layer, obtains the gate tube device cell.
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| CN110112290A (en) * | 2019-04-19 | 2019-08-09 | 华中科技大学 | A kind of gate tube and preparation method thereof applied to three-dimensional flash memory memory |
| CN110707209A (en) * | 2019-09-03 | 2020-01-17 | 华中科技大学 | Three-dimensional stacked phase change memory and preparation method thereof |
| CN110797457A (en) * | 2019-10-22 | 2020-02-14 | 华东师范大学 | Preparation method of multilayer storage structure transmission electron microscope in-situ electrical test unit |
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| CN110943102A (en) * | 2019-11-12 | 2020-03-31 | 华中科技大学 | High-density phase change memory three-dimensional integrated circuit structure |
| CN111584710A (en) * | 2020-04-10 | 2020-08-25 | 中国科学院上海微系统与信息技术研究所 | OTS material, gating unit and preparation method thereof |
| CN112018232A (en) * | 2019-05-31 | 2020-12-01 | 中国科学院上海微系统与信息技术研究所 | Gate tube material and gate tube unit comprising same |
| WO2023145795A1 (en) * | 2022-01-28 | 2023-08-03 | 国立大学法人東北大学 | Variable resistance material, switch element material, switch layer, switch element, and storage device |
| WO2024041611A1 (en) * | 2022-08-25 | 2024-02-29 | 华为技术有限公司 | Gating tube material, phase change memory chip, storage device, and electronic device |
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| CN110707209B (en) * | 2019-09-03 | 2022-03-18 | 华中科技大学 | Three-dimensional stacked phase change memory and preparation method thereof |
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| CN110797457A (en) * | 2019-10-22 | 2020-02-14 | 华东师范大学 | Preparation method of multilayer storage structure transmission electron microscope in-situ electrical test unit |
| CN110931636A (en) * | 2019-10-30 | 2020-03-27 | 华中科技大学 | Preparation method of VOx gate tube with novel structure and material |
| CN110931636B (en) * | 2019-10-30 | 2021-07-06 | 华中科技大学 | Preparation method of VOx gate tube with novel structure and material |
| CN110943102A (en) * | 2019-11-12 | 2020-03-31 | 华中科技大学 | High-density phase change memory three-dimensional integrated circuit structure |
| CN110943102B (en) * | 2019-11-12 | 2023-07-18 | 华中科技大学 | Three-dimensional integrated circuit structure of high-density phase change memory |
| CN111584710A (en) * | 2020-04-10 | 2020-08-25 | 中国科学院上海微系统与信息技术研究所 | OTS material, gating unit and preparation method thereof |
| CN111584710B (en) * | 2020-04-10 | 2023-09-26 | 中国科学院上海微系统与信息技术研究所 | OTS material, gate unit and preparation method thereof |
| WO2023145795A1 (en) * | 2022-01-28 | 2023-08-03 | 国立大学法人東北大学 | Variable resistance material, switch element material, switch layer, switch element, and storage device |
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