CN109148556B - Super junction device and manufacturing method thereof - Google Patents

Super junction device and manufacturing method thereof Download PDF

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CN109148556B
CN109148556B CN201710500206.4A CN201710500206A CN109148556B CN 109148556 B CN109148556 B CN 109148556B CN 201710500206 A CN201710500206 A CN 201710500206A CN 109148556 B CN109148556 B CN 109148556B
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contact hole
region
type
contact
polysilicon
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CN109148556A (en
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肖胜安
曾大杰
李东升
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Shenzhen Shangyangtong Technology Co ltd
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Shenzhen Sanrise Tech Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The invention discloses a super junction device, which is provided with a protective ring oxide film surrounding the periphery of a charge flowing area, so that the JFET area and a source area can be completely injected, the aspect ratio of a second contact hole in a transition area is more than or equal to that of a first contact hole in the charge flowing area, and the tungsten plug process is adopted for filling, and meanwhile, the first contact hole and the second contact hole with different aspect ratios are reliably filled. The invention also discloses a manufacturing method of the super junction device. The invention can reliably fill the contact hole in the transition region when the contact hole has higher height-to-width ratio, can form the protective ring oxide film in the transition region and reduce photoetching level by using the protective ring oxide film, is favorable for distributing the contact hole according to the requirement of a device, and simultaneously ensures that the avalanche breakdown resistance of the device is not influenced by the contact hole process in the transition region.

Description

Super junction device and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction (junction) device; the invention also relates to a manufacturing method of the super junction device.
Background
In the existing super junction device, in a charge flowing region, there are P-type columns and N-type columns which are alternately arranged, taking the structure of a strip-shaped P-N column, that is, a P-type column and an N-type column which are alternately arranged as an example, there is a polysilicon gate above each N column, the polysilicon gate may partially cover the peripheral P column or not, there is a P-type well (PWell) above each P column, there is an N + source region in the P-type well, there is a contact hole, a source metal is connected with a source region through the contact hole, the source metal is connected with the P region, that is, the P-type well through a high concentration P + contact region, and the source metal is a front metal layer constituting the source.
Between the charge flow region and the voltage-carrying terminal region, there is a transition region in which a P-type ring region connected to the P-type well of the charge flow region is formed, the P-type ring region having a contact hole formed thereon, and a P + contact region having a high concentration below the contact hole, so that the P-type ring is also connected to the source metal through the P + contact region and the contact hole at the top.
In order to facilitate the design, or to reduce the number of times of photolithography, in the case of performing source region ion implantation using a thick field oxide film as a self-alignment, at least a part of the P-type ring of the transition region needs to be covered by the thick field oxide film, so the aspect ratio of the contact hole on the region covered by the thick oxide film is larger than the minimum aspect ratio of the contact hole of the charge flow region, wherein the contact hole of the charge flow region only needs to pass through the interlayer film, and the contact hole on the region covered by the thick oxide film in the transition region needs to pass through the interlayer film and the thick oxide film at the same time, so the aspect ratio of the contact hole on the region covered by the thick oxide film is larger than the minimum aspect ratio of the contact hole of the charge flow region; in the prior art, when the metal deposition adopts the manufacturing process of Ti, TiN and ALCu, and Ti, TiN and ALSiCu, the metal has limited coverage capability on a metal contact hole, and a metal pinhole appears when metal filling is carried out on a hole with a high aspect ratio such as more than 0.5, so that the performance and reliability of a device are caused.
Disclosure of Invention
The invention aims to solve the technical problem of providing a super junction device, which can perform pinhole-free filling when a contact hole in a transition region adopts a higher height-to-width ratio, thereby forming a protective ring oxide film in the transition region, reducing photoetching levels by using the protective ring oxide film, being beneficial to layout of the contact hole according to the requirements of the device and simultaneously ensuring that the anti-avalanche breakdown capability of the device is not influenced by the contact hole process in the transition region. Therefore, the invention also provides a manufacturing method of the super junction device.
In order to solve the technical problem, the middle region of the super junction device provided by the invention is a charge flowing region, a terminal region surrounds the periphery of the charge flowing region, and a transition region is positioned between the charge flowing region and the terminal region; the method comprises the following steps:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; and filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.
A P-well is formed at the top of each P-type column in the charge flowing region and each P-well extends to the surface of the N-type column on both sides of the corresponding P-type column.
A P-type ring surrounding the charge flowing region is formed on the surface of the super junction structure in the transition region; each of the P-type wells is in contact with the P-type ring.
A first oxide film is formed on the surface of the super junction structure on which the P-type well and the P-type ring are formed, a protective epoxy film is formed by performing photolithography etching on the first oxide film, the protective epoxy film exposes the charge flowing region and at least partially covers the transition region, the protective epoxy film further extends to the surface of the termination region and completely covers the termination region or only exposes the outermost periphery of the termination region, and the protective ring oxide film surrounds the periphery of the charge flowing region.
And a source region consisting of an N + region is formed on the surface of the P-type well of the charge flowing region, and an injection region of the source region is defined by the self-alignment of the guard ring oxide film.
And a first contact hole is formed in the charge flowing region, a second contact hole is formed in the transition region, and the photoetching process of the first contact hole is the same as that of the second contact hole.
The top of the first contact hole and the top of the second contact hole are both connected to a source electrode composed of a front metal layer.
The bottom of the first contact hole penetrates through an interlayer film and the source region and makes contact with the source region and the P-type well.
The second contact holes are distributed in a partial region where the surface of the transition region is covered with the protective epoxy film, and the bottom of the second contact holes penetrates through the interlayer film and the protective ring oxide film and makes contact with the P-type ring.
Setting the ratio of the depth of the first contact hole to the minimum transverse dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole to the minimum transverse dimension as a second aspect ratio; the second aspect ratio is larger than or equal to the first aspect ratio, the first contact hole and the second contact hole are filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capacity and simultaneously realize reliable filling of the first contact hole and the second contact hole with different aspect ratios.
The further improvement is that a planar gate structure formed by overlapping a gate oxide film and a polysilicon gate is formed on the surface of the super junction structure in the charge flowing area, the forming area of the polysilicon gate is defined by a photoetching process, each polysilicon gate covers the corresponding P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel.
The source regions are formed on two sides of the polysilicon gate in the charge flowing region in a self-alignment mode.
Each polysilicon gate is of a strip structure, and the length direction of each polysilicon gate is parallel to the length direction of the groove.
Forming a polysilicon bus on the surface of the protection ring oxide film in the terminal area, wherein each polysilicon gate is connected to the polysilicon bus through a polysilicon connecting line formed on the surface of the protection epoxy film in the transition area, and the polysilicon bus, the polysilicon connecting line and the polysilicon gate are formed simultaneously by adopting the same polysilicon deposition and polysilicon etching processes; the width of the polysilicon connecting line is less than or equal to that of the polysilicon gate.
The further improvement is that each first contact hole is in a strip structure, and the length direction of each first contact hole is parallel to the length direction of the groove; the width of each first contact hole is the minimum transverse dimension.
The array structure is formed by arranging the first contact holes which are in strip structures or more than two first contact holes which are in parallel arrangement and are in strip structures or a plurality of first contact holes which are rectangular in plane view.
The top view surface of each second contact hole is rectangular, the width of each second contact hole is larger than or equal to that of each first contact hole, and one second contact hole is arranged between every two adjacent polysilicon connecting lines or an array structure formed by arranging a plurality of second contact holes is arranged between every two adjacent polysilicon connecting lines.
In a further improvement, the P-type ring completely encloses the second contact hole with a margin of 1 micron or more.
The further improvement is that a third contact hole is formed at the top of the polysilicon bus, and the photoetching process of the first contact hole is the same as that of the third contact hole.
The tops of the third contact holes are connected to a gate electrode composed of a front metal layer.
The bottom of the third contact hole passes through an interlayer film and into the polysilicon bus line and the bottom of the third contact hole stays in or passes through the polysilicon bus line.
In a further improvement, the second contact hole also extends to a partial region of the surface of the transition region not covered with the protective epoxy film, and the bottom of the second contact hole in the partial region makes contact with the P-type ring through the interlayer film.
In a further improvement, a P + contact region is formed at the bottom of each of the first contact holes and each of the second contact holes.
In a further improvement, the process conditions of the P-type well and the P-type ring are the same and are formed simultaneously; alternatively, the process conditions of the P-type ring and the P-type well are independent and separately formed.
In a further improvement, a JFET area is formed on the surface of the super junction structure of the charge flowing area, and the forming area of the JFET area is defined by the guard ring oxide film in a self-aligned mode.
In order to solve the technical problem, the middle area of the super junction device of the manufacturing method of the super junction device provided by the invention is a charge flowing area, a terminal area surrounds the periphery of the charge flowing area, and a transition area is positioned between the charge flowing area and the terminal area; the method comprises the following steps:
step one, providing an N-type epitaxial layer, defining a forming area of a groove by carrying out a first photoetching process, and then carrying out dry etching on the N-type epitaxial layer to form a plurality of grooves.
And filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer among the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns.
And secondly, defining a forming region of a P-type well in the charge flowing region by carrying out a second photoetching process, and then carrying out P-type ion implantation to form the P-type well.
One P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the P-type column.
Forming a P-type ring surrounding the periphery of the charge flow region on the surface of the super junction structure in the transition region by the same process while forming the P-type well; each of the P-type wells is in contact with the P-type ring.
And thirdly, growing a first oxide film on the surface of the super junction structure with the P-type well and the P-type ring, defining an etching area of the first oxide film by a third photoetching process, etching the first oxide film to form a protective ring oxide film, exposing the charge flowing area and at least covering partial area of the transition area by the protective epoxy film, extending the protective epoxy film to the surface of the terminal area and completely covering the terminal area or only exposing the outermost periphery of the terminal area, and surrounding the protective ring oxide film on the periphery of the charge flowing area.
And carrying out overall first N-type ion implantation by taking the guard ring oxide film as a self-alignment condition to form a JFET region in the charge flowing region, and simultaneously forming a terminal first N-type implantation region in or outside the terminal region outside the protection epoxy film covering region.
And step four, sequentially forming a gate oxide film and a first layer of N-type heavily doped polysilicon, defining a forming area of a polysilicon gate by performing a fourth photoetching process, etching the first layer of polysilicon to form polysilicon gates, wherein each polysilicon gate is of a planar gate structure, covers the corresponding P-type well, and is used for forming a channel on the surface of the P-type well covered by the polysilicon gate.
And carrying out comprehensive second N-type ion implantation by taking the polysilicon gate and the guard ring oxide film as self-alignment conditions to form source regions on two sides of the polysilicon gate in the charge flowing region respectively, and simultaneously forming a terminal second N-type implantation region in or outside the terminal region outside the protection epoxy film covering region.
Depositing an interlayer film, and defining forming areas of a first contact hole, a second contact hole and a third contact hole by a fifth photoetching process; then, etching is carried out to form openings of the first contact hole, the second contact hole and the third contact hole; filling metal in the openings of the first contact hole, the second contact hole and the third contact hole to form the first contact hole, the second contact hole and the third contact hole.
The bottom of the first contact hole penetrates through the interlayer film and the source region and makes contact with the source region and the P-type well.
The second contact holes are distributed in a partial region where the surface of the transition region is covered with the protective epoxy film, and the bottom of the second contact holes penetrates through the interlayer film and the protective ring oxide film and makes contact with the P-type ring.
Setting the ratio of the depth of the first contact hole to the minimum transverse dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole to the minimum transverse dimension as a second aspect ratio; the second aspect ratio is larger than or equal to the first aspect ratio, the first contact hole, the second contact hole and the third contact hole are filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capacity to simultaneously realize reliable filling of the first contact hole and the second contact hole with different aspect ratios.
And sixthly, depositing front metal to form a front metal layer, defining forming areas of a grid electrode and a source electrode by carrying out a sixth photoetching process, etching the front metal layer to form the grid electrode and the source electrode, connecting each source region in the charge flowing region and the corresponding P-type well to the source electrode through the first contact hole with the same top, connecting the P-type ring in the transition region to the source electrode through the second contact hole with the same top, and connecting the polysilicon gate to the grid electrode through the third contact hole.
In a further improvement, in the fifth step, after the forming of the openings of the first contact hole, the second contact hole and the third contact hole, before the metal filling, a step of performing P + ion implantation at the bottoms of the first contact hole and the second contact hole to form a P + contact region is further included.
The further improvement is that the interlayer film is composed of an oxide film, in the fifth step, when the openings of the first contact hole, the second contact hole and the third contact hole are formed by etching, the oxide film is etched firstly, when the interlayer film in the first contact hole area is completely removed and the source area at the bottom is exposed, the oxide film is stopped to be etched, and the epitaxial layer material is etched; when the epitaxial layer material is etched, the epitaxial layer at the bottom of the first contact hole is over-etched, and meanwhile, the oxide film in the second contact hole area is partially etched; and performing P + ion implantation of the P + contact region before the oxide film of the second contact hole region is not completely removed, so that the peak value of the P + ion implantation of the P + contact region of the second contact hole region is positioned in the oxide film, and after the openings of the first contact hole, the second contact hole and the third contact hole and the metal filling are completely finished, the peak value of the doping concentration of the P + contact region at the bottom of the second contact hole is smaller than the peak value of the doping concentration of the P + contact region at the bottom of the first contact hole.
The further improvement is that the doping concentration of the P + contact zone at the bottom of the second contact hole is adjusted by adjusting the thickness of an oxide film positioned at the bottom of the second contact hole area when P + ions of the P + contact zone are implanted, and the peak value of the doping concentration of the P + contact zone at the bottom of the second contact hole is 1/2-1/10 of the peak value of the doping concentration of the P + contact zone at the bottom of the first contact hole.
In a further improvement, in the second step, the P-type ring is formed by adopting separate photoetching and ion implantation processes, and the forming process of the P-type ring is positioned before the forming process of the P-type well.
A further improvement is that in the fourth step, a polysilicon bus is formed on the surface of the protective epoxy film in the termination region and a polysilicon connection line is formed on the surface of the protective epoxy film in the transition region while the polysilicon gates are formed, each polysilicon gate is connected to the polysilicon bus through the polysilicon connection line, and the width of the polysilicon connection line is less than or equal to the width of the polysilicon gate.
And fifthly, the third contact hole is positioned at the top of the polycrystalline silicon bus, the bottom of the third contact hole penetrates through an interlayer film and enters the polycrystalline silicon bus, and the bottom of the third contact hole stays in the polycrystalline silicon bus or penetrates through the polycrystalline silicon bus.
And fifthly, protecting the third contact hole region by adopting a photoetching process when injecting the P + ions of the P + contact region.
The invention makes special design for the filling process of the contact hole, and specially adopts the tungsten plug filling process to fill the contact hole, compared with the existing process for filling the contact hole by adopting metal AlCu or AlSiCu, the tungsten plug filling process can fill the contact holes with various aspect ratios without pinholes, thus the invention can adopt the contact hole with higher aspect ratio than a charge flowing area, namely the second contact hole, on a transition area, and the second contact hole can simultaneously penetrate through a protective ring oxide film and an interlayer film in the longitudinal direction, and simultaneously can ensure that no pinhole exists.
The invention can ensure that the second contact hole is not filled with pinholes, so the invention can realize that the protective ring oxide film is arranged in the transition region under the condition of ensuring that the contact hole realizes good filling, is favorable for the protective ring oxide film to realize the self-aligned injection of the source region and the JFET region, and can further ensure that the invention adopts the process of saving photoetching layers, namely, the invention can save the photoetching process of forming the source region and the JFET region, thereby reducing the manufacturing cost and shortening the production period.
In addition, on the transverse structure of the top view surface, the transverse size and distribution of the second contact holes can be distributed according to the requirements of the device, so the invention can realize convenient arrangement of the second contact holes, and finally can ensure that the avalanche breakdown resistance of the device is not influenced or improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a top view of a trench formation region of a super junction device according to a first embodiment of the present invention;
fig. 2 is a top view of a formation region of a P-type well of the super junction device according to the first embodiment of the present invention;
fig. 3 is a plan view of a formation region of a guard ring oxide film of the super junction device according to the first embodiment of the present invention;
fig. 4 is a top view of a formation region of a polysilicon gate of a super junction device according to a first embodiment of the present invention;
fig. 5 is a top view of a formation region of a contact hole of the super junction device according to the first embodiment of the present invention;
fig. 6 is a top view of a formation area of a source and a gate formed of a front metal layer of the super junction device according to the first embodiment of the present invention;
fig. 7 is a schematic cross-sectional view of the superjunction device of the first embodiment of the present invention taken along line A1a2 of fig. 6;
fig. 8 is a schematic cross-sectional view of the superjunction device of the first embodiment of the present invention taken along line B1B2 of fig. 6;
fig. 9 is a schematic cross-sectional view of the superjunction device of the first embodiment of the present invention taken along line C1C2 of fig. 6;
fig. 10 is a schematic cross-sectional view of the superjunction device of the first embodiment of the present invention taken along line D1D2 of fig. 6;
fig. 11 is a top view of a formation region of a contact hole of a superjunction device according to a second embodiment of the present invention;
fig. 12 is a top view of a formation region of a contact hole of a super junction device according to a third embodiment of the present invention;
fig. 13 is a top view of a formation region of a contact hole of a superjunction device according to a fourth embodiment of the present invention;
fig. 14 is a top view of a formation region of a contact hole of a superjunction device according to a fifth embodiment of the present invention;
fig. 15 is a flowchart of a method of manufacturing a super junction device of the first embodiment of the present invention;
fig. 16A to 16D are structural views of contact holes in the steps of the tungsten plug process in the method according to the first embodiment of the present invention.
Detailed Description
The first embodiment of the invention is a super junction device:
as shown in fig. 6, is a top view of a formation region of the source electrode 7a and the gate electrode 7b formed of the front metal layer of the super junction device according to the first embodiment of the present invention; in order to more clearly explain the structure of the device according to the first embodiment of the present invention, the structure is also described with reference to fig. 1 to 5 and fig. 7 to 10, and the following details are described:
the super junction device of the first embodiment of the present invention is described by taking a super junction MOSFET as an example, the middle region of the super junction device of the first embodiment of the present invention is a charge flowing region, a terminal region surrounds the periphery of the charge flowing region, and a transition region is located between the charge flowing region and the terminal region; a super junction device of a first embodiment of the present invention includes:
the manufacturing method comprises the following steps that an N-type epitaxial layer 1 is subjected to dry etching to form a plurality of grooves; and filling a P-type epitaxial layer in the groove to form a P-type column 2, forming an N-type column by the N-type epitaxial layer 1 between the P-type columns 2, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns 2. Fig. 1 is a plan view of a super junction structure, and fig. 1 clearly shows an alternate arrangement structure of the N-type columns and the P-type columns 2.
One P-type well 3 is formed at the top of each P-type column 2 in the charge flowing region and each P-type well 3 extends to the surface of the corresponding N-type column on both sides of the P-type column 2.
A P-type ring 4 surrounding the charge flowing region is formed on the surface of the super junction structure in the transition region; each of the P-type wells 3 is in contact with the P-type ring 4. Referring to fig. 2, fig. 2 is a partial top view, and the P-type well 3 and the P-type ring 4 are actually surrounded by the P-type ring 4. In the first embodiment of the present invention, the process conditions of the P-well 3 and the P-type ring 4 are the same and formed simultaneously. In other embodiments, this can also be: the process conditions of the P-type ring 4 and the P-type well 3 are independent and separately formed.
A first oxide film is formed on the surface of the super junction structure on which the P-type well 3 and the P-type ring 4 are formed, a protective epoxy film 103 is formed by photolithography etching of the first oxide film, the protective epoxy film 103 exposes the charge flowing region and covers at least a part of the transition region, the protective ring oxide film 103 further extends to the surface of the termination region and covers the termination region entirely or exposes only the outermost periphery of the termination region, and the protective ring oxide film 103 surrounds the periphery of the charge flowing region. Referring to fig. 7, a specific structure of the protective epoxy film 103 is shown, and a region of the protective epoxy film 103 is shown in a top view in fig. 3, where a line M1M2 in fig. 3 indicates the region of the protective epoxy film 103, a left side of a line M1M2 is the region of the protective epoxy film 103, a right side of a line M1M2 is not formed with the protective epoxy film 103, and actually, a left side of the line M1M2 is a direction pointing to a termination region, and a right side of the line M1M2 is a direction pointing to a charge flow region. As shown in fig. 3, the protective epoxy film 103 does not completely cover the P-type ring 4.
A planar gate structure formed by superposing a gate oxide film and a polysilicon gate 5a is formed on the surface of the super junction structure of the charge flowing region, the forming region of the polysilicon gate 5a is defined by a photoetching process, each polysilicon gate 5a covers the corresponding P-type well 3, and the surface of the P-type well 3 covered by the polysilicon gate 5a is used for forming a channel.
The source regions 106 are self-aligned on both sides of the polysilicon gate 5a in the charge flow region.
Each of the polysilicon gates 5a has a strip structure, and the length direction of each of the polysilicon gates 5a is parallel to the length direction of the trench.
A polysilicon bus 5c is formed on the surface of the protective epoxidation film 103 in the terminal region, each polysilicon gate 5a is connected to the polysilicon bus 5c through a polysilicon connecting line 5b formed on the surface of the protective epoxidation film 103 in the transition region, and the polysilicon bus 5c, the polysilicon connecting line 5b and the polysilicon gate 5a are formed simultaneously by the same polysilicon deposition and polysilicon etching processes; the width of the polysilicon connecting line 5b is less than or equal to the width of the polysilicon gate 5 a.
Fig. 4 is a top view of the polysilicon bus 5c, the polysilicon connecting line 5b, and the polysilicon gate 5 a.
A source region 106 composed of an N + region is formed on the surface of the P-well 3 of the charge flowing region, referring to fig. 10, the source region 106 is self-aligned to two sides of the polysilicon gate 5a formed in the charge flowing region; therefore, the formation region of the source region 106 is defined by self-aligning the polysilicon gate 5a and the protective epoxy film 103, wherein the protective ring oxide film 103 can protect the outside of the charge flow region, and the polysilicon gate 5a self-aligns the source region 106 on both sides of the polysilicon gate 5a, so that the first embodiment of the present invention does not need to additionally use a photolithography process to define the source region 106, and a layer of mask for defining the source region 106 can be saved.
As shown in fig. 5, a first contact hole 6a is formed in the charge flow region, a second contact hole 6b is formed in the transition region, and a third contact hole 6c is formed at the top of the polysilicon bus line 5c, and the first contact hole 6a, the second contact hole 6b, and the third contact hole 6c are formed at the same time by the same photolithography process.
As shown in fig. 6, the tops of the first contact hole 6a and the second contact hole 6b are connected to a source electrode 7a composed of a front metal layer. The tops of the third contact holes 6c are all connected to the gate electrode 7b composed of the front-side metal layer. In fig. 6, in order to show that the underlying structures of the source 7a and the gate 7b are only drawn by a line frame, and the corresponding patterns are not filled, the schematic regions of the source 7a and the gate 7b in fig. 7 are represented by filled patterns.
The bottom of the first contact hole 6a penetrates through an interlayer film 104 and the source region 106 and makes contact with the source region 106 and the P-type well 3.
The second contact holes 6b are distributed in a partial region where the surface of the transition region is covered with the protective epoxy film 103, and the bottom of the second contact holes 6b pass through the interlayer film 104 and the protective ring oxide film 103 and make contact with the P-type ring 4.
The bottom of the third contact hole 6c passes through the interlayer film 104 and enters the polysilicon bus line 5c and the bottom of the third contact hole 6c stays in the polysilicon bus line 5c, and the polysilicon bus line 5c can be passed through for the bottom of the third contact hole 6c in other embodiments. Fig. 7 shows the sectional structures of the first contact hole 6a, the second contact hole 6b, and the third contact hole 6c, fig. 8 shows the sectional structure of the third contact hole 6c alone, fig. 9 shows the sectional structure of the second contact hole 6b alone, and fig. 10 shows the sectional structure of the first contact hole 6a alone.
Setting the ratio of the depth of the first contact hole 6a to the minimum lateral dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole 6b to the minimum lateral dimension as a second aspect ratio; the second aspect ratio is greater than or equal to the first aspect ratio, the first contact hole 6a and the second contact hole 6b are both filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capability and simultaneously realize reliable filling of the first contact hole 6a and the second contact hole 6b with different aspect ratios.
As shown in fig. 6, each of the first contact holes 6a has a strip-shaped structure, and a length direction of each of the first contact holes 6a is parallel to a length direction of the trench; the width of each of the first contact holes 6a is a minimum lateral dimension.
Each two adjacent polysilicon gates 5a include one first contact hole 6a having a strip structure therebetween.
The plan view surface of each second contact hole 6b is rectangular, the width of each second contact hole 6b is equal to the width of each first contact hole 6a, and an array structure formed by arranging a plurality of second contact holes 6b is arranged between every two adjacent polysilicon connecting lines 5 b. The second contact hole 6b having a width equal to that of the first contact hole 6a is a structure used in the related art, and in other embodiments, a structure in which the second contact hole 6b has a width greater than that of the first contact hole 6a may be used. The area of the contact holes of the total transition region can be increased by the array structure formed by arranging the plurality of second contact holes 6b between every two adjacent polysilicon connecting lines 5b, so that the carrier collecting capability of the transition region can be improved.
In the first embodiment of the present invention, it is required to ensure that the P-type ring 4 completely encloses the second contact holes 6b and ensure that the margin is greater than or equal to 1 micron, that is, the outer edge of each second contact hole 6b is located inside the edge of the corresponding P-type ring 4, and the interval between the outer edge of each second contact hole 6b and the edge of the corresponding P-type ring 4 is greater than or equal to 1 micron.
In the device of the first embodiment of the present invention, the interval between each second contact hole 6b and the adjacent polysilicon is greater than or equal to 0.2 μm; the polysilicon adjacent to the second contact hole 6b includes the polysilicon bus line 5c, the polysilicon link line 5b, and the polysilicon gate 5 a.
As shown in fig. 10, P + contact regions 107 are formed at the bottoms of the first contact holes 6a and the second contact holes 6 b.
A JFET region 102 is formed on the surface of the super junction structure of the charge flowing region, the formation region of the JFET region 102 is defined by the guard ring oxide film 103 in a self-aligned manner, and the JFET region 102 is an ion implantation region, and an implantation position is indicated by a dotted line in fig. 10.
As shown in fig. 7, the N-type epitaxial layer 1 is formed on a surface of a semiconductor substrate 101, such as a silicon substrate, the silicon substrate is in an N-type heavily doped structure and is located in a drain region of the superjunction device, and a drain 105 composed of a back metal layer is formed on a back surface of the drain region.
In the super junction device according to the first embodiment of the present invention, a 600V super junction MOSFET is taken as an example to describe the parameters in detail:
the resistivity of the semiconductor substrate 101 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 1 is 1-2 ohm.cm, and the thickness is 30-70 micrometers, preferably 40-60 micrometers. In the first embodiment of the present invention, the semiconductor substrate 101 is a silicon substrate, and the N-type epitaxial layer 1 is a silicon epitaxial layer.
As can be seen from a comparison between fig. 9 and fig. 10, the dielectric film passed through by the first contact hole 6a is only the interlayer film 104, and the dielectric film passed through by the second contact hole 6b includes the interlayer film 104 and the guard ring oxide film 103, so that the dielectric film passed through by the first contact hole 6a is thinner, and since the first contact hole 6a and the second contact hole 6b are formed simultaneously by using the same photolithography and etching process, in the first embodiment of the present invention, the first contact hole 6a needs to over-etch the silicon at the bottom, i.e., the silicon of the N-type epitaxial layer 1, after passing through the interlayer film 104, and the etching amount thereof needs to reach or exceed the depth of the source region 106; the second contact hole 6b only needs to penetrate the interlayer film 104 and the guard ring oxide film 103 to expose the surface of the P-type ring 4, and the second contact hole 6b is not limited to whether the silicon at the bottom is over-etched.
In the first embodiment of the present invention, the thickness of the interlayer film 104 is 8000 a to 10000 a, and the thickness of the protective epoxy film is 8000 a to 10000 a. When the width of the first contact hole 6a takes 0.6 micrometers, the width of the second contact hole 6b is also 0.6 micrometers.
In the super junction device according to the first embodiment of the present invention, a tungsten plug process is particularly adopted to fill the first contact hole 6a and the second contact hole 6b, and the tungsten plug process is utilized to ensure hole covering capability and simultaneously realize reliable filling of the first contact hole 6a and the second contact hole 6b having different aspect ratios. The difference between the tungsten plug process and the process of filling the contact hole with AlCu in the prior art is described as follows:
1. when the W plug process is not adopted, an ALCu pinhole is easy to appear when the general height-to-width ratio is more than 0.5, and the existence of the pinhole can cause that the metal in a contact hole is local, the ALCU is thin, and the reliability problem of a product is caused.
2. In the device provided by the embodiment of the invention, after the W plug process is adopted, the tungsten plug process has good covering capability on the contact hole, so that a flattened surface can be formed at the top of the contact hole after the contact hole is filled by the tungsten plug process, and AlCu is deposited on the flattened surface when an ALCu deposition is subsequently carried out to form a front metal layer, so that the thickness of the ALCU is uniform everywhere, the problem that the ALCU is thin in a metal area in the contact hole is avoided, and the reliability of the contact hole is ensured.
3. For the W plug process itself, in fact, it is generally pinhole-like, and the W plug center generally has a very thin slit, and may have a Void (Void) in the middle. However, this does not affect the reliability of the contact hole because there is some Void in the middle of the W plug on a flat surface when ALCu is deposited, there is a small gap in the center of the W plug, which is usually filled when Ti and TiN are deposited, and ALCU can be deposited well.
By adopting the tungsten plug process, for the contact hole with the height-width ratio smaller than 10, the filling problem can not occur, and in the first embodiment of the invention: the width of the first contact hole 6a is 0.6 μm, and the thickness of the interlayer film 104 is
Figure GDA0003072565990000123
The aspect ratio of the first contact hole 6a is 1.33; if the thickness of the thick field oxide film, i.e., the protective epoxy film 103, is set to be as thick as
Figure GDA0003072565990000124
The minimum size or width of the contact hole in the transition region, i.e. the second contact hole 6b, is 0.6 microns, so that the aspect ratio of the contact hole is 2.67 and is less than 10, therefore, the filling problem is not existed, and the pinhole-free filling can be realized.
The second embodiment of the invention is a super junction device:
as shown in fig. 11, is a top view of a formation region of a contact hole of the superjunction device of the second embodiment of the present invention; the second embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: the second contact holes 6a in fig. 11 are all placed in the transition region to the protective epoxy film 103, that is, all of the second contact holes 6a are left of the boundary line M1M2 in the plan view of fig. 11, and the structure shown in fig. 12 is convenient in design.
The third embodiment of the invention is a super junction device:
as shown in fig. 12, is a top view of a formation region of a contact hole of the super junction device according to the third embodiment of the present invention; the third embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: the second contact hole 6a is expanded in fig. 12 into the transition region without the guard ring oxide film 103, as the second contact hole 6a shown in the region of the dashed circle 13 in fig. 12, and the bottom of the second contact hole 6b in this partial region comes into contact with the P-type ring 4 through the interlayer film 104. The structure shown in fig. 12 can maximize the area of the second contact hole 6 a.
The fourth embodiment of the invention is a super junction device:
as shown in fig. 13, is a top view of a formation region of a contact hole of a superjunction device according to a fourth embodiment of the present invention; the fourth embodiment superjunction device of the present invention is different from the first embodiment superjunction device of the present invention in that: in fig. 13, the width of the polysilicon line 5b is the same as that of the polysilicon gate 5a and is formed by directly extending the polysilicon gate 5 a.
The super junction device of the fifth embodiment of the present invention:
as shown in fig. 14, is a top view of a formation region of a contact hole of a super junction device according to a fifth embodiment of the present invention; the fifth embodiment superjunction device of the present invention is different from the fourth embodiment superjunction device of the present invention in that: in fig. 14, each two adjacent polysilicon gates 5a include more than two first contact holes 6a arranged in parallel and in a stripe structure. In other embodiments, this can also be: a plurality of first contact holes 6a with a rectangular plane of view are arranged between every two adjacent polysilicon gates 5a to form an array structure.
The manufacturing method of the super junction device of the first embodiment of the invention comprises the following steps:
as shown in fig. 15, is a flowchart of a method of manufacturing a super junction device according to the first embodiment of the present invention; the manufacturing method of the super junction device according to the first embodiment of the present invention is used for manufacturing the above-mentioned super junction device according to the first embodiment of the present invention, the middle region of the super junction device is a charge flowing region, a terminal region surrounds the periphery of the charge flowing region, and a transition region is located between the charge flowing region and the terminal region; the method comprises the following steps:
step one, as shown in fig. 1, providing an N-type epitaxial layer 1, performing a first photolithography process to define a formation region of a trench, and then performing dry etching on the N-type epitaxial layer 1 to form a plurality of trenches.
And filling a P-type epitaxial layer in the groove to form a P-type column 2, forming an N-type column by the N-type epitaxial layer 1 among the P-type columns 2, and forming a super junction structure by a plurality of alternately arranged N-type columns and the P-type columns 2.
In the method of the first embodiment of the present invention, the manufactured super junction device is a super junction MOSFET as an example for detailed description: the N-type epitaxial layer 1 is formed on the surface of a semiconductor substrate 101, and the semiconductor substrate 101 adopts an N-type heavily doped structure; preferably, the N-type epitaxial layer 1 is a silicon epitaxial layer, and the semiconductor substrate 101 is a silicon substrate, which is also known as a silicon wafer or a silicon wafer. The drain region of the super junction MOSFET is usually formed on the back surface of the semiconductor substrate 101, so the heavily doped semiconductor substrate 101 is directly used, and in the method according to the first embodiment of the present invention, the resistivity of the semiconductor substrate 101 is 0.001-0.003 ohm cm; the resistance of the N-type epitaxial layer 1 is 1-2 ohm.cm, the thickness is 30-70 micrometers, and preferably 40-60 micrometers; P-N column region is super junction structure region: when the source-drain breakdown voltage BVds of the corresponding device is 600V-700V, the height of the super junction structure is 35 micrometers-45 micrometers. In the method according to the first embodiment of the present invention, to ensure that a buffer layer with a certain thickness, for example, more than 5 μm, is provided between the trench and the high-concentration semiconductor substrate 101 to maintain the device with a good current surge resistance, the buffer layer is generally directly formed by the N-type epitaxial layer 1 located at the bottom of the trench.
In the method according to the first embodiment of the present invention, before the first photolithography process, a step of forming a first dielectric film on the surface of the N-type epitaxial layer is further included, and after the first photolithography process, dry etching is sequentially performed on the first dielectric film and the N-type epitaxial layer 1 to form a plurality of trenches.
After the P-type epitaxial layer is filled in the groove, a Chemical Mechanical Polishing (CMP) process is carried out to remove the P-type epitaxial layer on the surface of the N-type epitaxial layer 1, so that the P-type epitaxial layer is only filled in the corresponding groove 1 and forms the P-type column 2; and removing or partially retaining the first dielectric film after the chemical mechanical polishing process is finished.
In the method according to the first embodiment of the present invention, the composition material of the first dielectric film and the corresponding process method can be selected as follows:
the first option is: the first dielectric film is a single oxide film, for example, an oxide film with a thickness exceeding 1 micron, the oxide film can be used as a hard mask during trench etching, an oxide film with a certain thickness is left after trench formation, for example, an oxide film with a thickness of 0.1 micron to 0.2 micron, and during the process of performing epitaxial filling and CMP, the oxide film is used as a protective layer of an N-type epitaxial layer 1 during CMP, so that silicon at the position cannot form defects in the CMP process, and leakage or quality problems are caused.
The second option is: the first dielectric film is composed of a layer of oxide film with the thickness of 0.1-0.15 micron, a layer of SIN film with the thickness of 0.1-0.2 micron and an oxide film with the thickness of the top layer being more than 1 micron, and the first dielectric film is a multilayer film structure; this allows for better control of uniformity during fabrication: for example, after the trench etching is completed, at least a part of the SIN film is remained on the oxide film thereunder, and before the epitaxial growth, the SIN film is removed, so that the uniformity of the oxide film before the epitaxial growth is good, and the uniformity of CMP for the epitaxy can be improved. A further improvement of the above-described multilayer film structure is that the first oxide film is formed by thermal oxidation, which further improves uniformity.
Step two, as shown in fig. 2, a second photolithography process is performed to define a formation region of the P-type well 3 in the charge flowing region, and then P-type ion implantation is performed to form the P-type well 3.
One P-type well 3 is formed at the top of each P-type column 2 in the charge flowing region, and each P-type well 3 extends to the surface of the corresponding N-type column on both sides of the P-type column 2.
Forming a P-type ring 4 surrounding the periphery side of the charge flowing region on the surface of the super junction structure in the transition region by the same process while forming the P-type well 3; each of the P-type wells 3 is in contact with the P-type ring 4.
And after the P-type ion implantation of the P-type well 6 is finished, carrying out an annealing process on the P-type well 6, wherein the annealing process has the temperature of more than 1000 ℃ and the time of more than 30 minutes.
The process conditions of the P-type well 6 need to meet the requirement of the threshold voltage of the device, and for the device with the threshold voltage requirement of 2-4V, the process conditions of B30-100 KEV and 3-10E13/cm2 can be adopted, namely, the impurity is implanted into boron (B), the implantation energy is 30-100Kev, and the implantation dosage is 3E13cm-2～10E13cm-2(ii) a Meanwhile, when the breakdown voltage of the device occurs, source-drain Punch-through (Punch through) does not occur at the channel, otherwise, the device has large leakage and low breakdown voltage.
Step three, as shown in fig. 3, a first oxide film is grown on the surface of the super junction structure on which the P-type well 3 and the P-type well 4 are formed, a third photolithography process is performed to define an etching region of the first oxide film, then the first oxide film is etched to form a guard ring oxide film 103, the guard ring oxide film 103 exposes the charge flowing region and covers at least a partial region of the transition region, the guard ring oxide film 103 further extends to the surface of the termination region and covers the termination region entirely or exposes only the outermost peripheral portion of the termination region, and the guard ring oxide film 103 surrounds the peripheral side of the charge flowing region.
Preferably, the first oxide film is formed by a thermal oxidation process at a temperature higher than 800 ℃, so that dangling bonds and unstable interface states can be reduced at the Si-SiO2 interface, the voltage bearing capability of the terminal region is further improved, and the breakdown voltage consistency of the device is improved. The thickness of the first oxide film is required to be set according to the magnitude of the device BVds, namely the source-drain breakdown voltage, generally, the larger the BVds is, the thicker the thickness of the first oxide film is required to be, and generally, the thickness of the first oxide film required by the device with the voltage of 600V or more is more than 0.8 μm.
And carrying out first N-type ion implantation on the whole surface by taking the guard ring oxide film 103 as a self-alignment condition to form a JFET region 102 in the charge flowing region, and simultaneously forming a first N-type terminal implantation region in or outside the terminal region outside the coverage region of the guard ring oxide film 103.
In the method of the first embodiment of the present invention, since the transition region and the termination region are protected by the guard ring oxide film 7, JFET implantation can be performed without photolithography, which saves the cost of the photolithography process, because if a JFET is implanted into the termination region, BVds of the device is significantly reduced, and if a JFET is implanted into the transition region, the current impact resistance of the device is reduced.
In the method according to the first embodiment of the present invention, the process condition of the first N-type ion implantation corresponding to the JFET region is phosphorus (phos),30-100Kev 1-4E13/cm2, that is: the implantation impurity is phosphorus, the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 1E13cm-2～4E13cm-2(ii) a Or, in the third step, the first N-type ion implantation corresponding to the JFET region is formed by a combination of two implantations with implantation energies of 30Kev to 60Kev and 1Mev to 1.5Mev, and the high-energy implantation can further reduce the specific on-resistance of the device, improve the charge balance around the P-type well 6, increase the Bvds of the device, and perform experimental verification to obtain: for a 600V device, Bvds can be improved by 10V-20V.
And step four, as shown in fig. 4, sequentially forming a gate oxide film and a first layer of N-type heavily doped polysilicon, performing a fourth photolithography process to define a formation region of a polysilicon gate 5a, then etching the first layer of polysilicon to form a polysilicon gate 5a, wherein each polysilicon gate 5a is a planar gate structure, each polysilicon gate 5a covers the corresponding P-type well 3, and the surface of the P-type well 3 covered by the polysilicon gate 5a is used for forming a channel.
And forming a polysilicon bus 5c on the surface of the protective epoxidation film 103 in the termination region and a polysilicon connection line 5b on the surface of the protective epoxidation film 103 in the transition region while forming the polysilicon gates 5a, wherein each polysilicon gate 5a is connected to the polysilicon bus 5c through the polysilicon connection line 5b, and the width of the polysilicon connection line 5b is less than or equal to the width of the polysilicon gate 5 a. When the width of the polysilicon connecting line 5b is smaller than that of the polysilicon gate 5a, the contact hole distribution area of the transition region can be conveniently enlarged, and the metal leakage of the gate and the source can not be caused. That is, the polysilicon bus (gate bus) may cover or partially cover the guard ring dielectric film in the transition region, and there may be poly-crystals isolated from each other in the termination region to serve as field plates for terminating the flat electric field.
And performing a second N-type ion implantation on the polysilicon gate 5a and the protective epoxy film 103 as a self-aligned condition to form source regions 106 on both sides of the polysilicon gate 5a in the charge flowing region, and simultaneously forming a second N-type terminal implantation region in or outside the terminal region outside the region covered by the protective ring oxide film 103.
The second N-type injection region of the terminal can be used for preventing the surface inversion of the terminal region, and the stability of the breakdown characteristic of the device is better improved. The termination second N-type implant region can also be formed in the outermost peripheral termination region of the device, also serving as a termination region.
Preferably, the implantation impurities of the second N-type ion implantation corresponding to the source region 106 are arsenic, phosphorus, or a combination of arsenic and phosphorus, and the process conditions of the second N-type ion implantation including arsenic implantation during arsenic implantation are as follows: the implantation energy is 30 Kev-100 Kev, and the implantation dosage is 1E15cm-2～5E15cm-2。
Step five, as shown in fig. 6, depositing an interlayer film 104, and performing a fifth photolithography process to define formation regions of the first contact hole 6a, the second contact hole 6b, and the third contact hole 6 c; then, etching is carried out to form openings of the first contact hole 6a, the second contact hole 6b and the third contact hole 6 c; the first contact hole 6a, the second contact hole 6b, and the third contact hole 6c are formed by filling metal into openings of the first contact hole 6a, the second contact hole 6b, and the third contact hole 6 c.
The bottom of the first contact hole 6a penetrates the interlayer film 104 and the source region 106 and makes contact with the source region 106 and the P-type well 3.
The second contact holes 6b are distributed in a partial region where the surface of the transition region is covered with the protective epoxy film 103, and the bottom of the second contact holes 6b pass through the interlayer film 104 and the protective ring oxide film 103 and make contact with the P-type ring 4.
The third contact hole 6c is located at the top of the polysilicon bus line 5c, the bottom of the third contact hole 6c passes through the interlayer film 104 and into the polysilicon bus line 5c and the bottom of the third contact hole 6c stays in the polysilicon bus line 5c or passes through the polysilicon bus line 5 c.
Setting the ratio of the depth of the first contact hole 6a to the minimum lateral dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole 6b to the minimum lateral dimension as a second aspect ratio; the second aspect ratio is greater than or equal to the first aspect ratio, the first contact hole 6a, the second contact hole 6b and the third contact hole 6c are all filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capability and simultaneously realize reliable filling of the first contact hole 6a and the second contact hole 6b with different aspect ratios.
As shown in fig. 16A to 16D, which are structural diagrams of the contact hole in each step of the tungsten plug process in the method according to the first embodiment of the present invention, the tungsten plug process includes the following steps:
as shown in fig. 16A, after the opening of the contact holes, i.e., the first contact hole 6A, the second contact hole 6b, and the third contact hole 6c, is completed, a Ti and TiN blocking layer 201 is deposited. Thereafter, as shown in fig. 16B, the contact hole is filled by depositing the metal tungsten 202, and if the opening width of the contact hole is 0.6 μm, the thickness of the metal tungsten 202 can be 4000 angstroms. Then, as shown in fig. 16C, a plasma dry etching back process is performed to remove all the metal on the surface outside the contact hole. Next, fig. 16D shows the front metal layer 203 formed in the sixth subsequent step, and the front metal layer 203 is patterned to form the source electrode 7a and the gate electrode 7 b.
In the method of the first embodiment of the present invention, the tungsten plug process is adopted to fill the contact holes with different aspect ratios without using the pin holes.
In the method according to the first embodiment of the present invention, the interlayer film 104 is a combination of an undoped oxide film and a BPSG film. The thickness of the interlayer film 104 is
Figure GDA0003072565990000171
The second contact hole 6b realizes the connection between the source electrode 7a formed by the subsequent front metal layer and the protection ring P-type well 6 region in the transition region, thereby ensuring that the device terminal structure with the same size can bear the same voltage as the prior art in the method of the first embodiment of the invention.
In the etching of the contact hole, N + at the bottom of the first contact hole 6a in the charge flow region, namely the source region 106, needs to be etched, namely, over-etching of silicon is needed, the over-etching amount of silicon can be 2000 angstroms to 4000 angstroms, and the over-etching amount of silicon specifically needs to be determined according to the implantation conditions, namely, implantation dose and implantation energy, of the second N-type ion implantation corresponding to the source region 106; in the transition region, the second contact hole 6b only needs to pass through the interlayer film 104 and the guard ring oxide film 103, and silicon over-etching may not be performed, and the amount of silicon over-etching is 0 to 500 angstroms.
Because the first contact hole 6a in the charge flowing region penetrates through the range of the N +, namely the source region 106, the contact problem between the P-type well 3 and metal caused by the overall injection of the source region 106 outside the polysilicon gate 5a can be avoided, and the normal electrical characteristics can be ensured.
After the openings of the first contact hole 6a, the second contact hole 6b and the third contact hole 6c are formed, the step of filling metal is further included before the step of forming the openings of the first contact hole 6a and the second contact hole 6bb is subjected to a P + ion implantation to form a P + contact region 107. And when the P + ions of the P + contact region 107 are implanted, a photoetching process is adopted to protect the region of the third contact hole 6 c. The contact resistance of the first contact hole 6a and the second contact hole 6b is reduced by the P + contact region 107. Preferably, the P-type dopant of the P + contact region 107 is B, BF2, or a combination of B and BF2, and the typical implantation energy is 30Kev to 80Kev, and the implantation dose is 1E15cm-2～3E15cm-2The current surge resistance of the device can be improved by optimizing the injection conditions. In order to better improve the softness of the reverse recovery process of the body diode, the energy and dose of the P-type implantation of the P + contact region 107 can also be reduced, for example, the energy can be BF2, 5 Kev-40 KEV, 5E14 cm-2～2E15 cm-2The dose is selected so that the energy is selected primarily to take into account the capabilities of the ion implantation equipment in order to ensure the minimum dose to form the ohmic contacts.
And sixthly, depositing front metal to form a front metal layer, defining forming regions of a grid electrode 7b and a source electrode 7a by performing a sixth photoetching process, etching the front metal layer to form the grid electrode 7b and the source electrode 7a, connecting each source region 106 in the charge flowing region and the corresponding P-type well 3 to the source electrode 7a through the first contact hole 6a with the same top, connecting the P-type ring 4 in the transition region to the source electrode 7a through the second contact hole 6b with the same top, and connecting the polysilicon gate 5a to the grid electrode 7b through the third contact hole 6 c.
The front side metal layer 14 can be of a material such as ALSi or AlSiCu, and can have a barrier layer, which can be Ti/TIN or TIN. The total thickness of the front metal layer 14 is generally 4 μm to 6 μm.
And then thinning the back surface of the semiconductor substrate 101, and forming a drain region by using the N + region formed in the thinned semiconductor substrate 101, wherein the drain region can be directly formed by the heavily doped semiconductor substrate 101 or formed by injecting the heavily doped semiconductor substrate 101 and N-type heavily doped ions. And then depositing a back metal layer on the back of the semiconductor substrate 101, namely the drain region to form a drain electrode 105.
After the above steps, the super junction device according to the first embodiment of the present invention is formed.
In the manufacturing process corresponding to the method of the first embodiment of the present invention, the device that can be obtained only by 8 times of photolithography in the prior art is realized by using six times of photolithography including trench photolithography, i.e., first photolithography, P-type well photolithography, i.e., second photolithography, protective epoxy film photolithography, i.e., third photolithography, polycrystalline photolithography, i.e., fourth photolithography, contact hole photolithography, i.e., fifth photolithography, and front metal photolithography, i.e., sixth photolithography, that is, the method of the first embodiment of the present invention saves JFET implantation photolithography and source implantation photolithography. Therefore, the method of the first embodiment of the present invention reduces the manufacturing cost. In order to ensure the production stability in production, 0 layer of photoetching and/or mark layer photoetching can be added before the groove photoetching, so that an alignment mark and an alignment precision test mark are formed by photoetching and etching; the process for layer 0 may be deposition
Figure GDA0003072565990000195
Then photolithography, etching the oxide film, and then etching silicon
Figure GDA0003072565990000194
Forming a step; in order to better protect the front side of the device and improve the reliability of the device, a passivation layer may be deposited after the front side metal pattern is formed, and then the passivation layer of the metal region to be opened is etched away by the passivation layer lithography and etching. While in other areas the passivation layer is left to protect the device, which may be SIN, SION, SIO2, typically 0.8 μm to 2 μm thick.
By adopting the tungsten plug process, for the contact hole with the height-width ratio smaller than 10, the filling problem can not occur, and in the first embodiment of the invention: the width of the first contact hole 6a is 0.6 μm, and the thickness of the interlayer film 104 is
Figure GDA0003072565990000191
The aspect ratio of the first contact hole 6a is 1.33; guard ring oxide film if thick field oxide film103 has a thickness of
Figure GDA0003072565990000192
The minimum size or width of the contact hole in the transition region, i.e. the second contact hole 6b, is 0.6 microns, so that the aspect ratio of the contact hole is 2.67 and is less than 10, therefore, the filling problem is not existed, and the pinhole-free filling can be realized.
When the distribution area of the contact holes in the transition area, i.e. the second contact holes 6b, is enlarged, it is necessary to ensure that the P-type ring completely covers each of the contact holes 6b, and the capacity of the covering needs to be more than 1 micrometer.
In the first embodiment of the present invention, in the second step, the P-type ring is formed simultaneously by using the same process as the P-type well 3. In other embodiments, the method can also be: the P-type ring 4 is formed by adopting separate photoetching and ion implantation processes, and the forming process of the P-type ring 4 is positioned before the forming process of the P-type well 3. For example: according to the design requirement, a single P-type ring 4 is photoetched and implanted, for example, after the groove is filled, the P-type ring 4 is photoetched and implanted, the implantation energy can be better than that of the P-type well 3, and all the subsequent high-temperature processes are performed, so that the junction of the P-type ring 4 is deeper than that of the P-type well 3, the reliability of the device is further improved, and the soft factor of the body diode reverse recovery of the device is increased, because: the junction is deepened, and the distance from the collected holes to the high-concentration P-type contact region is increased, so that the soft factor of the body diode reverse recovery is increased. The implantation dose of the P-type ring 4 can also be smaller than, larger than or equal to the dose of the P-type well 3 according to the requirement.
In other embodiments, the contact hole implantation, i.e., the P + ion implantation of the P + contact region 107, may be performed in two times, for example, after the contact hole process is completed, a full implantation may be performed first, the energy and dose used are set according to the requirement of the transition region, and then a photolithography may be performed to protect the contact hole of the transition region, i.e., the second contact hole 6b, and only the contact hole of the charge flow region, i.e., the first contact hole 6a, may be performed, at this time, the P-type impurity of the contact region 107 may be set according to the requirement of the charge flow region, and through such a process, the P-type impurity of the contact region 107 of the two regions may be set according to the respective requirement, so as to further optimize the performance of the device.
The method for manufacturing the super junction device comprises the following steps:
the difference between the method according to the second embodiment of the present invention and the method according to the first embodiment of the present invention is that the method according to the second embodiment of the present invention employs the following steps to form the contact hole and the P + contact region 107 at the bottom of the contact hole:
the interlayer film 104 is composed of an oxide film, in the fifth step, when the openings of the first contact hole 6a, the second contact hole 6b and the third contact hole 6c are formed by etching, the oxide film is etched first, and when the interlayer film 104 in the first contact hole 6a area is completely removed and the source area 106 at the bottom is exposed, the oxide film is stopped from being etched, so that the epitaxial layer material, namely, the silicon material is etched.
When the epitaxial layer material is etched, the epitaxial layer at the bottom of the first contact hole 6a is over-etched, and meanwhile, the oxide film in the second contact hole 6b area is partially etched; the P + ion implantation of the P + contact region 107 is performed before the oxide film in the second contact hole 6b region is not completely removed, so that the peak value of the P + ion implantation of the P + contact region 107 in the second contact hole 6b region is located in the oxide film, and after the opening and metal filling of the first contact hole 6a, the second contact hole 6b and the third contact hole 6c are completed, the peak value of the doping concentration of the P + contact region 107 at the bottom of the second contact hole 6b is smaller than the peak value of the doping concentration of the P + contact region 107 at the bottom of the first contact hole 6 a.
And adjusting the doping concentration of the P + contact region 107 at the bottom of the second contact hole 6b by adjusting the thickness of the oxide film at the bottom of the second contact hole 6b during the P + ion implantation of the P + contact region 107, wherein the peak value of the doping concentration of the P + contact region 107 at the bottom of the second contact hole 6b is 1/2-1/10 of the peak value of the doping concentration of the P + contact region 107 at the bottom of the first contact hole 6 a.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (13)

1. A super junction device is provided, wherein the middle region of the super junction device is a charge flowing region, a terminal region surrounds the periphery of the charge flowing region, and a transition region is positioned between the charge flowing region and the terminal region; it is characterized by comprising:
the N-type epitaxial layer is subjected to dry etching to form a plurality of grooves; filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer between the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns;
a P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the N-type column on two sides of the corresponding P-type column;
a P-type ring surrounding the charge flowing region is formed on the surface of the super junction structure in the transition region; each P-type trap is contacted with the P-type ring;
forming a first oxide film on the surface of the super junction structure on which the P-type well and the P-type ring are formed, the first oxide film being formed by photolithography etching, the protective epoxy film exposing the charge flowing region and covering at least a partial region of the transition region, the protective epoxy film further extending to the surface of the termination region and covering the termination region entirely or exposing only an outermost peripheral portion of the termination region, the protective ring oxide film surrounding a peripheral side of the charge flowing region;
a source region composed of an N + region is formed on the surface of the P-type well of the charge flowing region, and an injection region of the source region is defined by the self-alignment of the guard ring oxide film;
a first contact hole is formed in the charge flowing region, a second contact hole is formed in the transition region, and the photoetching process of the first contact hole is the same as that of the second contact hole;
the tops of the first contact hole and the second contact hole are connected to a source electrode consisting of a front metal layer;
the bottom of the first contact hole penetrates through an interlayer film and the source region and is in contact with the source region and the P-type well;
the second contact holes are distributed in a partial area of the surface of the transition area covered with the protective epoxy film, and the bottom of the second contact holes penetrates through the interlayer film and the protective ring oxide film and is in contact with the P-type ring;
setting the ratio of the depth of the first contact hole to the minimum transverse dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole to the minimum transverse dimension as a second aspect ratio; the second aspect ratio is larger than or equal to the first aspect ratio, the first contact hole and the second contact hole are filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capacity and simultaneously realize reliable filling of the first contact hole and the second contact hole with different aspect ratios;
a planar gate structure formed by overlapping a gate oxide film and a polysilicon gate is formed on the surface of the super junction structure of the charge flowing area, the forming area of the polysilicon gate is defined by a photoetching process, each polysilicon gate covers the corresponding P-type well, and the surface of the P-type well covered by the polysilicon gate is used for forming a channel;
the source region is formed on two sides of the polysilicon gate in the charge flowing region in a self-alignment mode;
each polysilicon gate is of a strip structure, and the length direction of each polysilicon gate is parallel to the length direction of the groove;
forming a polysilicon bus on the surface of the protection ring oxide film in the terminal area, wherein each polysilicon gate is connected to the polysilicon bus through a polysilicon connecting line formed on the surface of the protection epoxy film in the transition area, and the polysilicon bus, the polysilicon connecting line and the polysilicon gate are formed simultaneously by adopting the same polysilicon deposition and polysilicon etching processes; the width of the polysilicon connecting line is less than or equal to that of the polysilicon gate;
each first contact hole is of a strip-shaped structure, and the length direction of each first contact hole is parallel to the length direction of the groove; the width of each first contact hole is the minimum transverse dimension;
the array structure is formed by arranging one first contact hole in a strip structure or more than two first contact holes in parallel arrangement in a strip structure or a plurality of first contact holes with rectangular top-view surfaces between every two adjacent polysilicon gates;
the top view surface of each second contact hole is rectangular, the width of each second contact hole is larger than or equal to that of each first contact hole, and one second contact hole is arranged between every two adjacent polysilicon connecting lines or an array structure formed by arranging a plurality of second contact holes is arranged between every two adjacent polysilicon connecting lines.
2. The superjunction device of claim 1, wherein: the P-type ring completely covers the second contact hole and ensures that the margin is more than or equal to 1 micron.
3. The superjunction device of claim 1, wherein: a third contact hole is formed at the top of the polycrystalline silicon bus, and the photoetching process of the first contact hole is the same as that of the third contact hole;
the tops of the third contact holes are connected to a grid electrode consisting of a front metal layer;
the bottom of the third contact hole passes through an interlayer film and into the polysilicon bus line and the bottom of the third contact hole stays in or passes through the polysilicon bus line.
4. The superjunction device of claim 1, wherein: the second contact holes also extend to be distributed in a partial region where the surface of the transition region is not covered with the protective epoxy film, and the bottom of the second contact holes in the partial region is brought into contact with the P-type ring through the interlayer film.
5. The superjunction device of claim 1, wherein: p + contact regions are formed at the bottoms of the first contact holes and the second contact holes.
6. The superjunction device of claim 1, wherein: the process conditions of the P-type well and the P-type ring are the same and are formed simultaneously; alternatively, the process conditions of the P-type ring and the P-type well are independent and separately formed.
7. The superjunction device of claim 1, wherein: and a JFET area is formed on the surface of the super junction structure of the charge flowing area, and the forming area of the JFET area is defined by the guard ring oxide film in a self-aligned mode.
8. A manufacturing method of a super junction device is provided, wherein the middle area of the super junction device is a charge flowing area, a terminal area surrounds the periphery of the charge flowing area, and a transition area is positioned between the charge flowing area and the terminal area; the method is characterized by comprising the following steps:
step one, providing an N-type epitaxial layer, defining a forming area of a groove by a first photoetching process, and then carrying out dry etching on the N-type epitaxial layer to form a plurality of grooves;
filling a P-type epitaxial layer in the groove to form a P-type column, forming an N-type column by the N-type epitaxial layer between the P-type columns, and forming a super junction structure by a plurality of alternately arranged N-type columns and P-type columns;
step two, defining a forming area of a P-type well in the charge flowing area by carrying out a second photoetching process, and then carrying out P-type ion implantation to form the P-type well;
one P-type well is formed at the top of each P-type column in the charge flowing region, and each P-type well extends to the surface of the corresponding N-type column on two sides of the corresponding P-type column;
forming a P-type ring surrounding the periphery of the charge flow region on the surface of the super junction structure in the transition region by the same process while forming the P-type well; each P-type trap is contacted with the P-type ring;
step three, growing a first oxide film on the surface of the super junction structure on which the P-type well and the P-type ring are formed, performing a third photolithography process to define an etching area of the first oxide film, and then etching the first oxide film to form a guard ring oxide film, wherein the guard ring oxide film exposes the charge flowing area and covers at least a partial area of the transition area, the guard ring oxide film further extends to the surface of the termination area and covers the termination area completely or only exposes the outermost periphery of the termination area, and the guard ring oxide film surrounds the periphery of the charge flowing area;
carrying out overall first N-type ion implantation by taking the guard ring oxide film as a self-alignment condition to form a JFET (junction field effect transistor) region in the charge flowing region, and simultaneously forming a terminal first N-type implantation region in or outside the terminal region outside the protection epoxy film covering region;
sequentially forming a gate oxide film and a first layer of N-type heavily doped polysilicon, defining a forming region of a polysilicon gate by a fourth photoetching process, etching the first layer of polysilicon to form polysilicon gates, wherein each polysilicon gate is of a planar gate structure, covers the corresponding P-type well, and is used for forming a channel on the surface of the P-type well covered by the polysilicon gate;
carrying out comprehensive second N-type ion implantation by taking the polysilicon gate and the guard ring oxide film as self-alignment conditions to form source regions on two sides of the polysilicon gate in the charge flowing region respectively, and simultaneously forming a terminal second N-type implantation region in or outside the terminal region outside the protection epoxy film covering region;
depositing an interlayer film, and defining forming areas of a first contact hole, a second contact hole and a third contact hole by a fifth photoetching process; then, etching is carried out to form openings of the first contact hole, the second contact hole and the third contact hole; filling metal in openings of the first contact hole, the second contact hole and the third contact hole to form the first contact hole, the second contact hole and the third contact hole;
the bottom of the first contact hole penetrates through the interlayer film and the source region and is in contact with the source region and the P-type well;
the second contact holes are distributed in a partial area of the surface of the transition area covered with the protective epoxy film, and the bottom of the second contact holes penetrates through the interlayer film and the protective ring oxide film and is in contact with the P-type ring;
setting the ratio of the depth of the first contact hole to the minimum transverse dimension as a first aspect ratio, and setting the ratio of the depth of the second contact hole to the minimum transverse dimension as a second aspect ratio; the second aspect ratio is larger than or equal to the first aspect ratio, the first contact hole, the second contact hole and the third contact hole are filled by adopting a tungsten plug process, and the tungsten plug process is utilized to ensure hole covering capacity and simultaneously realize reliable filling of the first contact hole and the second contact hole with different aspect ratios;
and sixthly, depositing front metal to form a front metal layer, defining forming areas of a grid electrode and a source electrode by carrying out a sixth photoetching process, etching the front metal layer to form the grid electrode and the source electrode, connecting each source region in the charge flowing region and the corresponding P-type well to the source electrode through the first contact hole with the same top, connecting the P-type ring in the transition region to the source electrode through the second contact hole with the same top, and connecting the polysilicon gate to the grid electrode through the third contact hole.
9. The method of manufacturing a superjunction device of claim 8, wherein: and fifthly, after the openings of the first contact hole, the second contact hole and the third contact hole are formed, before metal filling, a step of performing P + ion implantation at the bottoms of the first contact hole and the second contact hole to form a P + contact region is further included.
10. The method of manufacturing a superjunction device of claim 9, wherein: the interlayer film is composed of an oxide film, in the fifth step, when the openings of the first contact hole, the second contact hole and the third contact hole are formed by etching, the oxide film is etched firstly, when the interlayer film in the first contact hole area is completely removed and the source area at the bottom is exposed, the oxide film is stopped to be etched, and the epitaxial layer material is etched; when the epitaxial layer material is etched, the epitaxial layer at the bottom of the first contact hole is over-etched, and meanwhile, the oxide film in the second contact hole area is partially etched; and performing P + ion implantation of the P + contact region before the oxide film of the second contact hole region is not completely removed, so that the peak value of the P + ion implantation of the P + contact region of the second contact hole region is positioned in the oxide film, and after the openings of the first contact hole, the second contact hole and the third contact hole and the metal filling are completely finished, the peak value of the doping concentration of the P + contact region at the bottom of the second contact hole is smaller than the peak value of the doping concentration of the P + contact region at the bottom of the first contact hole.
11. The method of manufacturing a superjunction device of claim 10, wherein: and adjusting the doping concentration of the P + contact region at the bottom of the second contact hole by adjusting the thickness of the oxide film at the bottom of the second contact hole region during the P + ion implantation of the P + contact region, wherein the peak value of the doping concentration of the P + contact region at the bottom of the second contact hole is 1/2-1/10 of the peak value of the doping concentration of the P + contact region at the bottom of the first contact hole.
12. The method of manufacturing a superjunction device of claim 8, wherein: and in the second step, the P-type ring is formed by adopting separate photoetching and ion implantation processes, and the forming process of the P-type ring is positioned before the forming process of the P-type well.
13. The method of manufacturing a superjunction device of claim 9, wherein: forming a polysilicon bus on the surface of the protective epoxy film in the terminal area and forming polysilicon connecting lines on the surface of the protective epoxy film in the transition area while forming the polysilicon gates, wherein each polysilicon gate is connected to the polysilicon bus through the polysilicon connecting lines, and the width of each polysilicon connecting line is less than or equal to that of the polysilicon gate;
in the fifth step, the third contact hole is positioned at the top of the polycrystalline silicon bus, the bottom of the third contact hole penetrates through an interlayer film and enters the polycrystalline silicon bus, and the bottom of the third contact hole stays in the polycrystalline silicon bus or penetrates through the polycrystalline silicon bus;
and fifthly, protecting the third contact hole region by adopting a photoetching process when injecting the P + ions of the P + contact region.
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