CN109147851B - Latch circuit - Google Patents
Latch circuit Download PDFInfo
- Publication number
- CN109147851B CN109147851B CN201811014888.9A CN201811014888A CN109147851B CN 109147851 B CN109147851 B CN 109147851B CN 201811014888 A CN201811014888 A CN 201811014888A CN 109147851 B CN109147851 B CN 109147851B
- Authority
- CN
- China
- Prior art keywords
- nmos transistor
- high voltage
- control signal
- programming
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The invention discloses a latch circuit, which comprises a storage array, a latch circuit and a latch circuit, wherein the storage array is M sub-storage areas <0: M-1> obtained by dividing the original whole storage array area according to bytes and is used for storing information according to bytes; the latch module is used for generating high voltage GBL < k, i > required by erasing, programming and preprogramming for M sub-storage areas <0: M-1>, and the latch module and the storage array are divided according to bytes, so that the latch and the storage array can be used efficiently, the use frequency of the storage array is reduced, the aging rate of the storage array is slowed down, and the reliability of the storage array is improved.
Description
Technical Field
The invention relates to the technical field of nonvolatile Memory design, in particular to a novel Flash Memory (Flash Memory) latch circuit.
Background
The embedded non-volatile MEMORY (EFLASH MEMORY) can well store data after the system is powered off, and can be widely applied to industries such as automotive electronics, smart home and the like. With the rise of these industries, higher requirements are put on the reliability (the number of times of erasing and the service life) of flash, and therefore, it is very important to research how to improve the reliability of flash.
In general, the system architecture of Flash includes two parts, a memory array and peripheral circuits. The peripheral circuit comprises a row decoding circuit, a column decoding circuit, a logic control circuit, a read amplifying circuit and a data latch circuit. The data reading failure problem of the Flash IP can occur after a certain service life, and the reason is that the aging of the storage array can be caused along with the increase of the erasing times and the service life, the threshold voltage of the storage array is reduced, and the data reading window is reduced, so that the data cannot be correctly read. There are two ways to improve reliability: a first raised threshold voltage window, which is related to the design of the sense amplifier circuit; the second is to reduce the aging rate of the memory array, which is related to the design of the data latch circuit. The scheme is a design scheme provided based on how to reduce the aging of the storage array, optimizes the data latch circuit, and reduces the use times of the storage array, thereby improving the reliability of the storage array.
FIG. 1 is a diagram of a prior art latch architecture for a flash IP memory array, as shown in FIG. 1, which includes a latch module (page latch) and a memory data array module. The latch address (latch address), the input data (data in), and the high voltage control signal generate a GBL (global bit line) signal through the latch module to act on a BL (bit line) of a SONOS (silicon-oxide-nitride-oxide-silicon) memory cell.
The GBL voltages generated in the pre-program, erase, program high voltage mode are shown in table 1.
TABLE 1 GBL increment table
The high-voltage operation of the memory unit is divided into three steps, firstly, the pre-programming operation is carried out, negative high voltage vneg is added on a bit line BL, and the threshold voltage of the memory unit is improved; then, erasing (erase) operation is carried out, historical storage data are cleared, positive high voltage vpos is added on a bit line BL, the threshold voltage of the storage unit is pulled down, and the storage unit is cleared to be 0 after the erasing (erase) operation; finally, a program operation is performed, according to the 0/1 states of the latch din, a positive voltage vbl/a negative high voltage vneg is applied to the bit line BL, wherein the value of vbl is between 0 and vdd (power supply voltage), which causes the threshold voltage of the memory cell to be pulled up to different degrees. Thus, the high-voltage programming operation of the memory unit is completed, data is stored in the memory array, and the data in the memory array can be read out through the reading operation.
The latch circuit latches data to GBL < (n-1) by performing a high-voltage operation on GBL: 0>, which means that all columns of the memory array are selected for each high voltage operation. However, in practical applications, the data capacity of each time of modification by a client is much smaller than the capacity of the whole memory array, which causes repeated erasing of the unmodified part, accelerates aging of the memory array, reduces the use frequency of the memory array, and thus reduces the reliability of the memory array.
Disclosure of Invention
In order to overcome the defects in the prior art, the present invention provides a latch circuit, which is used to implement a byte operation, so as to avoid performing high-voltage erasing operation on all memory arrays at one time, reduce the aging rate of the memory arrays, and thus improve the reliability of flash IP stored data.
To achieve the above and other objects, the present invention provides a latch circuit, which includes
The storage array is used for storing information according to bytes, wherein M sub-storage areas <0: M-1> are obtained by dividing the original integral storage array area according to bytes;
the latch module is used for generating high voltage GBL < k, i >, k is 0,1,2, … …, M-1, i is 0,1,2, … …, W-1, W is the digit of the byte word for the M sub-storage areas <0: M-1> and is needed for erasing, programming and preprogramming.
Preferably, the latch module includes:
an address decoder for generating a byte selection signal pasel < k > according to the address signal;
m page latch sub-circuits for generating high voltages GBL < k, i > required for erasing, programming and preprogramming M sub-memory regions <0: M-1> according to a byte selection signal pasel < k >.
Preferably, each page latch sub-circuit includes:
a byte latch circuit for converting a byte selection signal pasel < k > output from the address decoder into an in-phase byte selection signal paseld < k > and a complementary section selection signal paselb < k >, k being 0,1, … …, M-1;
a logic circuit for generating mode control signals required by different operation modes under the control of a byte selection signal and an operation mode (pre-program/erase/program);
and the high voltage generating circuit is used for generating high voltages required by different working modes.
Preferably, the required high voltage control signals include an erase high voltage control signal ldersb, a program high voltage control signal ldprg, a complementary program high voltage control signal hv _ ldprgb, high voltage program input data hv _ data, and a high voltage pre-program control signal hv _ pep.
Preferably, the high voltages required for the different operating modes include high voltages required for erasing, programming and pre-programming.
Preferably, the address signal pa is connected to an input terminal of the address decoder, an output byte selection signal pasel < k > of the address signal pa is respectively connected to input terminals of the M byte latch circuits, an output of each byte latch circuit is connected to input terminals of the corresponding logic circuit, a mode control signal output by the logic circuit and an erase high voltage control signal ldersb, a program high voltage control signal ldprg, a complementary program high voltage control signal hv _ ldprgb, high voltage program input data hv _ data, a high voltage preprogramming control signal hv _ pep generated by a high voltage module (not shown) are connected to an input terminal of the corresponding high voltage generating circuit, an output high voltage GBL < k, i > of the high voltage generating circuit is connected to a W bit of the corresponding sub memory region k, the programming input data din and the high voltage control signal Hv control signal are connected to the input terminal of the high voltage generating circuit.
Preferably, the byte latch circuit includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a first NMOS transistor MN1 and a second NMOS transistor MN 2.
Preferably, the sources and the substrate of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to ground vgnd, the gate of the first NMOS transistor MN1 is connected to a reset signal reset, the gate of the second NMOS transistor MN2 is connected to a byte selection signal pasel < k >, the drain of the first NMOS transistor MN1 is connected to the output end of the second inverter INV2 and the input ends of the first inverter INV1 and the fourth INV4, the drain of the second NMOS transistor MN2 is connected to the output end of the first inverter INV1 and the input ends of the second inverter INV2 and the third INV3, the output of the third inverter INV3 is an in-phase byte selection signal pasel < k >, and the output of the fourth inverter INV4 is a complementary node selection signal pasel < k >.
Preferably, the high voltage generating circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN 5.
Preferably, the substrate of the third NMOS transistor MN3 and the sources and substrates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to the negative high voltage hv _ vneg _ c, the substrates of the second PMOS transistor MP2 and the third PMOS transistor MP3 and the source and substrate of the first PMOS transistor MP1 are connected to the positive high voltage hv _ vpos _ c, the gate of the fourth NMOS transistor MN4 is connected to the high voltage programming input data hv _ data, the gate of the third NMOS transistor MN3 is connected to the programming high voltage control signal ldprg, the gate of the fifth NMOS transistor MN5 is connected to the high voltage programming control signal hv _ pep, the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4, the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3, the source of the second PMOS transistor MP2 is connected to the high voltage vbl, and the drain of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, the drain of the fifth NMOS transistor MN, the PMOS transistor MN 58k and the drain output node < PMOS transistor MP 58k > GBL < output node.
Compared with the prior art, the latch circuit provided by the invention has the advantages that the latch module and the storage array are divided according to the bytes, so that a client can reasonably utilize the bytes according to the requirement, the latch and the storage array can be efficiently used, the use frequency of the storage array is reduced, the aging rate of the storage array is slowed down, and the reliability of the storage array is improved.
Drawings
FIG. 1 is a diagram of a prior art flash IP memory array latch architecture;
FIG. 2 is a schematic diagram of a latch circuit according to the present invention;
FIG. 3 is a block diagram of a Latch module (Page Latch) according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a byte (Word) latch circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a high voltage generating circuit according to an embodiment of the invention.
Detailed Description
Other advantages and capabilities of the present invention will be readily apparent to those skilled in the art from the present disclosure by describing the embodiments of the present invention with specific embodiments thereof in conjunction with the accompanying drawings. The invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention.
Fig. 2 is a schematic structural diagram of a latch circuit according to the present invention. As shown in fig. 2, a Latch circuit of the present invention includes a Latch module (Page Latch)10 and a memory array 20.
The storage array 20 is M sub-storage areas <0: M-1> obtained by dividing the original whole storage array area by bytes (word), and is used for storing information by bytes; a latch module (page latch)10, configured to generate high voltages GBL < k, i >, k is 0,1,2, … …, M-1, i is 0,1,2, … …, W-1, W is the number of bits of the byte word, for M sub-memory regions <0: M-1> required for erasing, programming, and preprogramming.
As shown in fig. 3, the Latch module (Page Latch)10 is composed of an address decoder 110 and M Page Latch (Page Latch <0: M-1>) sub-circuits 120, wherein the Page Latch (Page Latch <0: M-1>) sub-circuits 120 include a byte (Word) Latch circuit 121, a logic circuit 122 and a high voltage generating circuit 123, wherein the byte (Word) Latch circuit 121 converts a byte select signal passk > output from the address decoder 110 into an in-phase byte select signal passk > and a complementary byte select signal passb > (k ═ 0,1, … …, M-1), the logic circuit 122 generates mode control signals required for different operation modes such as pre-programming, erasing and programming under the control of the byte select signal and the operation mode (pre-program/erase/program), the high voltage generating circuit 123, for generating the high voltages required for different operation modes such as erase, program and pre-program under the control of the mode control signal outputted from the logic circuit 122 and the high voltage control signal outputted from the high voltage module (not shown) such as the erase high voltage control signal ldersb, the program high voltage control signal ldprg, the complementary program high voltage control signal hv _ ldprgb, the high voltage program input data hv _ data, the high voltage pre-program control signal hv _ pep.
Specifically, the address signal pa is connected to an input terminal of the address decoder 110, an output byte selection signal pasel < k > (k is 0,1, … …, M-1) of which is respectively connected to input terminals of M byte (Word) latch circuits 121, an output in-phase byte selection signal paseld < k > and a complementary section selection signal paselb < k > (k is 0,1, … …, M-1) and an operation mode (pre-program/erase/program) of each byte (Word) latch circuit 121 are connected to input terminals of the corresponding logic circuit 122, a mode control signal output by the logic circuit 122 and an erase high voltage control signal ldersb, a program high voltage control signal ldprg, a complementary program high voltage control signal hv _ ldprgb, high voltage program input data hv _ data, a high voltage preprogramming control signal hv _ pep output by a high voltage module (not shown) are connected to input terminals of the corresponding high voltage generating circuit 123, the output high voltage GBL < k, i > of the high voltage generating circuit 123 is connected to the W bit (k is 0,1, … …, M-1; i is 0,1,2, … …, W-1, W is the bit number of the byte word of the sub memory region k, W is 2 in fig. 2, and the bit number W is n in fig. 2) of the corresponding sub memory region k, and the programming input data din and the high voltage control signal Hv control signal are connected to the input terminal of the high voltage generating circuit 123.
Specifically, as shown in fig. 4, the byte (Word) latch circuit 121 includes inverters INV1, INV2, INV3, INV4 and NMOS transistors MN1 and MN2, sources and substrates of NMOS transistors MN1 and MN2 are connected to ground vgnd, a gate of NMOS transistor MN1 is connected to a reset signal reset, a gate of NMOS transistor MN2 is connected to a byte select signal pasel < k >, a drain of NMOS transistor MN1 is connected to an output terminal of inverter INV2 and input terminals of inverters INV1 and INV4, a drain of NMOS transistor MN2 is connected to an output terminal of inverter INV1 and input terminals of inverters INV2 and INV3, an output of inverter INV3 is an in-phase byte select signal pasel < k >, an output of inverter INV4 is a complementary node select signal pasel < k >, and a bit sequence k of each signal is omitted in fig. 4 (k is 670, 1, … …, M-1)
As shown in fig. 5, the high voltage generating circuit 123 includes PMOS transistors MP1, MP2, MP3, NMOS transistor MN3, MN4, and MN5, the substrate of the NMOS transistor MN3 and the sources and substrates of the NMOS transistors MN4 and MN5 are connected to the negative high voltage hv _ vneg _ c, the substrates of the PMOS transistors MP2 and MP3 and the sources and substrates of the PMOS transistor MP1 are connected to the positive high voltage hv _ vpos _ c, the gate of the NMOS transistor MN4 is connected to the high voltage programming input data hv _ data, the gate of the NMOS transistor MN5 is connected to the programming high voltage control signal ldprg, the gate of the NMOS transistor MN5 is connected to the high voltage control signal hv _ pep, the source of the NMOS transistor MN3 is connected to the drain of the NMOS transistor MN4, the drain of the PMOS transistor MP2 is connected to the source of the PMOS transistor MP3, the source of the PMOS transistor MP2 is connected to the high voltage vbl, and the drain of the NMOS transistor MN3 is connected to the drain of the NMOS transistor MN 69556, the drain of the PMOS transistor MN 828653 and the PMOS transistor MN 86 3.
The customer can select the required latch module (page latch) and memory array area according to the requirement to carry out erasing operation, and the unselected area does not need to carry out erasing operation, thus effectively utilizing the memory array, reducing the aging speed of the memory array and improving the reliability of the memory array.
GBL < k, i > voltages generated by the latch circuit after byte division are shown in a table 2 (the bit sequence < k, i > is ignored subsequently), a word is selected, and the GBL voltage generated by the latch circuit is the same as the GBL voltage generated by the traditional latch circuit; while GBLs generated by unselected words are all pulled to "0" (vgnd) in high voltage mode.
TABLE 2 GBL increment table generated by byte-divided latch circuit
The circuit works specifically as follows:
(1) the number M of the latch address (pa) decoding confirmation latch modules (page latches) divided by byte
(2) The latch address (pa) determines the selected word, which selects the latch circuit as shown in FIG. 4. When pasel is '1', word is selected; past is "0" and word is not selected
(3) Logic control between the pasel and the high-voltage mode and input data latch confirm the voltage of the selected word and GBL under different high-voltage modes; word, GBL, is pulled to "0" if not selected "
Therefore, the latch circuit provided by the invention divides the latch module and the storage array according to the bytes, so that a client can reasonably utilize the bytes according to the requirement, the latch and the storage array can be efficiently used, the use frequency of the storage array is reduced, the aging rate of the storage array is slowed down, and the reliability of the storage array is improved.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Modifications and variations can be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (7)
1. A latch circuit comprises
The storage array is used for storing information according to bytes, wherein M sub-storage areas <0: M-1> are obtained by dividing the original integral storage array area according to bytes;
the latch module comprises an address decoder and M page latch sub-circuits; the address decoder is used for generating a byte selection signal pasel < k > according to the address signal; each page latch sub-circuit comprises a byte latch circuit, a logic circuit and a high-voltage generating circuit; the byte latch circuit is used for converting the byte selection signal passl < k > output by the address decoder into an in-phase byte selection signal passd < k > and a complementary section selection signal passb < k >, k being 0,1, … …, M-1; the logic circuit is used for generating mode control signals required by different working modes under the control of byte selection signals and operation modes pre-program/erase/program; the high voltage generating circuit is used for generating high voltage GBL < k, i > required by erasing, programming and preprogramming for M sub-storage regions <0: M-1> under the control of the mode control signal, wherein k is 0,1,2, … …, M-1, i is 0,1,2, … …, W-1, and W is the digit of a byte;
the address signal pa is connected to the input end of the address decoder, the output byte selection signal pasel < k > is respectively connected to the input ends of the M byte latch circuits, the output in-phase byte selection signal paseld < k > and the complementary section selection signal paselb < k > of each byte latch circuit are connected to the input end of the corresponding logic circuit, the mode control signal output by the logic circuit is connected to the input end of the corresponding high-voltage generating circuit, and the output high-voltage GBL < k, i > of the high-voltage generating circuit is connected to the W bit of the corresponding sub-storage area k.
2. A latch circuit according to claim 1, wherein: the required high voltage control signals include an erasing high voltage control signal ldersb, a programming high voltage control signal ldprg, a complementary programming high voltage control signal hv _ ldprgb, high voltage programming input data hv _ data, a high voltage pre-programming control signal hv _ pep.
3. A latch circuit according to claim 2, wherein: the erasing high-voltage control signal ldersb, the programming high-voltage control signal ldprg, the complementary programming high-voltage control signal Hv _ ldprgb, the high-voltage programming input data Hv _ data and the high-voltage pre-programming control signal Hv _ pep generated by the high-voltage module are connected to the input end of the corresponding high-voltage generating circuit, and the programming input data din and the high-voltage control signal Hv control signal are connected to the input end of the high-voltage generating circuit.
4. A latch circuit according to claim 3, wherein: the byte latch circuit comprises a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, a first NMOS transistor MN1 and a second NMOS transistor MN 2.
5. A latch circuit according to claim 4, wherein: the source electrodes and the substrate of the first NMOS transistor MN1 and the second NMOS transistor MN2 are connected to ground vgnd, the gate electrode of the first NMOS transistor MN1 is connected to a reset signal reset, the gate electrode of the second NMOS transistor MN2 is connected to a byte selection signal pasel < k >, the drain electrode of the first NMOS transistor MN1 is connected to the output end of the second inverter INV2 and the input ends of the first inverter INV1 and the fourth INV4, the drain electrode of the second NMOS transistor MN2 is connected to the output end of the first inverter INV1 and the input ends of the second inverter INV2 and the third INV3, the output of the third inverter INV3 is an in-phase byte selection signal paseld < k >, and the output of the fourth inverter INV4 is a complementary node selection signal paselb < k >.
6. A latch circuit according to claim 3, wherein: the high voltage generating circuit comprises a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a third NMOS tube MN3, a fourth NMOS tube MN4 and a fifth NMOS tube MN 5.
7. A latch circuit according to claim 6, wherein: the substrate of the third NMOS transistor MN3, the substrates of the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5, and the sources and substrates of the fourth NMOS transistor MN2 and the third PMOS transistor MP3 are connected to the negative high voltage hv _ vneg _ c, the substrates of the second NMOS transistor MP2 and the third PMOS transistor MP3, and the sources and substrates of the first PMOS transistor MP1 are connected to the positive high voltage hv _ vpos _ c, the gate of the fourth NMOS transistor MN4 is connected to the high voltage programming input data hv _ data, the gate of the third NMOS transistor MN3 is connected to the programming high voltage control signal ldprg, the gate of the fifth NMOS transistor MN5 is connected to the high voltage programming control signal hv _ pep, the source of the third NMOS transistor MN3 is connected to the drain of the fourth NMOS transistor MN4, the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3, the source of the second PMOS transistor MP 38 is connected to the high voltage vbl, and the drain of the third NMOS transistor MN3 is connected to the drain of the fifth NMOS transistor MN5, the drain of the PMOS transistor MP 596k, and the drain of the first PMOS transistor MP3, and the drain node < PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811014888.9A CN109147851B (en) | 2018-08-31 | 2018-08-31 | Latch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811014888.9A CN109147851B (en) | 2018-08-31 | 2018-08-31 | Latch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109147851A CN109147851A (en) | 2019-01-04 |
| CN109147851B true CN109147851B (en) | 2020-12-25 |
Family
ID=64826010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811014888.9A Active CN109147851B (en) | 2018-08-31 | 2018-08-31 | Latch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109147851B (en) |
Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0139889B1 (en) * | 1994-12-27 | 1999-04-15 | 김주용 | Flash memory device |
| US6097638A (en) * | 1997-02-12 | 2000-08-01 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
| JP2002216483A (en) * | 2001-01-18 | 2002-08-02 | Toshiba Corp | Semiconductor memory |
| CN1720587A (en) * | 2002-11-14 | 2006-01-11 | 柰米闪芯集成电路有限公司 | Combination nonvolatile memory using unified technology |
| JP4262033B2 (en) * | 2003-08-27 | 2009-05-13 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
| JP3898682B2 (en) * | 2003-10-03 | 2007-03-28 | 株式会社東芝 | Semiconductor integrated circuit |
| JP5018074B2 (en) * | 2006-12-22 | 2012-09-05 | 富士通セミコンダクター株式会社 | Memory device, memory controller and memory system |
| US8737135B2 (en) * | 2011-08-23 | 2014-05-27 | Winbond Electronics Corporation | Method for and flash memory device having improved read performance |
| KR101278103B1 (en) * | 2011-09-26 | 2013-06-24 | 에스케이하이닉스 주식회사 | Nonvolatile memory device and programming method thereof |
| US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
-
2018
- 2018-08-31 CN CN201811014888.9A patent/CN109147851B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN109147851A (en) | 2019-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102046073B1 (en) | Nonvolatile semiconductor memory device and Method of driving wordlines thereof | |
| US9281063B2 (en) | Method for processing data, flash memory, and terminal | |
| KR960005370B1 (en) | Method for erasing and verifying nonvolatile semiconductor memory device | |
| US9899091B2 (en) | Semiconductor memory device for switching high voltage without potential drop | |
| JP2015170374A (en) | Semiconductor storage device | |
| US7362614B2 (en) | Non-volatile semiconductor storage apparatus | |
| US10083755B2 (en) | Discharge circuit and semiconductor memory device | |
| JP2017147011A (en) | Semiconductor storage device | |
| KR20190052548A (en) | Nonvolatile memory device | |
| JP2007087571A (en) | Flash memory device and its high-voltage recharging method | |
| CN115910129A (en) | Nonvolatile memory and electronic device | |
| US9564231B2 (en) | Non-volatile memory device and corresponding operating method with stress reduction | |
| KR100587683B1 (en) | High voltage generator in non-volatile semiconductor memory device | |
| CN109147851B (en) | Latch circuit | |
| US6487139B1 (en) | Memory row line driver circuit | |
| US6813186B2 (en) | Nonvolatile semiconductor memory device | |
| CN107799146B (en) | Memory array and reading, programming and erasing operation method thereof | |
| US6768678B1 (en) | Data sensing method used in a memory cell circuit | |
| US6580645B1 (en) | Page buffer of a flash memory | |
| JP2008004175A (en) | Nonvolatile semiconductor memory device and its voltage applying method | |
| JP5073234B2 (en) | Word line decoder suitable for low operating power supply voltage of flash memory devices | |
| US8537586B2 (en) | Memory array and storage method | |
| KR101766972B1 (en) | Systems, devices and methods for memory operations | |
| KR100632367B1 (en) | Program bit scan display circuit in nonvolatile semiconductor memory device | |
| JP6744893B2 (en) | Nonvolatile semiconductor memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |