CN109119487B - Super barrier diode device - Google Patents
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- CN109119487B CN109119487B CN201810961371.4A CN201810961371A CN109119487B CN 109119487 B CN109119487 B CN 109119487B CN 201810961371 A CN201810961371 A CN 201810961371A CN 109119487 B CN109119487 B CN 109119487B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
A super barrier diode device belongs to the technical field of semiconductor power devices. The cell structure comprises a cathode metal, an N + semiconductor substrate and an N-semiconductor drift region which are sequentially arranged from bottom to top, wherein a P-type semiconductor base region is arranged on the left side of the top layer of the N-semiconductor drift region, and a P + semiconductor contact region and an N + semiconductor source region which are closely contacted are sequentially arranged in parallel on the left side of the top layer of the P-type semiconductor base region from left to right; the upper surface of the right side of the N + semiconductor source region, the upper surface of the P-type semiconductor base region on the right side of the N + semiconductor source region and the upper surface of the N-semiconductor drift region on the right side of the P-type semiconductor base region are provided with groove structures; a grid structure is arranged on the groove structure and comprises a dielectric layer, polycrystalline silicon and anode metal which are arranged from bottom to top, and the bottommost part of the lower surface of the polycrystalline silicon is lower than the topmost part of the groove structure; an anode metal is disposed on an upper surface of the super barrier diode device. The invention improves the forward conduction current level and the voltage blocking capability of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a super barrier diode device structure.
Background
The human era has entered the 21 st century, and although there are many forms of new energy sources, such as wind, nuclear, solar and geothermal, the world's energy production and consumption will be dominated by fossil energy, which will still occupy the most important place of the human's energy needs for a long period of time. The large amount and long-term use of fossil energy has inevitably led to a series of problems which are associated with the worsening of global environmental problems such as global warming at present. A significant proportion of fossil energy is converted into electrical energy. Electric energy is one of the main forms of energy which can be directly utilized by human beings, and the improvement of the use efficiency of the electric energy is an important solution for solving the problem of world energy. The electric power system is a necessary way for human beings to utilize electric energy and improve the use efficiency of the electric energy, and the electric power system reflects the modernization degree of the electric power system on the aspects of electric energy transportation, management and use efficiency and further reflects the utilization efficiency of energy resources by human beings. The high-efficiency use of energy resources has great significance for human sustainable development. Specifically, the power system mainly adjusts, measures, controls, protects, schedules, communicates, and the like, in the process of generating electric energy, and in the process, the power semiconductor device plays a central role. That is, the performance of the power semiconductor device determines the performance of the power system. The performance of the power semiconductor device and the module thereof is good and bad, which is about the sustainable development of human beings.
The power device is mainly composed of a thyristor, a power PIN device, a power bipolar junction device, a Schottky barrier diode, a power MOSFET and an insulated gate field effect transistor, and is widely applied in the full power range, and the silicon-based power device occupies the leading market of the power semiconductor device by virtue of long history and mature design technology and process technology. However, since researchers have studied the mechanism of the silicon-based power device more thoroughly, the performance of the silicon-based power device is close to the theoretical limit of the silicon material, and it is difficult to achieve a large improvement in performance by designing and optimizing the silicon-based power device.
Wide bandgap semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN), also called next-generation semiconductor materials, have attracted the attention of researchers due to their excellent material characteristics. Silicon carbide material is a typical representative of the third generation semiconductor material, and is one of the most mature and widely applied wide bandgap semiconductor materials in the crystal growth technology and device manufacturing level at present. Compared with silicon materials, the silicon material has larger forbidden band width, higher thermal conductivity, higher electron saturation drift velocity and critical breakdown electric field which is 10 times that of the silicon materials, so that the silicon material becomes an ideal semiconductor material in the application occasions of high temperature, high frequency, high power and radiation resistance. Since the silicon carbide power device can significantly reduce the energy consumption of electronic equipment, the silicon carbide power device has the name of a green energy device which drives a new energy revolution.
Silicon carbide diodes are one of the leading products in which silicon carbide materials are used as base materials for power devices. In the development and design process of a common silicon carbide diode, the forward conduction voltage drop of a conventional silicon carbide PIN diode is large (about 3.1V) and the reverse recovery characteristic is poor, while the silicon carbide Schottky diode (SBD) has large electric leakage and poor high-temperature reliability, and a brand new power device which can overcome the defects of the two devices is required in various application occasions. The silicon carbide super barrier diode makes up the defects of two traditional diodes, has lower forward conduction voltage drop and smaller leakage current, and has the advantage of being in accordance with the theme of energy conservation and emission reduction in the modern society, so that the silicon carbide super barrier diode has a certain attention on the market of power devices. The traditional cellular structure of the super barrier diode is shown in fig. 1, however, as a channel type device, the super barrier diode has the defects of low forward conduction current density, poor reverse blocking capability and the like, and the defects limit the further application and popularization of the super barrier diode in the power device market.
Disclosure of Invention
Aiming at the problems of low forward conduction current density and poor reverse blocking capability of the traditional super barrier diode, the invention provides a super barrier diode device which can improve the forward conduction current density and the voltage blocking capability and obviously improve the forward conduction current level of the device by arranging a groove structure; by adding the heterojunction, the multi-sub current branches of the device in the on state are increased, and the forward conducting current level of the device is improved again; in addition, the super junction structure is provided for improving the voltage blocking capability of the device, reducing the forward on-resistance of the device and obtaining a good compromise relationship between reverse blocking and forward voltage drop.
The technical scheme of the invention is as follows:
a super barrier diode device comprises a cell structure which comprises a cathode metal 9, an N + semiconductor substrate 8 and an N-semiconductor drift region 7 which are sequentially arranged from bottom to top, wherein a P-type semiconductor base region 6 is arranged on the left side of the top layer of the N-semiconductor drift region 7, a P + semiconductor contact region 5 and an N + semiconductor source region 4 which are closely contacted are sequentially arranged on the left side of the top layer of the P-type semiconductor base region 6 side by side from left to right, and the depth of the N + semiconductor source region 4 is not more than that of the P + semiconductor contact region 5;
a trench structure is arranged on the upper surface of the right side of the N + semiconductor source region 4, the upper surface of the P-type semiconductor base region 6 on the right side of the N + semiconductor source region 4 and the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, and the depth of the bottommost part of the lower surface of the trench structure is smaller than that of the N + semiconductor source region 4; the gate structure is arranged on the trench structure and comprises an upper surface of the trench structure and an upper surface of an N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, the gate structure comprises a dielectric layer 3, polycrystalline silicon 2 and anode metal 1 which are arranged from bottom to top, and the bottommost part of the lower surface of the polycrystalline silicon 2 is lower than the topmost part of the trench structure; the anode metal 1 is disposed on an upper surface of the super barrier diode device.
Specifically, the trench structure may include only the dielectric layer 3 and the polysilicon 2, that is, the bottommost portion of the lower surface of the polysilicon 2 is lower than the topmost portion of the trench structure, and the bottommost portion of the lower surface of the anode metal 1 is higher than the topmost portion of the trench structure; the trench structure may further include the anode metal 1, that is, a bottommost portion of a lower surface of the anode metal 1 is lower than a topmost portion of the trench structure.
Specifically, a groove may be formed in the trench structure, and the groove may be a structure extending from the N + semiconductor source region 4 to the N-semiconductor drift region 7 in the X direction and penetrating through the P-type semiconductor base region 6, or a plurality of discontinuous grooves may be formed in the Z direction.
Specifically, the trench structure may be only disposed on the left upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, or may extend rightward to cover the entire upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6; when the trench structure is only arranged on the upper surface of the left side of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, the gate structure is arranged on the upper surface of the trench structure and the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, which is not arranged on the trench structure, in addition to the upper surface of the trench structure.
Specifically, the dielectric layer 3 on the upper surface of the right side of the N-semiconductor drift region 7 is replaced by the polysilicon 2, the polysilicon 2 is directly contacted with the N-semiconductor drift region 7 to form a heterojunction, the heterojunction has a rectifying characteristic, and the heterojunction can be formed in a trench structure or a part of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6 where the trench structure is not arranged.
Specifically, a super junction structure is arranged in an N-semiconductor drift region 7 between a P-type semiconductor base region 6 and an N + semiconductor substrate 8, the super junction structure comprises an N column and a P column which are alternately arranged, the N column is a first N-type doping 7a, the P column is a P-type doping 10, and the N column and the P column meet the requirement that the charge quantity is equal to Qn (Qp) by controlling and adjusting process parameters, and are fully depleted in a blocking state; the N-semiconductor drift region 7 on the super junction structure and located on the right side of the P-type semiconductor base region 6 is replaced by a second N-type doping 7b, and the doping concentration of the first N-type doping 7a and the doping concentration of the second N-type doping 7b are higher than that of the N-semiconductor drift region 7.
Specifically, a P-type semiconductor buried layer 11 is disposed in the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, and the N-semiconductor drift region 7 is not divided into two parts by the P-type semiconductor buried layer 11, so that the P-type semiconductor buried layer 11 may be disposed to be continuously distributed in the Z direction and not to be in contact with the right boundary of the N-semiconductor drift region 7 in the X direction, or may be disposed to be in contact with the right boundary of the P-type semiconductor base region 6 and the right boundary of the N-semiconductor drift region 7 in the X direction and to be discontinuously distributed in the Z direction.
Specifically, when the super barrier diode device has no heterojunction, the bulk material of the super barrier diode device is one of silicon, silicon carbide, gallium arsenide, germanium, diamond, silicon germanium, gallium oxide, or gallium nitride.
Specifically, when the super barrier diode device has a heterojunction, the wide bandgap material and the narrow bandgap material in the heterojunction may be silicon carbide and silicon material, respectively, or may not be limited to silicon carbide and silicon material, and may be also applicable to combinations of other wide bandgap materials and narrow bandgap materials.
The invention provides a method for manufacturing a super barrier diode device, which comprises the following steps:
step 1: sequentially laminating an N + semiconductor substrate 8 and an N-semiconductor drift region 7 from bottom to top;
step 2: forming a P-type semiconductor base region 6 on the left side of the top layer of the N-semiconductor drift region 7;
and 3, step 3: forming a P + semiconductor contact region 5 on the left side of the top layer of the P-type semiconductor base region 6;
and 4, step 4: forming an N + semiconductor source region 4 on the top layer of the P-type semiconductor base region 6 and positioned at the right side of the P + semiconductor contact region 5, wherein the N + semiconductor source region 4 is tightly contacted with the P + semiconductor contact region 5 and the depth of the N + semiconductor source region 4 does not exceed the depth of the P + semiconductor contact region 5;
and 5, step 5: etching grooves on the upper surface of the right side of the N + semiconductor source region 4, the upper surface of the P-type semiconductor base region 6 on the right side of the N + semiconductor source region 4 and the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6;
and 6, step 6: forming a dielectric layer 3 on the upper surface and the side wall of the groove;
and 7, step 7: depositing a layer of polycrystalline silicon on the upper surface of the whole device, and removing the unnecessary polycrystalline silicon through etching to form polycrystalline silicon 2;
and 8, step 8: and forming cathode metal 9 on the lower surface of the N + semiconductor substrate 8, and forming anode metal 1 on the upper surface of the whole device.
Specifically, in the step 1, a silicon carbide wafer with appropriate resistivity and thickness is selected for manufacturing the N + semiconductor substrate 8 and the N-semiconductor drift region 7.
Specifically, in the step 2, aluminum ion implantation is performed through a high-energy ion implantation process or the P-type semiconductor base region 6 is formed in an epitaxial manner.
Specifically, in step 3, aluminum ion implantation is performed by using a PSD mask through photolithography, ion implantation, and the like to form the P + semiconductor contact region 5.
Specifically, in the step 4, through the processes of photolithography, ion implantation, and the like, phosphorus ion implantation is performed by using an NSD mask, so as to form the N + semiconductor source region 4.
Specifically, after the N + semiconductor source region 4 is formed in the 4 th step, a reverse doping implantation of a P-type semiconductor impurity is performed in the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, a P-type semiconductor buried layer 11 is provided, and a layer of N-type impurity is implanted into the surface of the P-type semiconductor buried layer 11, wherein the N-type impurity may be the N-semiconductor drift region 7.
Specifically, in the step 5, a Trench structure in concave-convex distribution is etched on the upper surface of the right side of the N + semiconductor source region 4, the upper surface of the P-type semiconductor base region 6 on the right side of the N + semiconductor source region 4 and the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6 by using a Trench mask through a Trench etching process, wherein the Trench structure can etch a groove in the direction along which the N + semiconductor source region 4 and the P-type semiconductor base region 6 are contacted and extended, or a plurality of grooves are continuously etched, and each groove is a structure extending from the N + semiconductor source region 4 to the N-semiconductor drift region 7 and penetrating through the P-type semiconductor base region 6.
Specifically, in the step 6, the dielectric layer 3 is formed through dry oxygen oxidation and etching processes, and when the trench structure only covers the left side of the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, the dielectric layer 3 is also formed on the upper surface without the trench structure.
Specifically, the polysilicon deposited in step 7 may be N-type polysilicon or P-type polysilicon.
Specifically, after the dielectric layer 3 is formed in the 6 th step, part of the dielectric layer 3 on the right side of the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6 is etched, so that when polycrystalline silicon is deposited in the 7 th step to form the polycrystalline silicon 2, part of the polycrystalline silicon is in direct contact with the N-semiconductor drift region 7, and when the N-semiconductor drift region 7 is an N-silicon carbide drift region 7, the N-silicon carbide drift region 7 and the polycrystalline silicon 2 form a Si/SiC heterojunction.
Specifically, when the polysilicon is etched in the step 7, the polysilicon in a part of the trench is etched, so that when the anode metal 1 is deposited in the step 8, the bottom depth of the part of the anode metal 1 is deeper than the top of the trench.
Specifically, after step 1 is completed, the N-semiconductor drift region 7 is completely etched, P columns formed by multiple times of epitaxy, thermal diffusion and etching and N-type epitaxial layers are distributed alternately, and appropriate doping concentrations and widths of the N columns and the P columns are formed through process control, so that the charge numbers of the N columns and the P columns are the same, that is, a super junction structure is formed.
Specifically, the anode metal 1 and the cathode metal 9 are respectively formed in step 8 through deposition, photolithography and etching processes.
Specifically, when the trench is etched in the step 5, the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6 is completely etched, so that the trench completely covers the upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6.
The principles of the present invention will be illustrated below by taking silicon carbide as the bulk material of the present invention, but it should be noted that the bulk material of the present invention is not limited to silicon carbide.
The forward conduction voltage drop of a conventional silicon carbide PIN diode is large (about 3.1V), while the leakage of a silicon carbide schottky diode (SBD) is large and its high temperature reliability is poor. Although the silicon carbide super barrier diode makes up the defects of two traditional diodes, has lower forward conduction voltage drop and small leakage current, the silicon carbide super barrier diode is used as a channel type device and has the natural defect of low forward conduction current density. The shortage causes the application and popularization of the device in the market to be greatly limited. The present invention provides a structure capable of optimizing the above-mentioned deficiencies of the silicon carbide super barrier diode and optimizing other electrical properties through structural improvement, and fig. 2 is a cross-sectional view of the super barrier diode on XY plane, wherein a schematic view of the YZ plane structure of the gate structure on the P-type silicon carbide base region 6 is shown in fig. 3. The operating principle of the schottky diode SBR is briefly explained as follows: through process control, parameters such as the doping concentration of the polysilicon 2, the thickness of the dielectric layer 3, the number of charges of the dielectric layer, the doping concentration of the P-type silicon carbide base region 6 and the like are adjusted, so that the polysilicon 2, the dielectric layer 3 and the P-type silicon carbide base region 6 form a metal-insulator-semiconductor MIS structure, and the threshold voltage of the metal-insulator-semiconductor MIS structure is about 0.1V. When the voltage of the anode metal 1 is close to 0.1V, a small part of electron current flows through the N-silicon carbide drift region 7, the P-type silicon carbide base region 6 and the N-type silicon carbide source region 4 due to the existence of the current of the sub-threshold region of the MIS structure, and the electron current causes the voltage drop on the P-type silicon carbide base region 6. The potential distribution on both sides of the dielectric layer 3 is shown in fig. 5, wherein marked points a1, a2, b1 and b2 on the XY plane are shown in fig. 4, a1 and b1 are two points on the contact surface of the P-type silicon carbide base region 6 and the polysilicon 2 respectively, wherein a1 point is close to the N-type silicon carbide source region 4, b1 point is far away from the N-type silicon carbide source region 4, a2 and b2 are two points on the contact surface of the polysilicon 2 and the dielectric layer 3 respectively, and the X coordinates thereof correspond to the X coordinates of the points a1 and b1 respectively. As can be seen from fig. 5, the potential difference between points a1 and a2 is almost zero, and the potential difference in the horizontal direction gradually increases from point a to point b. This difference makes it unnecessary to add the anode voltage to 0.1V (i.e., the gate voltage of the super barrier structure), and the device has a significant current flow, i.e., the device is in an on-state at this time. For the power device, it normally works above a higher voltage, so for the super barrier diode provided by the present invention, the turn-on voltage is lower than 0.1V, i.e. close to 0V.
Because the super-barrier diode belongs to a channel type device, when conducting in the forward direction, the forward conducting current density is too low under the influence of the thin conducting channel. According to the structure, the surface structure of the traditional P-type silicon carbide base region 6 is improved, a groove structure is formed on the surface of the P-type silicon carbide base region 6 on the right side of the P + semiconductor contact region 5, and a grid structure is formed on the groove structure, so that compared with the traditional super barrier diode device, the area of an inversion layer is greatly increased, as shown in fig. 6. At the same gate voltage, the forward conduction current increases significantly as shown in fig. 7. The improvement overcomes the defect that the forward conduction current level of the traditional super-barrier diode is low, and the forward conduction performance of the device is obviously improved.
Meanwhile, other improvements are made on the basis of the method. In some embodiments, the heterojunction is formed by the direct contact of the polysilicon 2 and the N-semiconductor drift region 7, so that the forward conduction current level of the super barrier device is further improved. For convenience of explaining the improvement, functional blocks of the improved super barrier diode are marked on the left side of fig. 10, wherein a functional block a is a super barrier structure part; the B functional block is a Si/SiC heterojunction part. Since the forward turn-on voltage of the Si/SiC heterojunction is greater than 0.1V, it can be considered that no current flows through the Si/SiC heterojunction at the time of conduction of the super-barrier structure, i.e., the potential of the polysilicon 2 is the same everywhere. When the anode voltage further rises to reach the Si/SiC heterojunction knee voltage, the Si/SiC heterojunction is conducted. For convenience of showing the I-V curve of the whole device when the Si/SiC heterojunction is conducted, the polysilicon is assumed to be P-type polysilicon. The knee voltage of the P-type poly/N-type silicon carbide heterojunction is about 1.1V. Therefore, when the whole device is turned on in the forward direction, the forward I-V curve is as shown in the right diagram of fig. 10. As can be seen from fig. 10, the forward conduction current level of the device is more improved.
In addition, in some embodiments, the structure of the present invention is further improved, a super junction structure is disposed in the N-semiconductor drift region 7 between the P-type semiconductor base region 6 and the N + semiconductor substrate 8, as shown in fig. 11, an epitaxial layer of the super junction structure is adopted, forward and reverse I-V curves of the device are shown in fig. 12, and it can be seen from fig. 12 that the epitaxial layer formed by the super junction structure significantly improves the voltage blocking capability of the inventive device, thereby obtaining a better compromise characteristic of forward voltage drop and breakdown voltage.
By combining the above analysis, the beneficial effects of the invention are: according to the super barrier diode device, the forward conducting current level of the device is obviously improved by forming the groove structure, so that the rectifying efficiency of the diode is improved, the on-state loss of the device is reduced, and the energy resource is saved; the heterojunction is added, so that the forward conduction current level of the device is further improved, and the rectification efficiency of the diode is further improved; the super junction structure is added, and the voltage blocking capability of the device is obviously improved, so that the super junction structure has better compromise characteristics of forward voltage drop and breakdown voltage.
Drawings
Fig. 1 is a schematic diagram of a conventional silicon carbide super barrier diode device cell structure.
Fig. 2 is a schematic diagram of a super barrier diode device cell structure provided in embodiment 1 of the present invention.
Fig. 3 is a schematic diagram for further explaining the structure of embodiment 1 of the present invention.
Fig. 4 is a schematic illustration of a super barrier diode device provided in embodiment 1 of the present invention.
Fig. 5 is a schematic illustration of a super barrier diode device provided in embodiment 1 of the present invention.
Fig. 6 is a schematic illustration of a super barrier diode device provided in embodiment 1 of the present invention.
Fig. 7 is a schematic illustration of a super barrier diode device provided in embodiment 1 of the present invention.
Fig. 8 is a schematic view of the P-type semiconductor base region 6 of the super barrier heterojunction diode device provided in embodiment 2 of the present invention in YZ plane.
Fig. 9 is a schematic diagram of a super barrier heterojunction diode device cell structure according to embodiment 3 of the present invention.
Fig. 10 is a schematic illustration of a super barrier heterojunction diode device provided in embodiment 3 of the present invention.
Fig. 11 is a schematic diagram of a super barrier heterojunction diode device cell structure according to embodiment 4 of the present invention.
Fig. 12 is a schematic illustration of a super barrier heterojunction diode device provided in embodiment 4 of the present invention.
Fig. 13 is a schematic diagram of a super barrier heterojunction diode device cell structure according to embodiment 5 of the present invention.
Fig. 14 is a schematic diagram of a super barrier heterojunction diode device cell structure according to embodiment 6 of the present invention.
Fig. 15 is a schematic diagram of a super barrier heterojunction diode device cell structure according to embodiment 7 of the present invention.
Fig. 16 is a schematic view of a silicon carbide substrate provided in example 8 of the present invention.
Fig. 17 is a schematic diagram of forming the P-type silicon carbide base region 6 by an ion implantation process according to embodiment 8 of the present invention.
Fig. 18 is a schematic view of P + silicon carbide contact region 5 formed by photolithography, ion implantation, or the like in embodiment 8 of the present invention.
Fig. 19 is a schematic view of the N + silicon carbide source region 4 formed by the steps of photolithography, ion implantation, and the like according to example 8 of the present invention.
Fig. 20 is a schematic diagram of a Trench etched to a specified size by using a Trench mask through a Trench etching process according to embodiment 8 of the present invention.
Fig. 21 is a schematic diagram of forming a dielectric layer 3 by dry oxygen oxidation and photolithography processes according to embodiment 8 of the present invention.
Fig. 22 is a schematic diagram of forming polysilicon 2 by deposition and etching processes according to embodiment 8 of the present invention.
Fig. 23 is a schematic diagram of forming the anode metal 1 and the cathode metal 9 by deposition, photolithography and etching processes according to embodiment 8 of the present invention.
Detailed Description
The technical solutions and the implementation principles of the present invention are described in detail below with reference to the accompanying drawings and the specific embodiments, which are used for explaining the present invention and not for limiting the scope of the present invention.
Example 1:
in this embodiment, a structure of a 1200V super barrier diode device is taken as an example, a bulk material is silicon carbide, and a schematic diagram of a cell thereof is shown in fig. 2. The cathode metal structure comprises a cathode metal 9, an N + silicon carbide substrate 8 and an N-silicon carbide drift region 7 which are sequentially arranged from bottom to top, wherein a P-type silicon carbide base region 6 is arranged on the left side of the top layer of the N-silicon carbide drift region 7, a P + silicon carbide contact region 5 and an N + silicon carbide source region 4 which are in close contact are sequentially arranged in parallel on the left side of the top layer of the P-type silicon carbide base region 6 from left to right, and the depth of the N + silicon carbide source region 4 is not more than that of the P + silicon carbide contact region 5; the upper surface of the right side of the N + silicon carbide source region 4, the upper surface of the P-type silicon carbide base region 6 on the right side of the N + silicon carbide source region 4 and the upper surface of the N-silicon carbide drift region 7 on the right side of the P-type silicon carbide base region 6 are provided with groove structures, and the depth of the bottommost part of the lower surface of each groove structure is smaller than that of the N + silicon carbide source region 4; a grid structure is arranged on the groove structure, and the grid structure comprises a dielectric layer 3, polycrystalline silicon 2 and anode metal 1 which are arranged from bottom to top; an anode metal 1 is provided on the upper surface of the super barrier diode device. In the embodiment, only the dielectric layer 3 and the polysilicon 2 are arranged inside the trench structure, that is, the bottommost part of the lower surface of the polysilicon 2 is lower than the topmost part of the trench structure, and the bottommost part of the lower surface of the anode metal 1 is higher than the topmost part of the trench structure.
Wherein, the thickness of the anode metal 1 and the cathode metal 9 is 0.5-2 μm, and the width is 0.5-2 μm; the doping concentration of the N + silicon carbide substrate 8 is 1e 18-9 e18/cm3The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide epitaxy 7 is 2e 15-8 e15/cm3The thickness is 5-8 μm, and the width is 0.5-2 μm; the P + silicon carbide base region 6 has a thickness of about 0.3 μm to about 0.4 μm, a width of about 0.1 μm to about 0.5 μm, and a doping concentration of about 1e16 to about 1e17/cm3(ii) a The P + silicon carbide contact region 5 has a thickness of about 0.3 μm to about 0.4 μm, a width of about 0.2 μm to about 1 μm, and a doping concentration of about 1e18 to about 2e19/cm3(ii) a The N + silicon carbide source region 4 has a thickness of about 0.15 μm to about 0.2 μm, a width of about 0.1 μm to about 0.5 μm, and a doping concentration of about 1e18 to about 2e19/cm3(ii) a The depth of the groove on the upper part of the P-type silicon carbide base area 6 is about 0.1-0.18 mu m, and the groove spacing is about 0.1-0.2 mu m; the thickness of the dielectric layer 3 is about 10 nm-50 nm; the thickness of the polysilicon 2 is about 0.8 μm to 1.6 μm. The super barrier diode provided by the embodiment is used for improving the forward conduction performance of the device by forming a three-dimensional super barrier structure.
Example 2:
this embodiment is modified to a certain extent with respect to embodiment 1, and has a structure substantially the same as that of embodiment 1, except that the trench structure further has an anode metal 1 inside, i.e. the bottommost depth of the anode metal 1 is deeper than the topmost depth of the trench structure, as shown in fig. 8. The improvement can reduce the gate resistance, improve the charging speed of gate charges, further optimize the rectification performance of the device and further improve the gate control capability of the device.
Example 3:
this embodiment is modified to some extent with respect to embodiment 1 and embodiment 2, and has a structure substantially the same as that of embodiment 2, except that the right side of the upper surface of the N-SiC drift region 7 on the right side of the P-type SiC base region 6 does not have a dielectric layer 3, the dielectric layer 3 is replaced by polysilicon 2, the polysilicon 2 and the N-SiC drift region 7 form a Si/SiC heterojunction, and the junction width is about 0.1 μm to 0.4 μm, as shown in fig. 9. The super-barrier diode in the embodiment has a three-dimensional super-barrier structure and a Si/SiC heterojunction, and the heterojunction increases multi-sub current branches of the device in an on state, so that the forward conducting current level of the diode in the embodiment is improved again.
Example 4:
this embodiment is modified to some extent with respect to embodiment 1, embodiment 2, and embodiment 3, and takes the modification of embodiment 3 as an example, and the structure thereof is substantially the same as that of embodiment 3, except that a super junction structure may be provided in the N-semiconductor drift region 7 between the P-type semiconductor base region 6 and the N + semiconductor substrate 8, as shown in fig. 11. By controlling and adjusting the process parameters, the N column and the P column meet the requirement of equal charge quantity Qn-Qp. The super-barrier diode in the embodiment has a three-dimensional super-barrier structure, a Si/SiC heterojunction and a super-junction structure, the super-junction structure improves the voltage blocking capability of a device by optimizing the electric field distribution in a blocking mode, and simultaneously reduces the forward on-resistance of the device, so that the better compromise characteristic of the forward voltage drop and the voltage blocking capability is obtained.
Example 5:
the present embodiment is modified to some extent as to embodiments 1 to 4, and the structure thereof is substantially the same as that of the above embodiments, except that the etching area is enlarged when the trench structure is etched, the trench structure is formed on the entire upper surface of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, and the gate structure is formed on the surface of the trench. During forward operation, the improvement is beneficial to forming an accumulation layer below a gate structure on the upper part of the N-semiconductor drift region 7 on the right side of the P-type semiconductor base region 6, so that adverse effects brought by JFET (junction field effect transistor) effect are reduced, and the improvement has a great effect on the forward conduction performance of a device. At the same time, the improvement has substantially no effect on the reverse process, so the improvement is favorable for the improvement of the device performance. The improved structure is shown in fig. 13.
Example 6:
the present embodiment is modified to some extent from embodiments 1 to 5, and the structure thereof is substantially the same as that of the above embodiments, except that a P-type buried silicon carbide layer 11 is disposed inside the N-semiconductor drift region 7 on the right side of the P-type silicon carbide base region 6, and the P-type buried silicon carbide layer 11 is not in contact with the right boundary of the N-semiconductor drift region 7 in the X direction, but is continuously distributed in the Z direction, as shown in fig. 14. The improvement ensures that the surface SBR structure is well protected, and the electric leakage is further reduced.
Example 7:
this embodiment is modified to some extent with respect to embodiment 6, and has substantially the same structure as the above-described embodiment, except that the P-type buried silicon carbide layer 11 is in contact with the right boundary of the P-type silicon carbide base region 6 and the right boundary of the N-semiconductor drift region 7 in the X direction, but is discontinuously distributed in the Z direction, as shown in fig. 15. The improvement also ensures that the surface SBR structure is well protected, and the electric leakage is further reduced.
Example 8:
in this embodiment, a method for manufacturing a diode device of 1200V is also taken as an example to describe the specific implementation manner of the above embodiments 1 to 7, and devices with different performance parameters can be prepared according to actual requirements according to common knowledge in the art.
Step 1: and selecting silicon carbide wafers with proper resistivity and thickness, and sequentially laminating the silicon carbide wafers from bottom to top to manufacture an N-silicon carbide drift region 7 and an N + silicon carbide substrate 8. Wherein the doping concentration of the N + silicon carbide substrate 8 is 1e 18-9 e18/cm3The thickness is 0.5 to 1.5 μm, and the width is 0.5 to 2 μm; the doping concentration of the N-silicon carbide drift region 7 is 2e 15-8 e15/cm3The thickness is 5 μm to 8 μm, and the width is 0.5 μm to 2 μm, as shown in FIG. 16;
step 2: performing aluminum ion implantation with high-energy ion implantation energy of 1500-2000 keV to form a layer with thickness of 0.3-0.4 μm, width of 0.1-0.5 μm, and doping concentration of 1e 16-1 e17/cm on the left side of the top layer of the N-SiC drift region 73The P-type silicon carbide base region 6, this step alsoThe P-type silicon carbide base region 6 may be formed by means of epitaxy. The structure of the device after the P-type silicon carbide base region 6 is finally formed is shown in fig. 17;
and 3, step 3: performing aluminum ion implantation by using a PSD mask through the processes of photoetching, ion implantation and the like, wherein the implantation energy is about 1300-1700 keV, the thickness is about 0.3-0.4 mu m, the width is about 0.2-1 mu m, and the doping concentration is about 1e 18-2 e19/cm3P + silicon carbide contact region 5, as shown in fig. 18;
and 4, step 4: through the processes of photoetching, ion implantation and the like, phosphorus ion implantation is carried out by utilizing an NSD mask, the implantation energy is about 1300-1700 keV, the thickness of the P-type silicon carbide base region 6 top layer and the position of the P + silicon carbide contact region 5 right side is about 0.15-0.2 μm, the width is about 0.1-0.5 μm, and the doping concentration is about 1e 18-1 e19/cm3As shown in fig. 19, of the N + silicon carbide source region 4. Then activating impurities at 1600-1700 ℃;
and 5, step 5: through a Trench etching process, a Trench structure in concave-convex distribution is etched on the upper surface of the right side of the N + silicon carbide source region 4, the upper surface of the P-type silicon carbide base region 6 on the right side of the N + silicon carbide source region 4 and the upper surface of the N-silicon carbide drift region 7 on the right side of the P-type silicon carbide base region 6 by using a Trench mask, as shown in FIG. 20, wherein FIG. 20 is a Trench structure on the upper surface of the P-type silicon carbide base region 6, the depth of each Trench is about 0.1 μm to 0.18 μm, and the distance between every two trenches is about 0.1 μm to 0.2 μm;
and 6, step 6: forming a dielectric layer 3 with the thickness of about 10 nm-50 nm on the surface of the device and the side wall and the bottom of the groove in the groove structure by a dry oxygen oxidation process at the temperature of about 1100-1300 ℃, and removing the unnecessary dielectric layer 3 by etching as shown in fig. 21;
and 7, step 7: depositing a layer of polysilicon on the surface of the device through deposition and etching processes, removing the unnecessary polysilicon through etching to form polysilicon 2 with the thickness of about 0.8-1.6 microns, as shown in figure 22, wherein the polysilicon in the groove is not etched in the step;
and 8, step 8: the anode metal 1 and the cathode metal 9 with the thickness of 0.5-2 μm and the width of 0.5-2 μm are respectively formed by deposition, photoetching and etching processes, as shown in fig. 23. Thus, the device is completed. The YZ viewing angle structure above the P-type silicon carbide base region 6 is shown in fig. 3.
Further, after completing the N-type silicon carbide source region 4 in step 4, performing a counter doping implantation of a P-type semiconductor impurity in the N-silicon carbide drift region 7 on the right side of the P-type silicon carbide base region 6 to form a P-type semiconductor buried layer 11, and implanting a layer of N-type impurity, which may be the N-semiconductor drift region 7, on the surface of the P-type semiconductor buried layer 11, to form the P-type silicon carbide buried layer 11 as shown in fig. 14/15.
Further, the polysilicon deposited in step 7 may be either N-type polysilicon or P-type polysilicon.
Further, when the polysilicon 2 is etched in the 7 th step, the depth of the polysilicon 2 in a part of the groove can be etched to be about 0.05 μm to 0.15 μm, so that when the anode metal 1 is deposited in the 8 th step, the bottom depth of the part of the anode metal 1 is deeper than the top of the groove, as shown in fig. 8, which is beneficial to improving the grid control capability and further improving the forward conducting current level of the device.
Further, when the dielectric layer 3 is etched in the step 6, a part of the dielectric layer 3 on the upper right of the N-silicon carbide drift region 7 is removed by etching, so that when the polycrystalline silicon is deposited in the step 7, the formed polycrystalline silicon 2 is in contact with the N-silicon carbide drift region 7, and further a Si/SiC heterojunction is formed, wherein the width of the junction surface of the Si/SiC heterojunction is about 0.1-0.4 μm, as shown in FIG. 9.
Further, after step 1 is completed, the N-silicon carbide drift region 7 is completely etched, the P columns formed by multiple times of epitaxy, thermal diffusion and etching and the N-type epitaxial layer are distributed alternately, and appropriate doping concentrations and widths of the N columns and the P columns are formed through process control, so that the charge numbers of the N columns and the P columns are the same, that is, a super junction structure is formed, as shown in fig. 11.
Further, when the P-type silicon carbide base region 6 is etched in the step 5, the etching area may be enlarged, and a continuous groove structure is etched on the entire upper surface of the N-silicon carbide drift region 7 on the right side of the P-type silicon carbide base region 6, so that a gate structure is formed on the upper portion of the N-silicon carbide drift region 7 on the right side of the P-type silicon carbide base region 6 later, as shown in fig. 13.
It should also be claimed that: as can be known by those skilled in the art based on the basic knowledge in the art, in the diode device structure and process of the present invention, the N-type polysilicon may also be implemented by P-type polysilicon, P-type single crystal silicon, or N-type single crystal silicon; the dielectric material used can be silicon dioxide (SiO)2) This can also be achieved by using silicon nitride (Si)3N4) Hafnium oxide (HfO)2) Aluminum oxide (Al)2O3) And the high-K dielectric materials are realized. Meanwhile, the specific implementation mode of the manufacturing process can be adjusted according to actual needs.
Claims (7)
1. A super barrier diode device comprises a cell structure which comprises a cathode metal (9), an N + semiconductor substrate (8) and an N-semiconductor drift region (7) which are sequentially arranged from bottom to top, wherein a P-type semiconductor base region (6) is arranged on the left side of the top layer of the N-semiconductor drift region (7), a P + semiconductor contact region (5) and an N + semiconductor source region (4) which are closely contacted are sequentially arranged on the left side of the top layer of the P-type semiconductor base region (6) side by side from left to right, and the depth of the N + semiconductor source region (4) is not more than that of the P + semiconductor contact region (5);
the device is characterized in that a groove structure is arranged on the upper surface of the right side of the N + semiconductor source region (4), the upper surface of a P-type semiconductor base region (6) on the right side of the N + semiconductor source region (4) and the upper surface of an N-semiconductor drift region (7) on the right side of the P-type semiconductor base region (6), the central axis of the groove structure is vertical to the transverse direction of the whole device, and the depth of the bottommost part of the lower surface of the groove structure is smaller than that of the N + semiconductor source region (4); the groove structure is filled with polycrystalline silicon (2), and the polycrystalline silicon (2) is directly contacted with the N-semiconductor drift region (7) to form a heterojunction; the surface of the polysilicon (2) is provided with anode metal (1).
2. The super barrier diode device according to claim 1, wherein the P-type semiconductor base region (6) and the N + semiconductor substrate (8) have a super junction structure therebetween, and the super junction structure comprises N columns and P columns which are alternately arranged.
3. The super barrier diode device according to claim 1 or 2, wherein the trench structure covers a left upper surface of the N-semiconductor drift region (7) on a right side of the P-type semiconductor base region (6).
4. The super barrier diode device according to claim 1, wherein a P-type buried semiconductor layer (11) is provided within the N-semiconductor drift region (7) to the right of the P-type semiconductor base region (6), the P-type buried semiconductor layer (11) not dividing the N-semiconductor drift region (7) into two parts.
5. The super barrier diode device according to claim 1, wherein a topmost portion of the trench structure is higher than a bottommost portion of a lower surface of the anode metal (1).
6. The super barrier diode device according to any of claims 1 to 5, wherein the body material of the super barrier diode device is one of silicon, silicon carbide, gallium arsenide, germanium, diamond, silicon germanium, gallium oxide or gallium nitride.
7. The super barrier diode device of claim 1, wherein the wide and narrow bandgap materials in the heterojunction are silicon carbide and silicon material, respectively.
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| CN104769715A (en) * | 2012-07-31 | 2015-07-08 | 硅联纳半导体(美国)有限公司 | Power device integration on a common substrate |
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