CN109119426B

CN109119426B - 3D memory device

Info

Publication number: CN109119426B
Application number: CN201811139601.5A
Authority: CN
Inventors: 胡斌; 肖莉红
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2018-09-28
Filing date: 2018-09-28
Publication date: 2024-04-16
Anticipated expiration: 2038-09-28
Also published as: CN109119426A

Abstract

The application discloses 3D memory device, its characterized in that includes: a CMOS circuit including a first bonding surface, and a first external pad exposed on the first bonding surface; and a memory cell array including a second bonding surface, and a second external pad exposed on the second bonding surface, wherein the first bonding surface of the CMOS circuit and the second bonding surface of the memory cell array are in contact with each other, the first external pad and the second external pad are bonded to each other, thereby achieving electrical connection between the CMOS circuit and the memory cell array, the CMOS circuit further includes a plurality of first grooves formed on the first bonding surface, and/or the memory cell array further includes a plurality of second grooves formed on the second bonding surface, the plurality of first grooves and the plurality of second grooves forming heat dissipation channels. The invention can improve the yield and the reliability of the 3D memory device by providing the heat dissipation channel on the bonding surface of the CMOS circuit and the memory cell array.

Description

3D memory device

Technical Field

The invention relates to the technical field of memories, in particular to a 3D memory device.

Background

The increase in memory density of memory devices is closely related to the progress of semiconductor manufacturing processes. As feature sizes of semiconductor fabrication processes become smaller, memory density of memory devices becomes higher. In order to further increase the storage density, three-dimensional structured memory devices (i.e., 3D memory devices) have been developed. The 3D memory device includes a plurality of memory cells stacked in a vertical direction, can improve integration in multiple per unit area of a wafer, and can reduce cost.

Existing 3D memory devices are mainly used as nonvolatile flash memories. Two main non-volatile flash technologies employ NAND and NOR architectures, respectively. The read speed in the NAND memory device is slightly slower, but the write speed is fast, the erase operation is simple, and smaller memory cells can be realized, thereby achieving higher memory density, as compared to the NOR memory device. Therefore, 3D memory devices employing NAND structures have found wide application.

In a 3D memory device of a NAND structure, a CMOS circuit is formed using a semiconductor substrate, a memory cell array is formed using a stacked structure including a selection transistor and a gate conductor of the memory transistor, and then the CMOS circuit and the memory cell array are bonded to each other. In the 3D memory device, a large number of metal wirings are used to provide electrical connection between the CMOS circuit and the memory cell array, and an increase in wiring density will affect the yield and reliability of the 3D memory device. Further improvements in the structure of 3D memory devices and methods of manufacturing the same are desired to increase the yield and reliability of 3D memory devices.

Disclosure of Invention

In view of the above, it is an object of the present invention to provide a 3D memory device in which grooves are formed on bonding surfaces of a CMOS circuit and a memory cell array to provide heat dissipation channels, thereby improving yield and reliability of the 3D memory device.

According to an embodiment of the present invention, there is provided a 3D memory device including: a CMOS circuit including a first bonding surface and a first external pad exposed on the first bonding surface; and a memory cell array including a second bonding surface and a second external pad exposed on the second bonding surface, wherein the first bonding surface of the CMOS circuit and the second bonding surface of the memory cell array are in contact with each other, the first external pad and the second external pad are bonded to each other, thereby achieving electrical connection between the CMOS circuit and the memory cell array, the CMOS circuit further includes a plurality of first grooves formed on the first bonding surface, and/or the memory cell array further includes a plurality of second grooves formed on the second bonding surface, the plurality of first grooves and the plurality of second grooves forming heat dissipation channels.

Preferably, the plurality of first grooves extend laterally on the first bonding surface from the first sidewall to the second sidewall of the CMOS circuit, and the plurality of second grooves extend laterally on the second bonding surface from the first sidewall to the second sidewall of the memory cell array.

Preferably, the first plurality of grooves and the second plurality of grooves are connected to each other to form an integral cavity.

Preferably, the CMOS circuit and the memory cell array each include a respective plurality of wiring layers extending laterally.

Preferably, the CMOS circuit and the memory cell array each include a respective plurality of conductive vias for providing electrical connection of the plurality of wiring layers to each other.

Preferably, the plurality of first grooves extend inward from the first bonding face of the CMOS circuit to the wiring layer of the CMOS circuit, and the plurality of second grooves extend inward from the second bonding face of the memory cell array to the wiring layer of the memory cell array.

Preferably, the plurality of first grooves and the plurality of second grooves are filled with a thermally conductive material.

Preferably, the CMOS circuit further comprises: a semiconductor substrate; a plurality of transistors located in the semiconductor substrate; a plurality of contact pads on the semiconductor substrate and connected to the plurality of transistors; and an insulating layer on the semiconductor substrate, wherein the plurality of wiring layers and the plurality of conductive vias are located in the insulating layer, the first external pad is located on the insulating layer, the first bonding surface is a free surface of the insulating layer, and the plurality of contact pads are connected to the respective first external pads via the plurality of wiring layers and the plurality of conductive vias.

Preferably, the memory cell array further includes: a semiconductor substrate; a common source region located in the semiconductor substrate; a gate stack structure on the semiconductor substrate, the gate stack structure comprising a plurality of levels of gate conductors; a plurality of channel pillars extending through the gate stack; a plurality of contact pads on the gate stack; and an insulating layer on the gate stack structure, wherein first ends of the plurality of channel pillars extend to the common source region, second ends are connected to corresponding contact pads, the plurality of layers of gate conductors are respectively connected to corresponding contact pads, the plurality of wiring layers and the plurality of conductive vias are located in the insulating layer, the second external pad is located on the insulating layer, the second bonding surface is a free surface of the insulating layer, and the plurality of contact pads are connected to corresponding second external pads via the plurality of wiring layers and the plurality of conductive vias.

Preferably, the plurality of channel pillars and the plurality of levels of gate conductors form a memory transistor and a select transistor.

Preferably, the memory cell array further includes: and the plurality of dummy channel columns penetrate through the gate stack structure, and are not connected with the contact welding disc.

Preferably, the memory cell array further includes: at least one additional conductive via extending through the gate stack structure, the at least one additional conductive via having a first end extending to the common source region and a second end connected to a corresponding contact pad.

According to the 3D memory device of this embodiment, a groove is formed on the surface of at least one of the CMOS circuit and the memory cell array, thereby providing a heat dissipation path. A large amount of heat is generated during the operation of the CMOS circuit and during the operation of the memory cell array. Since the opposite surfaces of the CMOS circuit and the memory cell array are bonded to each other, heat is concentrated near the bonding surface and released via the heat dissipation path. The heat release can keep the working temperature of the 3D memory device to meet the requirements, so that data writing errors can not occur when the 3D memory device writes data by utilizing the tunneling principle, and the device damage caused by the too high temperature is avoided. Therefore, the 3D memory device according to the embodiment improves yield and reliability.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

Fig. 1a and 1b show an equivalent circuit diagram and a schematic structure diagram of a memory cell string of a 3D memory device, respectively.

Fig. 2a and 2b are a perspective view and an overall perspective view, respectively, showing an internal structure of a 3D memory device according to a first embodiment of the present invention.

Fig. 3 illustrates a cross-sectional view of a 3D memory device according to a first embodiment of the present invention.

Fig. 4 respectively illustrates a cross-sectional view of a 3D memory device according to a second embodiment of the present invention.

Fig. 5 respectively show cross-sectional views of a 3D memory device according to a third embodiment of the present invention.

Fig. 6a to 6g show cross-sectional views of stages of a method of manufacturing a 3D memory device according to a first embodiment of the invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown. The semiconductor structure obtained after several steps may be depicted in one figure for simplicity.

It will be understood that when a layer, an area, or a structure of a device is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or further layers or areas can be included between the other layer, another area, etc. And if the device is flipped, the one layer, one region, will be "under" or "beneath" the other layer, another region.

If, for the purposes of describing a situation directly overlying another layer, another region, the expression "directly overlying … …" or "overlying … … and adjoining" will be used herein.

In this application, the term "semiconductor structure" refers to a generic term for the entire semiconductor structure formed in the various steps of fabricating a memory device, including all layers or regions that have been formed. Numerous specific details of the invention, such as device structures, materials, dimensions, processing techniques and technologies, are set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

In a 3D memory device of a NAND structure, a CMOS circuit is formed using a semiconductor substrate, a memory cell array is formed using a stacked structure that provides a selection transistor and a gate conductor of the memory transistor, and then the CMOS circuit and the memory cell array are bonded to each other. Both the CMOS circuitry and the memory cell array include wiring layers in which a large number of metal wirings are employed to provide electrical connections between the CMOS circuitry and the memory cell array.

The inventors of the present application have found that a significant amount of heat is generated during operation of the CMOS circuit as well as during operation of the memory cell array. Since the opposite surfaces of the CMOS circuit and the memory cell array are bonded to each other, a large number of wirings of the CMOS circuit and the memory cell array are located near the bonding surfaces, so that heat is concentrated there and cannot be released. This heat build up results in excessive temperatures of the 3D memory device. The 3D memory device writes data using a tunneling principle, and thus, the 3D memory device is sensitive to an ambient temperature, and an excessively high temperature may cause a write data error. In more severe cases, excessive temperatures may cause electrical disconnection between the CMOS circuitry and the memory cell array, resulting in device damage. The existing 3D memory device has no heat dissipation path between the CMOS circuit and the memory cell array, thereby affecting the yield and reliability of the 3D memory device.

The inventors of the present application have noted the above-described problem affecting the yield and reliability of the 3D memory device, and thus have proposed a further improved 3D memory device and a method of manufacturing the same.

The invention may be embodied in various forms, some examples of which are described below.

Fig. 1a and 1b show a circuit diagram and a schematic diagram of a memory cell string of a 3D memory device, respectively. The memory cell string shown in this embodiment includes a case of 4 memory cells. It is to be understood that the present invention is not limited thereto, and the number of memory cells in the memory cell string may be any number, for example, 32 or 64.

As shown in fig. 1a, the memory cell string 100 has a first terminal connected to the bit line BL and a second terminal connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between a first terminal and a second terminal, including: a first selection transistor Q1, memory transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the memory transistors M1 to M4 are connected to the corresponding word lines of the word lines WL1 to WL4, respectively.

As shown in fig. 1b, the first and second select transistors Q1 and Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel pillar 110. The channel pillar 110 penetrates the gate stack structure. In the middle portion of the channel pillar 110, a tunneling dielectric layer 112, a charge storage layer 113, and a blocking dielectric layer 114 are sandwiched between a gate conductor 121 and a channel layer 111, thereby forming memory transistors M1 to M4. A blocking dielectric layer 114 is interposed between the gate conductors 122 and 123 and the channel layer 111 at both ends of the channel pillar 110, thereby forming a first selection transistor Q1 and a second selection transistor Q2.

In this embodiment, the channel layer 111 is composed of, for example, doped polysilicon, the tunneling dielectric layer 112 and the blocking dielectric layer 114 are each composed of an oxide, for example, silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, for example, silicon nitride containing microparticles of a metal or semiconductor, and the gate conductors 121, 122, and 123 are composed of a metal, for example, tungsten. The channel layer 111 is used to provide channel regions for controlling the select and memory transistors, and the doping type of the channel layer 111 is the same as the type of the select and memory transistors. For example, for an N-type select transistor and a memory transistor, the channel layer 111 may be N-type doped polysilicon.

In this embodiment, the core of the channel pillar 110 is the channel layer 111, and the tunneling dielectric layer 112, the charge storage layer 113, and the blocking dielectric layer 114 form a stacked structure around the core sidewall. In an alternative embodiment, the core of channel pillar 110 is an additional insulating layer, and channel layer 111, tunneling dielectric layer 112, charge storage layer 113, and blocking dielectric layer 114 form a stacked structure around the core.

In this embodiment, the first and second selection transistors Q1 and Q2 and the memory transistors M1 to M4 use a common channel layer 111 and blocking dielectric layer 114. In the channel pillar 110, a channel layer 111 provides source and drain regions and channel layers of a plurality of transistors. In alternative embodiments, the semiconductor layers and the blocking dielectric layers of the first and second selection transistors Q1 and Q2 and the semiconductor layers and the blocking dielectric layers of the memory transistors M1 to M4 may be formed separately from each other.

In the write operation, the memory cell string 100 writes data to a selected one of the memory transistors M1 to M4 using FN tunneling efficiency. Taking the memory transistor M2 as an example, the ground selection line GSL is biased to about zero volt while the source line SL is grounded, so that the selection transistor Q2 corresponding to the ground selection line GSL is turned off, and the string selection line SSL is biased to the high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, BIT line BIT2 is grounded, word line WL2 is biased at a programming voltage VPG, e.g., around 20V, and the remaining word lines are biased at a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting data into charges to be stored in the charge storage layer 113 of the memory transistor M2.

In the read operation, the memory cell string 100 judges the amount of charge in the charge storage layer according to the on state of a selected one of the memory transistors M1 to M4, thereby obtaining data representing the amount of charge. Taking memory transistor M2 as an example, word line WL2 is biased at read voltage VRD and the remaining word lines are biased at high voltage VPS2. The on state of the memory transistor M2 is related to its threshold voltage, i.e. to the amount of charge in the charge storage layer, so that the data value can be determined from the on state of the memory transistor M2. The memory transistors M1, M3, and M4 are always in the on state, and thus, the on state of the memory cell string 100 depends on the on state of the memory transistor M2. The control circuit judges the on state of the memory transistor M2 from the electric signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

Fig. 2a and 2b are a perspective view and an overall perspective view, respectively, showing an internal structure of a 3D memory device according to a first embodiment of the present invention, and fig. 3 is a cross-sectional view showing the 3D memory device according to the first embodiment of the present invention.

For clarity, only the internal structure of the 3D memory device is shown in fig. 2a, where the semiconductor substrate of the memory cell array, and the CMOS circuitry and insulation layers in the memory cell array are not shown, and only the external structure of the 3D memory is shown in fig. 2 b.

The 3D memory device 200 shown in this embodiment includes a stacked CMOS circuit 210 and memory cell array 220.

The CMOS circuit 210 includes a semiconductor substrate 201, a plurality of contact pads 261 on the semiconductor substrate 201, a plurality of wiring layers 263 on the plurality of contact pads 261, a plurality of external pads 264 on the plurality of wiring layers 263, and conductive vias 262 providing interconnection in a direction perpendicular to the surface of the semiconductor substrate 201. Although not shown, it is understood that a plurality of transistors are formed in the semiconductor substrate 201. The plurality of wiring layers 263 are spaced apart from each other and the plurality of wiring layers 263 and the contact pad 261 and the external pad 264 with an interlayer insulating layer therebetween, and are electrically connected to each other with a conductive via 262 penetrating the interlayer insulating layer. The interlayer insulating layer is not shown in fig. 2 a.

In the CMOS circuit 210, a contact pad 261 is electrically connected with a transistor in the semiconductor substrate 201, the contact pad 261 is connected to a wiring layer 263 via a conductive path 262, and then the wiring layer 263 is connected from an external pad 264 via the conductive path 262. The external pads 264 provide electrical connections between transistors within the CMOS circuit 210 and the memory cell array 220.

The memory cell array 220 includes a total of 12 memory cell strings 4*3, each including 4 memory cells, thereby forming a total of 48 memory cells of 4×4×3. It is to be understood that the present invention is not limited thereto, and the 3D memory device may include any number of memory cell strings, for example 1024, and the number of memory cells in each memory cell string may be any number, for example 32 or 64.

The memory cell array 220 includes a semiconductor substrate 101, a gate stack structure on the semiconductor substrate 101, channel pillars 110 penetrating the gate stack structure, and an interconnect structure on the gate stack structure. The interconnect structure includes a plurality of conductive vias 161, a plurality of contact pads 162 respectively contacting the plurality of conductive vias 161, a plurality of wiring layers 164 on the plurality of contact pads 162, a plurality of external pads 165 on the plurality of wiring layers 164, and conductive vias 163 providing interconnection in a direction perpendicular to the surface of the semiconductor substrate 101. The gate stack structure includes, for example, gate conductors 121, 122, and 123. The plurality of gate conductors in the gate stack structure are, for example, stepped to provide space for conductive channels 161 to extend to the corresponding gate conductors.

In memory cell array 220, the memory cell strings include respective channel pillars 110, and common gate conductors 121, 122, and 123, respectively. The gate conductors 121, 122, and 123 are aligned with the stacking order of transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. The interlayer insulating layer is not shown in fig. 2 a.

In this embodiment, the internal structure of the channel pillar 110 is shown in fig. 1b, and will not be described in detail herein. The channel pillars 110 extend through the gate stack structure and are arranged in an array. A semiconductor substrate is positioned over the gate stack structure, wherein a common source region (not shown) is formed. First ends of the channel pillars 110 are commonly connected to a common source region, and second ends of the channel pillars 110 are connected to respective external pads 165 via conductive paths and wirings. The conductive path and the wiring layer here function the same as the bit line BL.

The gate conductor 122 of the first selection transistor Q1 is divided into different gate lines by a gate line slit (gate line slit) 151. The gate lines of the plurality of channel pillars 110 of the same row are connected to the corresponding external pads 165 via conductive paths and wirings, respectively. For clarity, a portion of the conductive path and wiring layer between gate conductor 122 and the contact pad is not shown in the figures. The conductive path and wiring layer here function the same as the string select line SSL.

The gate conductors 121 of the memory transistors M1 and M4 are connected to the corresponding word lines, respectively. If the gate conductors 121 of the memory transistors M1 and M4 are divided into different gate lines by the gate line slit 151, the gate lines of the same level are connected to the corresponding external pads 165 via conductive paths and wirings, respectively. For clarity, a portion of the conductive path and wiring layer between the gate conductor 121 and the contact pad is not shown in the figures. The conductive paths and wiring layers here function the same as the word lines WL1 to WL 4.

The gate conductors of the second selection transistors Q2 are connected in one piece. If the gate conductor 123 of the second selection transistor Q2 is divided into different gate lines by the gate line slit 151, the gate lines are connected to the corresponding external pads 165 via conductive paths and wirings, respectively. The conductive path and the wiring layer here function as the ground selection line GSL.

Preferably, a dummy channel pillar 130 may also be included in this embodiment, and the internal structure of the dummy channel pillar 130 and the channel pillar 110 may be identical and pass through at least a portion of the gate conductor in the gate stack structure. However, the dummy channel columns 130 are not connected to the external pads 165, thereby providing only mechanical support, and are not used to form select transistors and memory transistors. Thus, the dummy channel pillars 130 do not form an effective memory cell.

Preferably, in this embodiment, a conductive via 141 and an insulating liner 142 are further included, and the conductive via 141 passes through the gate stack structure and is insulated from the gate stack structure by the insulating liner 142. The conductive via 141 extends into the semiconductor substrate above the gate stack at a first end to the common source region and at a second end to the wiring layer. The conductive path and the wiring layer here function as the source line GL.

After the CMOS circuit 210 and the memory cell array 220 are formed, they are bonded to each other to form the 3D memory device 200. The surfaces of the CMOS circuit 210 and the memory cell array 220 that face each other are the respective bonding surfaces. The large number of wirings of the CMOS circuit 210 and the memory cell array 220 are located near the respective bonding surfaces.

Referring to fig. 2b, according to the 3D memory device 200 of this embodiment, conductive channels and wiring layers of the cmos circuit 210 are located in at least one insulating layer 202, and conductive channels and wiring layers of the memory cell array 220 are located in at least one insulating layer 102. The bonding surfaces of the CMOS circuit 210 and the memory cell array 220 are surfaces of the insulating layers 202 and 102, respectively, opposite to each other. Further, the external pads 264 of the CMOS circuit 210 and the external pads 165 of the memory cell array 220 are respectively exposed on the corresponding bonding surfaces and disposed opposite to each other. Accordingly, when the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the 3D memory device 200, the external pad 264 of the CMOS circuit 210 and the external pad 165 of the memory cell array 220 are in contact with each other, thereby achieving electrical connection between the CMOS circuit 210 and the memory cell array 220.

Further, according to the 3D memory device 200 of this embodiment, grooves 203 and 103 are formed on the bonding surface of at least one of the CMOS circuit 210 and the memory cell array 220. The grooves 203 and 103 extend laterally over the bonding surfaces of the CMOS circuit 210 and the memory cell array 220, for example, having a substantially rectangular or trapezoidal cross-sectional shape. In the 3D memory device 200 formed by bonding the CMOS circuit 210 and the memory cell array 220 to each other, the grooves 203 and 103 communicate with the external environment, thereby providing a heat dissipation path between the CMOS circuit and the memory cell array.

Preferably, grooves 203 and 103 are formed on bonding surfaces of the CMOS circuit 210 and the memory cell array 220, respectively, and are disposed opposite to each other. Accordingly, when the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the 3D memory device 200, the grooves 203 of the CMOS circuit 210 and the grooves 103 of the memory cell array 220 are connected to each other to form a cavity communicating with the external environment, thereby providing a heat dissipation path between the CMOS circuit and the memory cell array.

The 3D memory device 300 shown in this embodiment includes a stacked CMOS circuit 210 and memory cell array 220. Only the differences between the second embodiment and the first embodiment are described in detail below.

Grooves 323 and 313 are formed on bonding surfaces of the CMOS circuit 210 and the memory cell array 220, respectively, and are disposed opposite to each other. The grooves 323 and 313 extend laterally on the bonding surfaces of the CMOS circuit 210 and the memory cell array 220, and further extend to the wiring layers 263 and 164 in a direction perpendicular to the bonding surfaces, for example, having an irregular cross-sectional shape. In the 3D memory device 200 formed by bonding the CMOS circuit 210 and the memory cell array 220 to each other, the grooves 323 and 313 communicate with the external environment, thereby providing a heat dissipation path between the CMOS circuit and the memory cell array.

According to the 3D memory device of this embodiment, the recess extending to the wiring layer is formed on the surface of at least one of the CMOS circuit and the memory cell array, thereby providing the heat dissipation path. A large amount of heat is generated during the operation of the CMOS circuit and during the operation of the memory cell array. Since the opposite surfaces of the CMOS circuit and the memory cell array are bonded to each other, heat is concentrated near the bonding surface and released via the heat dissipation path. The heat release can keep the working temperature of the 3D memory device to meet the requirements, so that data writing errors can not occur when the 3D memory device writes data by utilizing the tunneling principle, and the device damage caused by the too high temperature is avoided. Therefore, the 3D memory device according to the embodiment improves yield and reliability.

The 3D memory device 400 shown in this embodiment includes a stacked CMOS circuit 210 and memory cell array 220. Only the differences between the third embodiment and the first embodiment are described in detail below.

Grooves are formed on bonding surfaces of the CMOS circuit 210 and the memory cell array 220, respectively, and are disposed opposite to each other, and the grooves are filled with heat conductive materials 423 and 413, such as copper, silver, and heat conductive silicon. Thermally conductive materials 423 and 413 extend laterally over the bonding surfaces of CMOS circuit 210 and memory cell array 220, preferably via electrically conductive channels, to wiring layers 263 and 164. In the 3D memory device 200 formed by bonding the CMOS circuit 210 and the memory cell array 220 to each other, the heat conductive materials 423 and 413 are integrally formed in contact with each other and communicate with the external environment, thereby providing a heat dissipation path between the CMOS circuit and the memory cell array.

According to the 3D memory device of this embodiment, a groove is formed on the surface of at least one of the CMOS circuit and the memory cell array, and a heat conductive material is filled in the groove, preferably, via an electrically conductive path to the wiring layer, thereby providing a heat dissipation path. A large amount of heat is generated during the operation of the CMOS circuit and during the operation of the memory cell array. Since the opposite surfaces of the CMOS circuit and the memory cell array are bonded to each other, heat is concentrated near the bonding surface and released via the heat dissipation path. The heat release can keep the working temperature of the 3D memory device to meet the requirements, so that data writing errors can not occur when the 3D memory device writes data by utilizing the tunneling principle, and the device damage caused by the too high temperature is avoided. Therefore, the 3D memory device according to the embodiment improves yield and reliability.

Fig. 6a to 6g show cross-sectional views of various stages of a method of manufacturing a 3D memory device according to a first embodiment of the present invention, wherein fig. 6a to 6D show manufacturing steps of a memory cell array, fig. 6e and 6f show manufacturing steps of a CMOS circuit, and fig. 6g shows bonding of a CMOS to a memory cell array. The cross-sectional view is taken along line AA in fig. 2 a.

The method starts with a semiconductor structure in which a plurality of well regions have been formed on a semiconductor substrate 101, in this embodiment the semiconductor substrate 101 is for example a monocrystalline silicon substrate.

In this embodiment, in order to facilitate a programming operation for memory cells in a 3D memory device, a plurality of well regions are formed in the semiconductor substrate 101. For example, the semiconductor substrate 101 includes a common source region of a plurality of channel pillars.

As shown in fig. 6a, an insulating stack structure is formed on a semiconductor substrate 101.

The insulating stack structure includes a plurality of sacrificial layers 152 stacked, adjacent sacrificial layers 152 being separated from each other by insulating layers 102. In this embodiment, the insulating layer 102 is composed of, for example, silicon oxide, and the sacrificial layer 152 is composed of, for example, silicon nitride.

As described below, the sacrificial layer 152 will be replaced with gate conductors 121 to 123, the gate conductor 121 being connected to the string select line in one step, the gate conductor 123 being connected to the ground select line in one step, and the gate conductor 122 being connected to the word line in one step. To form a conductive path from the gate conductors 121 to 123 to the word line, the plurality of sacrificial layers 152 are, for example, patterned in a step shape, i.e., an edge portion of each sacrificial layer 152 is exposed with respect to an overlying sacrificial layer to provide an electrical connection region. After the patterning step of the plurality of sacrificial layers 152, an insulating layer may be used to cover the insulating stack structure. The interlayer insulating layer between the plurality of sacrificial layers 152 and the interlayer insulating layer covering the insulating stack structure are shown as a whole as insulating layer 102 in fig. 6 a. However, the present invention is not limited thereto, and a plurality of interlayer insulating layers between and over the plurality of sacrificial layers 152 may be formed using a plurality of independent deposition steps.

Further, a channel hole is formed in the insulating stack structure. In this embodiment, for example, a photoresist mask is formed on the surface of the semiconductor structure, and then anisotropic etching is performed to form a channel hole in the insulating stack structure. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, the etching is stopped near the lower side of the common source region, and the etching is stopped near the lower side of the first insulating region. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

Further, a channel pillar 110 is formed in the channel hole. The lower portion of the channel pillar 110 includes a semiconductor layer. Further, the channel pillar 110 includes a channel layer extending from an upper portion thereof to the semiconductor layer. For clarity, the internal structure of channel post 110 is not shown in fig. 6 a. Referring to fig. 1b, in the middle portion of the channel pillar 110, the channel pillar 110 includes a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer sequentially stacked on the channel layer, and at both ends of the channel pillar 110, the channel pillar 110 includes a blocking dielectric layer stacked on the channel layer or the semiconductor layer. The lower end of the channel pillar 110 contacts a common source region in the semiconductor substrate 101. In the final 3D memory device, the upper ends of the channel pillars 110 will be connected to the wiring layer, thereby forming an effective memory cell. The channel pillar 110 has a structure such as ONOP (oxide-nitride-oxide-polysilicon).

Preferably, dummy channel pillars 130 are formed in the channel holes. The dummy channel column 130 may be the same internal structure as the channel column 110 and passes through at least a portion of the gate conductor in the gate stack structure. However, in the final 3D memory device, the upper ends of the dummy channel columns 130 are not connected to the wiring layer, thereby providing only mechanical support, and are not used to form the select transistors and the memory transistors.

Preferably, a through hole is formed in the insulating laminate structure, and the conductive via 141 and the insulating liner 142 are formed in the through hole. The conductive vias 141 pass through the insulating laminate structure and are separated from the insulating laminate structure by insulating liners 142. One end of the conductive via 141 extends into the semiconductor substrate 101 under the insulating stack structure to the common source region, and the other end will be connected to the wiring layer.

As shown in fig. 6b, in the insulating stack structure, the sacrificial layer 152 is replaced with the gate conductors 121 to 123, forming a gate stack structure.

In this step, a gate line slit 151 (see fig. 2 a) is formed in the insulating stack structure, the insulating layer 102 is used as an etch stop layer, the sacrificial layer 152 is removed by etching through the gate line slit 151 to form a cavity, and the cavity is filled with a metal layer to form gate conductors 121 to 123, wherein a plurality of gate conductors 121 to 123 and the insulating layer 102 are alternately stacked. Accordingly, a plurality of channel pillars 110 extend through the gate stack structure.

In forming the gate line slit 151, anisotropic etching, for example, dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation may be employed. For example, by controlling the etching time, etching is stopped near the surface of the semiconductor substrate 101. In this embodiment, the gate line slit 151 divides the gate conductors 121 to 123 into a plurality of gate lines.

In forming the cavity, the sacrificial layer 152 in the insulating stack structure is removed by isotropic etching using the gate line slit 151 as an etchant passage to form the cavity. The isotropic etching may employ selective wet etching or vapor etching. An etching solution is used as an etchant in wet etching, wherein the semiconductor structure is immersed in the etching solution. An etching gas is used as an etchant in a gas phase etching, wherein the semiconductor structure is exposed to the etching gas.

In the case where the insulating layer 102 and the sacrificial layer 152 in the insulating stack structure are composed of silicon oxide and silicon nitride, respectively, a phosphoric acid solution may be used as an etchant in wet etching, and one or more of C4F8, C4F6, CH2F2, and O2 may be used in vapor etching. In the etching step, the gate line slit 151 is filled with an etchant. The end of the sacrificial layer 152 in the insulating stack structure is exposed in the opening of the gate line slit 151, and thus, the sacrificial layer 152 is contacted to the etchant. The etchant gradually etches the sacrificial layer 152 from the opening of the gate line slit 151 toward the inside of the insulating stack structure. Due to the selectivity of the etchant, the etching removes the sacrificial layer 152 with respect to the insulating layer 102 in the insulating stack structure.

In forming the gate conductors 121 to 123, atomic Layer Deposition (ALD) is used using the gate line slit 151 as a deposition path, and a metal layer is filled in the gate line slit 151 and the cavity.

In this embodiment, the metal layer is composed of tungsten, for example. The precursor source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, and the reducing gas used is, for example, silane SiH4 or diborane B2H6. In the step of atomic layer deposition, a deposition process is performed by obtaining a tungsten material by chemisorption of a reaction product of tungsten hexafluoride WF6 and silane SiH 4.

As shown in fig. 6c, an interconnect structure is formed over the gate stack structure.

The interconnect structure includes a plurality of conductive vias 161 located above the gate stack structure, a plurality of contact pads 162 respectively contacting the plurality of conductive vias 161, a plurality of wiring layers 164 located on the plurality of contact pads 162, a plurality of external pads 165 located on the plurality of wiring layers 164, and conductive vias 163 providing interconnection in a direction perpendicular to the surface of the semiconductor substrate 101.

The semiconductor structure formed at this step is a memory cell array 220 in which the gate stack structure forms a select transistor and a memory transistor together with the channel pillar. In the middle portion of the channel pillar 110, the gate conductors 121 to 123 form a memory transistor together with a channel layer, a tunneling dielectric layer, a charge storage layer, and a blocking dielectric layer inside the channel pillar 110. At both ends of the channel pillar 110, gate conductors 121 to 123 form a selection transistor together with a channel layer (or semiconductor layer) and a blocking dielectric layer inside the channel pillar 110.

The gate conductors 121, 122 and 123 in the gate stack structure are, for example, stepped to provide spaces for the conductive channels 161 to extend to the corresponding gate conductors. Conductive vias and wiring layers of the memory cell array 220 are located in at least one insulating layer 102. As described above, the insulating layer 102 is shown as a single layer in the drawing, however, the insulating layer 102 may actually be composed of a plurality of interlayer insulating layers including a plurality of interlayer insulating layers for separating the gate conductors 121, 122, and 123 and a plurality of interlayer insulating layers for separating different wiring layers. In addition, the contact pad 162 and the external pad 165 may also be located on separate interlayer insulating layers.

Further, first ends of the channel pillars 110 are commonly connected to a common source region in the semiconductor substrate 101, and second ends of the channel pillars 110 are connected to contact pads 162 via conductive vias 161, and then to corresponding external pads 165 via conductive vias and wiring. The first ends of the conductive vias 141 extend to a common source region in the semiconductor substrate 101 and the second ends are connected to contact pads 162 via conductive vias 161 and then to corresponding external pads 165 via conductive vias and wiring.

The bonding surface of the memory cell array 220 is the first surface of the insulating layer 102. In this step, the first surface is an exposed free surface. The contact surface of the external pad 165 is exposed on the first surface.

As shown in fig. 6d, a groove 103 is formed on the surface of the insulating layer 102 of the memory cell array 220.

On the first surface of the insulating layer 102, for example, the grooves 103 are located in the region between the external pads 165. Preferably, the groove 103 extends in a length direction or a width direction of the first surface of the insulating layer 102, from one side wall to the other side wall of the insulating layer 102, so as to extend laterally through the insulating layer 102.

In this step, for example, a photoresist mask is formed on the first surface of the insulating layer 102, and then anisotropic etching is performed to form a groove 103 in the insulating layer 102. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped at a distance inside the surface of the insulating layer 102. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

As shown in fig. 6e, transistors (not shown) of a CMOS circuit are formed in the semiconductor substrate 201, and an interconnect structure is formed on the semiconductor substrate 201.

In this embodiment, the semiconductor substrate 201 is, for example, a single crystal silicon substrate. To form a transistor, a plurality of doped regions are formed in the semiconductor substrate 201. For example, the semiconductor substrate 201 includes source and drain regions of a plurality of transistors.

The semiconductor structure formed at this step is a CMOS circuit 210 in which the doped regions of the plurality of transistors formed in the semiconductor substrate 201 provide external electrical connections via the interconnect structure.

The interconnect structure includes a plurality of contact pads 261 on the semiconductor substrate 201, a plurality of wiring layers 263 on the plurality of contact pads 261, a plurality of external pads 264 on the plurality of wiring layers 263, and conductive vias 262 providing interconnection in a direction perpendicular to the surface of the semiconductor substrate 201. The plurality of wiring layers 260 are spaced apart from each other and the plurality of wiring layers 260 and the contact pad 261 and the external pad 264 by the insulating layer 202 and are electrically connected to each other by the conductive via 262 in the insulating layer 202.

As shown in fig. 6f, a groove 203 is formed on the surface of the insulating layer 202 of the CMOS circuit 210.

On the first surface of the insulating layer 202, for example, the grooves 203 are located in the region between the external pads 264. Preferably, the groove 203 extends in a length direction or a width direction of the first surface of the insulating layer 202, from one side wall to the other side wall of the insulating layer 202, so as to extend laterally through the insulating layer 202.

In this step, for example, a photoresist mask is formed on the first surface of the insulating layer 202, and then anisotropic etching is performed, forming a groove 203 in the insulating layer 202. The anisotropic etching may be dry etching such as ion milling etching, plasma etching, reactive ion etching, laser ablation. For example, by controlling the etching time, etching is stopped at a distance inside the surface of the insulating layer 202. The photoresist mask is removed after etching by dissolution in a solvent or ashing.

As shown in fig. 6g, the CMOS circuit 210 and the memory cell array 220 are bonded to each other into a 3D memory device 200.

When the CMOS circuit 210 and the memory cell array 220 are bonded to each other into the 3D memory device 200, the external pad 264 of the CMOS circuit 210 and the external pad 165 of the memory cell array 220 are in contact with each other, thereby achieving electrical connection between the CMOS circuit 210 and the memory cell array 220.

Grooves 203 and 103 are formed on the bonding surface of at least one of the CMOS circuit 210 and the memory cell array 220. The grooves 203 and 103 extend laterally over the bonding surfaces of the CMOS circuit 210 and the memory cell array 220, for example, having a substantially rectangular or trapezoidal cross-sectional shape. In the 3D memory device 200 formed by bonding the CMOS circuit 210 and the memory cell array 220 to each other, the grooves 203 and 103 communicate with the external environment, thereby providing a heat dissipation path between the CMOS circuit and the memory cell array.

In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.

The embodiments of the present invention are described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the invention, and such alternatives and modifications are intended to fall within the scope of the invention.

Claims

1. A 3D memory device, comprising:

a CMOS circuit including a first bonding surface and a first external pad exposed on the first bonding surface; and

a memory cell array including a second bonding surface, and a second external pad exposed on the second bonding surface,

wherein a first bonding surface of the CMOS circuit and a second bonding surface of the memory cell array are in contact with each other, the first external pad and the second external pad are bonded to each other, thereby achieving electrical connection between the CMOS circuit and the memory cell array,

the CMOS circuit further comprises a plurality of first grooves etched on the first bonding surface, the memory cell array further comprises a plurality of second grooves etched on the second bonding surface, the plurality of first grooves and the plurality of second grooves form heat dissipation channels,

The CMOS circuit and the memory cell array each include a respective plurality of wiring layers extending laterally, the plurality of first recesses extending inwardly from a first bonding face of the CMOS circuit to the wiring layers of the CMOS circuit, and the plurality of second recesses extending inwardly from a second bonding face of the memory cell array to the wiring layers of the memory cell array.

2. The 3D memory device of claim 1, wherein the first plurality of grooves extend laterally across the first bonding surface from a first sidewall to a second sidewall of the CMOS circuit, wherein the second plurality of grooves extend laterally across the second bonding surface from the first sidewall to the second sidewall of the array of memory cells,

the first groove and the second groove are communicated with the external environment.

3. The 3D memory device of claim 2, wherein the first plurality of grooves and the second plurality of grooves are connected to each other to form an integral cavity.

4. The 3D memory device of claim 2, wherein the CMOS circuitry and the memory cell array each include a respective plurality of conductive vias for providing electrical connection of the plurality of wiring layers to each other.

5. The 3D memory device of claim 2, wherein the first plurality of grooves and the second plurality of grooves are filled with a thermally conductive material.

6. The 3D memory device of claim 4, wherein the CMOS circuit further comprises:

a semiconductor substrate;

a plurality of transistors located in the semiconductor substrate;

a plurality of contact pads on the semiconductor substrate and connected to the plurality of transistors; and

an insulating layer on the semiconductor substrate,

wherein the plurality of wiring layers and the plurality of conductive vias are located in the insulating layer, the first external pad is located on the insulating layer, the first bonding surface is a free surface of the insulating layer,

the plurality of contact pads are connected to respective first external pads via the plurality of wiring layers and the plurality of conductive vias.

7. The 3D memory device of claim 4, wherein the memory cell array further comprises:

a semiconductor substrate;

a common source region located in the semiconductor substrate;

a gate stack structure on the semiconductor substrate, the gate stack structure comprising a plurality of levels of gate conductors;

A plurality of channel pillars extending through the gate stack;

a plurality of contact pads on the gate stack; and

an insulating layer on the gate stack,

wherein first ends of the plurality of channel pillars extend to the common source region, second ends are connected to respective contact pads,

the gate conductors of the plurality of layers are each connected to a corresponding contact pad,

the plurality of wiring layers and the plurality of conductive vias are located in the insulating layer, the second external pad is located on the insulating layer, the second bonding surface is a free surface of the insulating layer,

the plurality of contact pads are connected to respective second external pads via the plurality of wiring layers and the plurality of conductive vias.

8. The 3D memory device of claim 7, wherein the plurality of channel pillars and the plurality of levels of gate conductors form a memory transistor and a select transistor.

9. The 3D memory device of claim 7, wherein the memory cell array further comprises: and the plurality of dummy channel columns penetrate through the gate stack structure, and are not connected with the contact welding disc.

10. The 3D memory device of claim 7, wherein the memory cell array further comprises: at least one additional conductive via extending through the gate stack structure, the at least one additional conductive via having a first end extending to the common source region and a second end connected to a corresponding contact pad.