CN108878526B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

Info

Publication number
CN108878526B
CN108878526B CN201710328760.9A CN201710328760A CN108878526B CN 108878526 B CN108878526 B CN 108878526B CN 201710328760 A CN201710328760 A CN 201710328760A CN 108878526 B CN108878526 B CN 108878526B
Authority
CN
China
Prior art keywords
layer
ions
punch
diffusion
fin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201710328760.9A
Other languages
Chinese (zh)
Other versions
CN108878526A (en
Inventor
周飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201710328760.9A priority Critical patent/CN108878526B/en
Publication of CN108878526A publication Critical patent/CN108878526A/en
Application granted granted Critical
Publication of CN108878526B publication Critical patent/CN108878526B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate, wherein fin parts are arranged on the substrate, and fin part gaps are formed between adjacent fin parts; setting a hard mask above the fin portion; forming a punch-through prevention layer above the hard mask, wherein punch-through prevention ions are arranged in the punch-through prevention layer; forming an anti-diffusion layer, wherein the height of the anti-diffusion layer is lower than that of the fin part, and anti-diffusion ions are injected into the gap of the fin part and can prevent the anti-punch-through ions from diffusing to the top of the fin part; removing the hard mask; and annealing is carried out.

Description

Semiconductor structure and forming method thereof
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the devices. However, as the size of the transistor is sharply reduced, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A FinFET channel protrudes out of the surface of a substrate to form a fin part, and a grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the multi-side control circuit of the fin part can be switched on and switched off. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. One approach is to reduce the possibility of drain-source punch-through and reduce the short channel effect by performing a punch-through prevention implant into the bottom of the fin.
However, the method of forming the semiconductor structure is susceptible to affecting the performance of the formed semiconductor structure.
Disclosure of Invention
The invention provides a semiconductor and a forming method thereof, which can improve the performance of a semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein fin parts are arranged on the substrate, and fin part gaps are formed between adjacent fin parts; setting a hard mask above the fin portion; forming a punch-through prevention layer above the hard mask, wherein punch-through prevention ions are arranged in the punch-through prevention layer; forming an anti-diffusion layer, wherein the height of the anti-diffusion layer is lower than that of the fin part, and anti-diffusion ions are injected into the gap of the fin part and can prevent the anti-punch-through ions from diffusing to the top of the fin part; removing the hard mask; and annealing is carried out.
Optionally, the annealing temperature is greater than or equal to 850 ℃.
Optionally, the ions implanted into the diffusion preventing layer are one or more of carbon ions, germanium ions and nitrogen ions.
Optionally, a protective layer is formed above the punch-through prevention layer, and the protective layer prevents the punch-through prevention ions from diffusing upward.
Optionally, the material of the protective layer is one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN.
Optionally, the penetration preventing layer covers the fin gap.
Optionally, forming the diffusion preventing layer comprises: forming an initial anti-diffusion layer, wherein the initial anti-diffusion layer covers the whole fin part and is formed by adopting a fluid chemical vapor deposition process; carrying out a first annealing process on the initial anti-diffusion layer, wherein the temperature of the first annealing process is 400-650 ℃; carrying out thermal ion implantation on the initial anti-diffusion layer, wherein the temperature of the thermal ion implantation process is 450-500 ℃; and etching the initial anti-diffusion layer to enable the height of the initial anti-diffusion layer to be lower than that of the fin portion, and forming the anti-diffusion layer.
Optionally, after the thermal ion implantation is performed, a second annealing process is performed on the initial anti-diffusion layer, where the temperature of the second annealing process is 500 ℃ to 700 ℃.
Optionally, in the thermal ion implantation process, the implanted ions are He.
Optionally, the energy of the hot ion implantation is 1-50Kev, and the implantation dose is 1.0e14-1.0e19atm/cm2。
Optionally, after the anti-diffusion layer is formed, the penetration preventing layer and the protective layer are etched, so that the heights of the penetration preventing layer and the protective layer are flush with the anti-diffusion layer.
Optionally, after the hard mask is disposed, an oxide layer is covered over the hard mask, and the oxide layer is removed before the anti-punch-through layer is formed.
Optionally, the substrate includes a first transistor region and a second transistor region, and the punch-through ion doping type is opposite to the transistor doping type of the corresponding region.
Optionally, the first transistor region is an NMOS transistor, and the punch-through ion doping type in the first transistor region is a P type.
Optionally, the anti-punch through layer is formed only in the first transistor region.
Optionally, the ions of the anti-punch-through layer in the first transistor area are boron ions or boron fluoride ions.
The invention also includes a semiconductor structure formed using any of the above methods.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor forming method, the anti-punch-through layer is formed, so that punch-through between a source region and a drain region can be prevented or reduced, and leakage current is reduced;
furthermore, a diffusion-preventing layer and a protective layer are arranged beside the punch-through-preventing layer, the protective layer can prevent punch-through ions from diffusing to the outside, and the diffusion-preventing layer can reduce the punch-through-preventing ions diffused into a channel of the transistor.
Furthermore, the diffusion-preventing ions are formed in the diffusion-preventing layers in the gaps between the adjacent fin portions, so that the process operation is more convenient, and the ions in the penetration-preventing layers are effectively prevented from diffusing to the tops of the fin portions.
Furthermore, the diffusion-proof layer is prepared by adopting a three-step process, and the thermal ion implantation process is introduced by combining the annealing process, the thermal ion implantation process and other processes, so that the densification temperature of the FCVD oxide is reduced, and the quality of the formed diffusion layer is higher.
Drawings
Fig. 1-3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Fig. 4-13 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
FIG. 14 is a schematic diagram of a semiconductor structure formation step of the present invention.
Detailed Description
The wafer test structure of the present invention will be described in more detail in conjunction with the schematic drawings, in which preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the present invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The method for forming the semiconductor structure has a plurality of problems, and the formed semiconductor structure is difficult to ensure stable performance.
Research shows that as the size of a fin portion for forming a fin field effect transistor is continuously reduced, the bottoms of a source region and a drain region formed in the fin portion are prone to bottom punch-through (punch through), that is, short circuits occur between the bottoms of the source region and the drain region, and leakage currents are generated at the bottoms of the source region and the drain region. To overcome the bottom punch-through phenomenon, one approach is to implant counter ions in the region between the source and drain bottom portions to isolate the source and drain bottom portions.
Fig. 1 to 3 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, and a fin 101 and a hard mask 110 on top of the fin 101 are disposed over the substrate 100. The substrate includes: a first transistor area a and a second transistor area B.
With continued reference to fig. 1, a punch-through prevention layer 102 is formed on the substrate 100, wherein the surface of the punch-through prevention layer 102 is lower than the top surface of the fin 101.
Referring to fig. 2, the anti-punch-through layer 102 is ion implanted with anti-punch-through ions.
Referring to fig. 3, after the anti-punch through ion implantation, an annealing process is performed to diffuse the anti-punch through ions into the bottom of the fin 101.
In the annealing process, the punch-through ions are likely to diffuse toward the top of the fin 101, which may increase the threshold voltage of the subsequently formed transistor and affect the performance of the transistor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate, wherein fin parts are arranged on the substrate, and fin part gaps are formed between adjacent fin parts; setting a hard mask above the fin portion; forming a punch-through prevention layer above the hard mask, wherein punch-through prevention ions are arranged in the punch-through prevention layer; forming an anti-diffusion layer, wherein the height of the anti-diffusion layer is lower than that of the fin part, and anti-diffusion ions are injected into the gap of the fin part and can prevent the anti-punch-through ions from diffusing to the top of the fin part; removing the hard mask; and annealing is carried out.
In the method for forming the semiconductor structure, before the annealing treatment, the anti-diffusion layer is formed, anti-diffusion ions are injected into the gap between the adjacent fin parts, namely the anti-diffusion layer and the anti-punch-through layer, the anti-diffusion ions are positioned at the top parts of the anti-diffusion layer and the anti-punch-through layer, and simultaneously, due to the doping characteristics, the concentration of doping is gradually reduced from the anti-diffusion ion doping source point to the outside, so that the anti-diffusion ions are also simultaneously present in the fin parts, and the anti-diffusion ions can prevent the ions in the anti-punch-through layer from diffusing to the top parts of the fin parts, so that the anti-punch-through ions diffused into the channel of the transistor can be reduced. Therefore, the forming method of the semiconductor structure can reduce the influence of the punch-through ion on the threshold voltage of the formed transistor, thereby improving the performance of the formed semiconductor structure. In addition, the anti-diffusion ions are formed in the anti-diffusion layer, so that the process operation is more convenient, and the ions in the anti-penetration layer are effectively prevented from diffusing to the top of the fin portion.
In addition, the anti-punch-through layer provided by the invention has anti-punch-through ions, so that the punch-through of a source region and a drain region in the semiconductor structure can be prevented or alleviated, and the leakage current is reduced.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 13 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
In this embodiment, the substrate includes: a first transistor area a and a second transistor area B. In other embodiments, the substrate may also include only the first transistor region or the second transistor region.
In this embodiment, the first transistor area a is used for forming an NMOS transistor; the second transistor region B is used to form a PMOS. In other embodiments, the first transistor region may also be used to form a PMOS transistor; the second transistor region is used for forming an NMOS.
Referring to fig. 4, the substrate further includes: a hard mask 204 on top of the fin 202, wherein the hard mask 204 can protect the top of the fin 202 from being implanted with anti-punch-through ions during a subsequent anti-punch-through ion implantation process, thereby reducing the impact of the anti-punch-through ion implantation on the transistor performance.
In an embodiment of the present invention, the forming of the substrate includes: providing an initial substrate; forming a patterned hard mask 204 on the initial substrate; and patterning the initial substrate by taking the hard mask 204 as a mask to form a substrate 200 and a fin part 202 positioned on the substrate 200, wherein the fin part 202 is used for forming a transistor channel.
Optionally, after disposing the hard mask, an oxide layer 203 is covered over the hard mask 204, and the oxide layer 203 covers the hard mask 204, the fin 202, and the fin gap 20. The material of the oxide layer 203 may be SiO2. The oxide layer 203 is subsequently removed prior to the formation of the anti-punch-through layer.
Referring to fig. 5, the oxide layer 203 is removed, and a punch-through prevention layer 205 is formed, wherein the punch-through prevention layer 205 has punch-through prevention ions therein, and covers the fin and the fin gap to prevent punch-through of the source region and the drain region in the semiconductor structure, thereby reducing leakage current.
Referring to fig. 6, in an embodiment of the invention, the substrate includes a first transistor area a and a second transistor area B. Optionally, the first transistor area a is an NMOS transistor, and the second transistor area B is a PMOS transistor. The punch-through ion doping type is opposite to the transistor doping type of the corresponding region. Optionally, the punch-through preventing ions of the first transistor region are P-type ions, such as boron ions or boron fluoride ions, and the punch-through preventing ions of the second transistor region are N-type ions, such as phosphorus ions or arsenic ions.
Optionally, the penetration preventing layer is disposed only in the first transistor area a. Specifically, on the basis of the process of fig. 5, the punch-through prevention layer portion in the second transistor region B is etched away, and only the punch-through prevention layer portion in the first transistor region a remains. Or in the process step of depositing the anti-punch-through layer, the second transistor area B is shielded by using a mask plate, so that the anti-punch-through layer is only formed on the anti-punch-through layer part in the first transistor area A. This is because NMOS transistors suffer more from loss of dopant ions (e.g., B ions) than PMOS transistors and are thus more susceptible to current punch-through.
Optionally, in an embodiment of the present invention, the substrate includes a first transistor region a and a second transistor region B. And performing first punch-through ion implantation prevention on the first transistor area A, and performing second punch-through ion implantation prevention on the second transistor area B. In other embodiments, when the substrate includes only the first transistor region or the second transistor region, the step of preventing punch-through ion implantation only includes: and performing first punch-through ion implantation prevention on the first transistor area, or performing second punch-through ion implantation prevention on the second transistor area.
If the thickness of the penetration preventing layer 205 is too large, material waste is easily generated; if the thickness of the anti-punch-through layer 205 is too small, it is difficult to sufficiently achieve the effect of preventing the source-drain punch-through of the formed transistor. Therefore, in this embodiment, the thickness of the through layer 205 is 20 to 60 angstroms.
In this embodiment, if the concentration of the punch-through ions in the punch-through prevention layer 205 is too high, the punch-through prevention ions are likely to diffuse toward the top of the fin 202 through the diffusion prevention layer, thereby affecting the performance of the transistor; if the concentration of punch-through preventing ions in the punch-through preventing layer 205 is too low, it is difficult to prevent the source-drain punch-through of the transistor to be formed. Therefore, in this embodiment, the concentration of punch-through preventing ions in the punch-through preventing layer 205 is 1.0E13atoms/cm2-1.0E15atoms/cm2。
In this embodiment, the process parameters of the punch-through ion implantation include: the implantation dose is 1.0E13atoms/cm2-1.0E15atoms/cm2(ii) a The implantation energy is 5KeV-100 KeV.
Referring to fig. 7, in an embodiment of the invention, a protection layer 206 is further formed above the punch-through prevention layer 205, and the protection layer 205 prevents punch-through prevention ions in the punch-through prevention layer 205 from diffusing upward during annealing. Since the purpose of the punch-through prevention layer 205 is to prevent punch-through of source and drain regions in the semiconductor device, which cannot be achieved if punch-through prevention ions are diffused upward, the protective layer 205 is provided to prevent punch-through prevention ions from being diffused upward. Optionally, the material of the protective layer is one or more of silicon nitride, SION, SICB, SiBCN, and SiOCN.
Referring to fig. 8, in an embodiment of the invention, an initial diffusion barrier layer 208 is formed, the initial diffusion barrier layer 208 covers the entire fin 202, i.e., covers the top and the side of the fin, the material of the initial diffusion barrier layer 208 may be silicon dioxide, and the initial diffusion barrier layer 208 may be formed by a Fluid Chemical Vapor Deposition (FCVD) process.
Then, a first annealing process is carried out on the initial anti-diffusion layer 208, the temperature of the first annealing process is 400-650 ℃, the first annealing process is mainly used for volatilizing the high polymer material, and the first annealing process is carried outIn (3), Si-O bonds are gradually formed. And then carrying out thermal ion implantation on the initial diffusion barrier layer 208, wherein the temperature of the thermal ion implantation process is 450-500 ℃. Because the material also contains a large amount of moisture and hydrogen bonds are formed among water molecules, the purpose of the hot ion implantation is to break redundant hydrogen bonds by utilizing the stress of implanted ions. Optionally, the ion implanted in the hot ion implantation process is He, the implantation energy is 1-50Kev, and the implantation dose is 1.0e14-1.0e19atm/cm2. Optionally, a second annealing process may be performed on the initial diffusion barrier layer 208, where the temperature of the second annealing process is 500 ℃ to 700 ℃, H ions in the second annealing process are removed, and the formed initial diffusion barrier layer is cured at the same time;
finally, the initial anti-diffusion layer 208 is etched to a height lower than that of the fin portion, so as to form an anti-diffusion layer 207 (as shown in fig. 9). In the embodiment, the diffusion-proof layer is prepared by adopting a three-step process, and the thermal ion implantation process is introduced in combination with the annealing process, the thermal ion implantation process and other processes, so that the densification temperature of the FCVD oxide is reduced, and the quality of the formed diffusion layer is higher.
In this embodiment, the material of the initial diffusion barrier layer 208 and the diffusion barrier layer 207 may be silicon oxide or silicon oxynitride.
Referring to fig. 10, after the diffusion barrier 207 is formed, the punch-through barrier 205 and the protection layer 206 are etched so that the heights of the punch-through barrier 205 and the protection layer 206 are equal to the diffusion barrier.
Referring to fig. 11, the fin gap 20 is implanted with anti-diffusion ions, which can prevent ions in the anti-punch through layer from diffusing to the top of the fin, specifically, the anti-diffusion ions are implanted in the anti-diffusion layer 207, the protective layer 206 and the anti-punch through layer 205, and due to the doping characteristics, the doping concentration is gradually reduced from the anti-diffusion ion doping source point to the outside, so that the anti-diffusion ions are also simultaneously present in the fin, for example, the anti-diffusion ions are present in the doping region 209 shown in fig. 12, and the anti-diffusion ions can prevent ions in the anti-punch through layer from diffusing to the top of the fin, thereby reducing the anti-punch through ions diffusing into the transistor channel.
The elements of the diffusion preventing ions are fourth main group elements or atomic elements which are not easy to form bonds with the fin atoms. The outermost layer of the group iv element atoms has the same number of electrons as the outermost layer of the atoms of the fin 202, so that it is not easy to form polycons in the fin 202, and thus, it is not easy to change the conductivity of the fin 202; atoms that are not readily bonded to the fin atoms are not readily activated during the subsequent annealing process. Therefore, atoms that do not readily bond to the fin atoms also do not readily alter the conductivity of the fin 202. In addition, the anti-diffusion ions can enter the positions of the gaps formed by the atoms of the fin portion 202, so that the anti-punch-through ions are prevented from diffusing to the top of the fin portion 202 through the gaps, and the performance of the formed semiconductor structure can be improved.
Therefore, the diffusion barrier layer 207 can prevent punch-through ions in the fin 202 from diffusing to the top of the fin 202 during the subsequent annealing process, so that the punch-through ions diffusing into the transistor channel can be reduced, the influence of the punch-through ions on the threshold voltage of the formed transistor can be reduced, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the diffusion preventing ions include: one or more of carbon ions, germanium ions and nitrogen ions. After the carbon ions, the germanium ions and the nitrogen ions enter the atomic gap of the fin 202, the punch-through ions are prevented from diffusing to the top of the fin 202. In addition, nitrogen ions are not easily activated during the annealing process and thus do not easily affect the conductivity of the fin 202; carbon and germanium are group iv elements, and are activated during the annealing process, which also does not easily affect the conductivity of the fin 202.
If the concentration of the anti-diffusion ions in the anti-diffusion layer 207 is too high, the conductivity of the fin portion 202 is easily affected, and the performance of the transistor is reduced; if the concentration of the diffusion preventing layer 207 is too high or too low, it is difficult to block the diffusion of punch-through preventing ions toward the top of the fin 202. Therefore, in this embodiment, the concentration of the anti-diffusion ions in the anti-diffusion layer 207 is 1.0E13atoms/cm2-1.0E16atoms/cm2。
In this embodiment, the process parameters of the diffusion-preventing ion implantation include: the injection energy is 1KeV-30 KeV; the implantation dose is 1.0E13atoms/cm2-1.0E16atoms/cm2。
Referring to fig. 13, the hard mask is finally removed from the semiconductor structure and annealed.
The annealing treatment is used for activating the punch-through preventing ions, so that the punch-through preventing ions play a role in preventing source-drain punch-through. During the annealing process, the anti-diffusion ions in the anti-diffusion layer 207 can prevent the anti-punch-through ions in the anti-punch-through layer from diffusing to the top of the fin 202, so that the influence of the anti-punch-through ions on the formed transistor can be reduced, and the performance of the semiconductor structure can be improved.
In this embodiment, the annealing temperature of the annealing treatment is greater than or equal to 850 ℃.
In this embodiment, after performing the degradation process, the forming method further includes: a gate structure is formed across the fin 202, covering a portion of the sidewalls and top surface of the fin 203.
In this embodiment, the top of the penetration prevention layer is flush with the bottom of the diffusion prevention layer. In other embodiments, the top of the penetration-preventing layer may be lower than the bottom of the diffusion-preventing layer, or the top of the penetration-preventing layer is higher than the top of the diffusion-preventing layer, and the bottom of the penetration-preventing layer is lower than the top of the diffusion-preventing layer.
FIG. 14 is a schematic diagram of a semiconductor structure formation step of the present invention.
The invention also comprises a semiconductor structure manufactured by the semiconductor forming method.
In summary, in the semiconductor forming method of the present invention, the anti-punch-through layer is formed, which can prevent or reduce punch-through between the source region and the drain region, thereby reducing leakage current;
furthermore, a diffusion-preventing layer and a protective layer are arranged beside the punch-through-preventing layer, the protective layer can prevent punch-through ions from diffusing to the outside, and the diffusion-preventing layer can reduce the punch-through-preventing ions diffused into a channel of the transistor.
Furthermore, the diffusion-preventing ions are formed in the diffusion-preventing layers in the gaps between the adjacent fin portions, so that the process operation is more convenient, and the ions in the penetration-preventing layers are effectively prevented from diffusing to the tops of the fin portions.
Furthermore, the diffusion-proof layer is prepared by adopting a three-step process, and the thermal ion implantation process is introduced by combining the annealing process, the thermal ion implantation process and other processes, so that the densification temperature of the FCVD oxide is reduced, and the quality of the formed diffusion layer is higher.
Therefore, the method for forming the semiconductor structure can improve the performance of the formed semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein fin parts are arranged on the substrate, and fin part gaps are formed between adjacent fin parts;
setting a hard mask above the fin portion;
forming a penetration preventing layer covering the hard mask, the fin part and the fin part gap, wherein penetration preventing ions are arranged in the penetration preventing layer and are used for preventing a source region and a drain region in the semiconductor structure from penetrating;
forming an anti-diffusion layer, wherein the height of the anti-diffusion layer is lower than that of the fin part;
etching the penetration-preventing layer to enable the height of the penetration-preventing layer to be flush with the diffusion-preventing layer;
injecting anti-diffusion ions into the fin part gap, wherein the anti-diffusion ions can prevent the anti-punch-through ions from diffusing to the top of the fin part;
removing the hard mask;
and annealing is carried out.
2. The method of forming a semiconductor structure of claim 1, wherein the annealing temperature is greater than or equal to 850 ℃.
3. The method of claim 1, wherein the ions implanted into the diffusion barrier layer are one or more of carbon ions, germanium ions, and nitrogen ions.
4. The method of claim 1, wherein a protective layer is formed over the punch-through prevention layer, the protective layer preventing upward diffusion of the punch-through prevention ions.
5. The method according to claim 4, wherein the protective layer is made of one or more of silicon nitride, SiON, SiCB, SiBCN, and SiOCN.
6. The method of forming a semiconductor structure of claim 1, wherein forming a diffusion barrier comprises:
forming an initial anti-diffusion layer, wherein the initial anti-diffusion layer covers the whole fin part and is formed by adopting a fluid chemical vapor deposition process;
carrying out a first annealing process on the initial anti-diffusion layer, wherein the temperature of the first annealing process is 400-650 ℃;
carrying out thermal ion implantation on the initial anti-diffusion layer, wherein the temperature of the thermal ion implantation process is 450-500 ℃;
and etching the initial anti-diffusion layer to enable the height of the initial anti-diffusion layer to be lower than that of the fin portion, and forming the anti-diffusion layer.
7. The method of claim 6, wherein a second annealing process is performed on the initial anti-diffusion layer after the thermal ion implantation, wherein the second annealing process is performed at a temperature of 500 ℃ to 700 ℃.
8. The method of claim 6, wherein in the thermal ion implantation process, the implanted ions are He.
9. The method of forming a semiconductor structure of claim 6, wherein said thermal ion implantation has an energy of 1-50Kev and a dose of 1.0e14-1.0e19atm/cm <2 >.
10. The method for forming a semiconductor structure according to claim 4, wherein after the diffusion-preventing layer is formed, the penetration-preventing layer and the protective layer are etched so that the heights of the penetration-preventing layer and the protective layer are flush with the diffusion-preventing layer.
11. The method of claim 1, wherein after the hard mask is disposed, covering an oxide layer over the hard mask, the oxide layer being removed prior to forming the anti-punch through layer.
12. The method of claim 1, wherein the substrate comprises a first transistor region and a second transistor region, and wherein the punch-through ion doping type is opposite to a transistor doping type of a corresponding region.
13. The method as claimed in claim 12, wherein the first transistor region is an NMOS transistor and the anti-punch-through ion doping type in the first transistor region is a P-type.
14. The method of claim 12, wherein a punch-through prevention layer is formed only in the first transistor region.
15. The method of claim 13, wherein the ions of the anti-punch through layer in the first transistor region are boron ions or boron fluoride ions.
16. A semiconductor structure formed using the method of any of claims 1-15.
CN201710328760.9A 2017-05-11 2017-05-11 Semiconductor structure and forming method thereof Active CN108878526B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710328760.9A CN108878526B (en) 2017-05-11 2017-05-11 Semiconductor structure and forming method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710328760.9A CN108878526B (en) 2017-05-11 2017-05-11 Semiconductor structure and forming method thereof

Publications (2)

Publication Number Publication Date
CN108878526A CN108878526A (en) 2018-11-23
CN108878526B true CN108878526B (en) 2021-11-09

Family

ID=64319363

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710328760.9A Active CN108878526B (en) 2017-05-11 2017-05-11 Semiconductor structure and forming method thereof

Country Status (1)

Country Link
CN (1) CN108878526B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112018163B (en) * 2019-05-30 2024-10-29 中芯国际集成电路制造(上海)有限公司 Semiconductor structure and forming method thereof

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733313A (en) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 Fin-type field effect transistor forming method
CN105990430A (en) * 2015-02-27 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device and preparation method thereof, and electronic device
CN106601678A (en) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device, preparation method therefor, and electronic device
CN106601620A (en) * 2015-10-16 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device, preparation method thereof and electronic device
CN106611789A (en) * 2015-10-26 2017-05-03 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9805987B2 (en) * 2015-09-04 2017-10-31 International Business Machines Corporation Self-aligned punch through stopper liner for bulk FinFET

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733313A (en) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 Fin-type field effect transistor forming method
CN105990430A (en) * 2015-02-27 2016-10-05 中芯国际集成电路制造(上海)有限公司 Semiconductor device and preparation method thereof, and electronic device
CN106601678A (en) * 2015-10-14 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device, preparation method therefor, and electronic device
CN106601620A (en) * 2015-10-16 2017-04-26 中芯国际集成电路制造(上海)有限公司 Semiconductor device, preparation method thereof and electronic device
CN106611789A (en) * 2015-10-26 2017-05-03 中芯国际集成电路制造(上海)有限公司 Fin field effect transistor and forming method thereof

Also Published As

Publication number Publication date
CN108878526A (en) 2018-11-23

Similar Documents

Publication Publication Date Title
US7217627B2 (en) Semiconductor devices having diffusion barrier regions and halo implant regions and methods of fabricating the same
JP5235486B2 (en) Semiconductor device
CN107919324B (en) Method for forming semiconductor device
CN102646590B (en) Method for forming NMOS (n-channel metal oxide semiconductor) transistor
CN102800595A (en) NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method
CN107785425B (en) Semiconductor device and method of forming the same
CN106856169B (en) Transistor and forming method thereof
CN108878526B (en) Semiconductor structure and forming method thereof
CN108281485B (en) Semiconductor structure and forming method thereof
CN110690109B (en) Semiconductor device and method of forming the same
KR100508867B1 (en) Method for fabricating the p-channel MOS transistor and CMOS transistor
CN108807268B (en) Semiconductor structure and forming method thereof
KR101131965B1 (en) Method for fabricating semiconductor device
CN110718454A (en) Semiconductor device and method of forming the same
KR100835519B1 (en) Method for fabricating a semiconductor device
KR100799020B1 (en) Method of manufacturing a semiconductor memory device
KR101180500B1 (en) Method for manufacturing Transistor
KR100728958B1 (en) Method of manufacturing semicondutor device
KR100650900B1 (en) Method for fabricating semiconductor device
CN108281482B (en) Semiconductor structure and forming method thereof
KR100588783B1 (en) Method For Manufacturing Semiconductor Devices
CN107591330B (en) Method for forming semiconductor structure
CN107799469B (en) Method for forming semiconductor device
CN107785319B (en) Method for forming semiconductor structure
KR100600253B1 (en) Method For Manufacturing Semiconductor Devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant