CN108878349A - A kind of structure and preparation method thereof of novel SOI substrate - Google Patents
A kind of structure and preparation method thereof of novel SOI substrate Download PDFInfo
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- CN108878349A CN108878349A CN201810675123.3A CN201810675123A CN108878349A CN 108878349 A CN108878349 A CN 108878349A CN 201810675123 A CN201810675123 A CN 201810675123A CN 108878349 A CN108878349 A CN 108878349A
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- 239000000758 substrate Substances 0.000 title claims abstract description 111
- 238000002360 preparation method Methods 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 32
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000001257 hydrogen Substances 0.000 claims abstract description 15
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 15
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 73
- 239000010703 silicon Substances 0.000 claims description 73
- 229910052751 metal Inorganic materials 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 53
- 238000004544 sputter deposition Methods 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 28
- 238000002347 injection Methods 0.000 claims description 18
- 239000007924 injection Substances 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 18
- 238000007254 oxidation reaction Methods 0.000 claims description 18
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 12
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 claims description 10
- 239000011651 chromium Substances 0.000 claims description 8
- 239000010936 titanium Substances 0.000 claims description 8
- 230000003028 elevating effect Effects 0.000 claims description 6
- RPAJSBKBKSSMLJ-DFWYDOINSA-N (2s)-2-aminopentanedioic acid;hydrochloride Chemical compound Cl.OC(=O)[C@@H](N)CCC(O)=O RPAJSBKBKSSMLJ-DFWYDOINSA-N 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910001092 metal group alloy Inorganic materials 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 239000000203 mixture Substances 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- 229910052715 tantalum Inorganic materials 0.000 claims description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000005546 reactive sputtering Methods 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims 1
- 230000005684 electric field Effects 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 111
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 72
- 238000005498 polishing Methods 0.000 description 27
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 24
- 230000008569 process Effects 0.000 description 21
- 239000003292 glue Substances 0.000 description 20
- 239000000126 substance Substances 0.000 description 20
- 229910052786 argon Inorganic materials 0.000 description 16
- 238000010586 diagram Methods 0.000 description 15
- 239000007788 liquid Substances 0.000 description 14
- 230000008859 change Effects 0.000 description 12
- 239000001301 oxygen Substances 0.000 description 10
- 229910052760 oxygen Inorganic materials 0.000 description 10
- 230000009471 action Effects 0.000 description 9
- -1 argon ion Chemical class 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 8
- 238000006243 chemical reaction Methods 0.000 description 8
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- 239000006061 abrasive grain Substances 0.000 description 5
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- 239000012212 insulator Substances 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000376 reactant Substances 0.000 description 5
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- 230000001133 acceleration Effects 0.000 description 4
- 235000013399 edible fruits Nutrition 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 229910044991 metal oxide Inorganic materials 0.000 description 4
- 150000004706 metal oxides Chemical class 0.000 description 4
- 238000000386 microscopy Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 230000005611 electricity Effects 0.000 description 3
- 150000002431 hydrogen Chemical class 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
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- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
The structure that the present invention discloses a kind of SOI substrate includes：First Si piece and the 2nd Si piece aoxidize the first Si piece using the method for thermal oxide, obtain layer of oxide layer, perform etching to the oxide layer of the first Si piece, and the oxide layer for having channel is formed；Then hydrogen is injected to the 2nd Si piece piece, the first Si piece a and the 2nd Si piece b is bonded, and the thickness of the 2nd Si piece of top layer is thinned, form SOI substrate.The present invention also provides a kind of preparation methods of SOI substrate structure.Influence of the electric field of fixed positive charge generation in traditional SOI substrate to epitaxial growth can be effectively reduced, and improves the thermal conductivity of BOX buried layer.
Description
Technical field
The invention belongs to technology of semiconductor chips fields more particularly to a kind of structure of SOI substrate and preparation method thereof.
Background technique
SOI full name is Silicon-On-Insulator, as silicon in insulating substrate, be briefly exactly in top layer silicon and
One layer of buried oxide layer is introduced between base substrate.SOI substrate opposite bank silicon substrate is more advantageous, for example, at high speed, it is low
Power consumption, low soft error, anti-latch up effect etc..SOI substrate is widely used in the products, high-performance such as 0.18 μm of grade microprocessor below
The fields such as special circuit and medical biotechnology.
However, there is also its intrinsic characteristics for SOI substrate.One of most typically characteristic is exactly self-heating effect.Self-heating effect
It should be since the heating conduction of buried oxide layer in SOI substrate is bad, the heat that carrier impact generates all is collected in trap,
This can reduce the service life of carrier.In addition, there is also fixed positive charge between BOX buried oxide layer and top layer silicon in SOI substrate,
Fixed positive charge can generate built-in field, and the presence of electric field can have an impact the growth of epitaxial layer above substrate, reduce extension
The quality of layer growth.
Summary of the invention
The purpose of the present invention is to provide a kind of structure of SOI substrate and preparation methods, carve in the oxide layer of SOI substrate
Channel out is lost, and to channel region splash-proofing sputtering metal, it is thermally conductive to can solve BOX buried oxide layer present in traditional SOI substrate in this way
The problem of performance difference, while the metal sputtered can play the role of shielding built-in field.The thermally conductive system of BOX buried layer in SOI substrate
Number is low, such as SiO2Thermal coefficient be 7.6W/mK, and the thermal coefficient of Si be 150W/mK.The thermal conductivity ratio BOX of metal is buried
The thermal conductivity of layer is good, can be improved the conduction efficiency of heat in buried layer.Meanwhile to the trench area splash-proofing sputtering metal in BOX buried layer, meeting
The a large amount of negative electrical charges of congregate in trench area, a large amount of positive charges between BOX buried layer and top layer Si form closure electric field.It can
To reduce the influence that built-in field caused by fixed positive charge grows SOI substrate upper epitaxial layer.Therefore the metal of sputtering can
To play the role of shielding built-in field.Meanwhile the size of trench area sectional area electricity according to caused by fixed positive charge
Field intensity is adjusted.
A kind of structure of SOI substrate, including：First Si piece and the 2nd Si piece carry out the first Si piece using thermal oxidation method
Oxidation after aoxidizing certain thickness, forms layer of oxide layer, performs etching to the oxide layer, several channels are formed, to channel region
Carry out splash-proofing sputtering metal；To the hydrogen ion of the 2nd Si piece injection certain depth range, the 2nd Si piece is located at the upper surface of the first Si piece, will
First Si piece oxide layer and the 2nd Si piece injection hydrogen ion surface are bonded, and are thinned to 0.05~0.3 μ to the 2nd Si piece thickness
M forms SOI substrate.
Preferably, oxidated layer thickness is 0.2~1.2 μm.
Preferably, the feature of channel region is：Depth be 0.2~0.5 μm, 0.2~8 μm of width, 0.2~8 μ of channel spacing
m。
Preferably, the cross sectional shape of channel region is one or more of rectangle, triangle, trapezoidal, parallelogram
Preferably, sputtering metal can for chromium (Cr), tungsten (W), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta) and its
The thermal expansion coefficient of the mixture of they and other metals, final metal alloy is close with buried oxide layer.
Preferably, injecting hydrionic depth to the 2nd Si piece is 0.05~0.3 μm.
Preferably, can also aoxidize using thermal oxidation method to the 2nd Si piece, layer of oxide layer is obtained, to described
Oxide layer performs etching, and forms several channels, while carrying out splash-proofing sputtering metal to channel.
A kind of preparation method of SOI substrate structure, including：
First Si piece and the 2nd Si piece are provided, to the first Si piece upper surface carry out thermal oxide, oxidated layer thickness be 0.2~
1.2 μm, and the first Si piece oxide layer is polished；
The oxide layer of the first Si piece is performed etching, several channel regions are etched, depth is 0.2~0.5 μm, width
0.2~8 μm, 0.2~8 μm of channel spacing；
(CMP) technique is chemically-mechanicapolish polished to the first Si piece oxidation layer surface, then channel region is splashed
The excess metal layer of channel region non-in oxide layer is finally purged by radioglold category；
Using the first Si piece a as underlying substrate material；
Hydrogen ion is injected in the 2nd Si piece b, the depth of injection is 0.05~0.3 μm, as upper layer basis material；
The 2nd Si piece b is injected hydrionic surface to be bonded with the oxidation layer surface of the first Si piece, specially：
Three phases are divided to increase temperature, the temperature elevating range of first stage is 300~400 DEG C, 2~3h of duration, realizes the first Si piece
With the bonding of the 2nd Si piece；The temperature elevating range of second stage is 450~650 DEG C, 30~45min of duration, so that top layer silicon
It is thinned to a thickness of 0.05~0.3 μm, the temperature elevating range of phase III is 950~1050 DEG C, and the duration is about 2min, to increase
The bond strength of strong first Si piece and the 2nd Si piece；
In ultra-high vacuum environment, it is annealed to room temperature, takes out SOI substrate.
Preferably, performing etching to the oxide layer of the first Si piece, the depth of etching is the 20~70% of oxidated layer thickness,
And the distance between adjacent channel is about channel width.
Preferably, channel region cross sectional shape is one or more of rectangle, triangle, trapezoidal, parallelogram.
Preferably, the technique that splash-proofing sputtering metal uses is d.c. sputtering, radio-frequency sputtering, reactive sputtering, magnetron sputtering, collimation
One of sputtering.
Preferably, splash-proofing sputtering metal be chromium (Cr), tungsten (W), molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta) and its they with
The thermal expansion coefficient of the mixture of other metals, final metal alloy is close with buried oxide layer.
Preferably, the area of section of channel region accounts for the percentage of entire oxide skin(coating) area of section according to the entirety of system
Performance determines.
Preferably, the technique for carrying out thermal oxide to the first Si piece is in dry-oxygen oxidation, wet-oxygen oxidation and steam oxidation
It is one of.
Structure of SOI substrate of the invention and preparation method thereof provides the first Si piece and the 2nd Si piece, by the first Si
The upper surface of piece carries out thermal oxide, forms certain thickness oxide layer.The oxide layer of first Si piece is performed etching, number is etched
Channel.Then, to the channel region splash-proofing sputtering metal of oxide layer, then, hydrogen ion is injected to the 2nd Si piece, then by the 2nd Si piece
Hydrionic surface is injected to be bonded with the oxidation layer surface of the first Si piece.Then temperature is increased, the thickness of the 2nd Si piece is thinned
Degree, and polishing is carried out to the 2nd Si piece surface using chemically mechanical polishing (CMP) technique and is polished.Temperature is finally reduced to room
Temperature obtains a piece of novel SOI substrate.
A kind of structure of novel SOI substrate of the invention has the following advantages that with preparation method：
Help to mention since the heating conduction of metal is more preferable comprising metal valley in the BOX buried layer oxidation of 1.SOI substrate
The capacity of heat transmission of high BOX buried layer.
2. the metal of sputtering can be negative in channel region congregate since the channel region to oxide skin(coating) has sputtered certain metal
Charge, the fixed positive charge between meeting and BOX buried layer and top layer Si form closure electric field.The metal of sputtering can play shielding part
Divide the effect of electric field, this creates a good environment for subsequent outer layer growth.
Simple process used by 3., it is easy to operate, and material can be saved, it is suitable for large-scale industrial production.
Detailed description of the invention
Fig. 1 is the flow diagram of novel SOI substrate production；
Fig. 2 is the schematic diagram aoxidized to Si piece；
Fig. 3 is the schematic diagram that channel is performed etching to the oxide layer of Si piece；
Fig. 4 is the structural schematic diagram for sputter to oxide layer channel region in Fig. 3 certain metal；
Fig. 5 is the structural schematic diagram that hydrogen is injected to Si piece；
Fig. 6 is the structural schematic diagram of upper and lower level basis material bonding in embodiment 1；
Fig. 7 is a kind of structural schematic diagram of novel SOI substrate of embodiment 1；
Fig. 8 is the structural schematic diagram that hydrogen is aoxidized and injected to Si piece；
Fig. 9 is the structural schematic diagram after performing etching to the oxide layer of Fig. 8；
Figure 10 is the structural schematic diagram for sputter to oxide layer channel in Fig. 9 certain metal；
Figure 11 is the structural schematic diagram of upper and lower level basis material bonding in embodiment 3；
Figure 12 is a kind of structural schematic diagram of novel SOI substrate of embodiment 3；
Figure 13 is the structural schematic diagram of upper and lower level basis material bonding in embodiment 4；
Figure 14 is a kind of structural schematic diagram of novel SOI substrate of embodiment 4；
Figure 15 is the temperature results change curve of embodiment 1；
Figure 16 is the temperature results change curve of embodiment 2；
Figure 17 is the temperature results change curve of embodiment 3；
Figure 18 is the temperature results change curve of embodiment 4.
In figure：1, SOI substrate top thin layer silicon；2, to certain metal of trench area sputtering；3, the oxide layer in substrate；4,
Silicon support chip in the underlying substrate material of SOI substrate；5, to the hydrogen ion injected in Si piece.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.But these descriptions are merely illustrative, is not
It limits the scope of the present disclosure.It is according to the various structural schematic diagrams of open embodiment, in order to clear in the following figures
Expresses and be exaggerated some regions to Chu.
In order not to obscure people, the important step prepared for this structure, conventional flowsheet are only described herein
It not will be described in detail herein, such as cleaning, early-stage preparations etc..
The embodiment of the present invention provides a kind of structure and preparation method thereof of SOI substrate, using the first of two panels routine
Si piece and the 2nd Si piece.
Referring to Fig. 1~14, to be illustrated to the SOI substrate of single layer prepared by the present invention and double-level-metal tunnel,
Specific step is as follows：
Embodiment 1：
A kind of the first preparation method of single-layer metal channel SOI substrate, steps are as follows：
Step 1, the preparation of SOI substrate underlying substrate material, as shown in Figure 2, Figure 3, Figure 4.
1a. chooses the first Si piece, carries out thermal oxide to the upper surface of the first Si piece, silicon wafer is placed in furnace chamber first,
And furnace chamber is evacuated.Then, after exhausting vacuum, setting program is begun to warm up.After temperature reaches 1050 DEG C, quickly it is passed through
The purity oxygen of one atmospheric pressure.Then after leading to oxygen, 20h is kept, is being evacuated.Finally silicon wafer is saved in a vacuum,
It naturally rings to silicon chip extracting after room temperature.The oxidated layer thickness of first Si piece is 1 μm；
1b. polishes the first Si piece oxidation layer surface using CMP process.The oxide layer table of the first Si piece is fixed first
Polishing pad is placed on abrasive disk by face in the bottom of rubbing head.Then, when polishing, the rubbing head of rotation is pressed in
On the polishing pad of rotation.Then, lapping liquid is allowed to flow between silicon chip surface and polishing pad, lapping liquid can be evenly distributed on polishing
On pad.Then, the chemical substance in lapping liquid can react with Si piece surfacing, convert insoluble substance to readily soluble
Substance.Then, these chemical reactants are removed from Si piece surface by the micromechanics rubbing action of abrasive grain.It finally carries out clear
It washes, dry, obtain smooth oxide layer；
1c. uses photoetching, performs etching to the oxide layer of the first Si on piece, carries out gluing, bondline thickness to silicon wafer first
It is 1 μm, then the silicon wafer for being painted with glue is baked, 150 DEG C of temperature, time 2min.Using the ultraviolet light of wavelength 330nm to glue
Face is exposed, and silicon wafer and reticle are in close contact, and is developed with developer for negative photoresist to silicon wafer, time 5min, developer solution temperature
Degree is 40 DEG C, and silicon wafer is put into insulating box, and temperature is 190 DEG C, time 30min, and with infrared light irradiation 10min, apart from glue
Face 6cm corrodes silicon wafer using wet etching.Then, the remaining glue surface in silicon wafer is removed, finally silicon wafer is carried out clear
It washes, it is dry.Several channel regions etched, depth are 0.5 μm, 4 μm of width, 4 μm of channel spacing；
1d. is blocked with non-channel region of the cover material layer (such as resist) to the first Si piece oxide layer, using magnetic
Control sputtering carries out splash-proofing sputtering metal to the channel region in the first Si piece oxide layer.Firstly, making reaction chamber reach vacuum condition, generally
Pressure is controlled 2 × 10-5torr.Then, it is passed through argon gas into reaction chamber, and opens DC power supply.Then electricity can occur for argon gas
From generation argon ion and an electronics.Then, under the action of electric field, anode is flown in electrons acceleration, meanwhile, argon ion can add
Speed flies to the target of cathode, i.e. certain metal, so that target is knocked off the surface for reaching substrate, generates metallic film.It has sputtered
Bi Hou is purged using excess metal and barrier material layer of the CMP process to channel region non-in oxide layer, and has gold to sputtering
The channel surface of category carries out smooth.
Step 2, the preparation of SOI substrate upper layer basis material, as shown in Figure 5.
2a. chooses the 2nd Si piece, polish to the 2nd Si piece upper surface using CMP process smooth；
2b. carries out hydrogen ion injection to the 2nd Si piece, and the depth of injection is 0.3 μm.
Step 3, upper and lower level basis material is bonded, as shown in Figure 6
3a. is staggered relatively in ultra-high vacuum environment by the first Si piece and the 2nd Si piece, and pressure control is 10-6Pa, will
Temperature is increased to 350 DEG C, duration 2h, so that the oxide layer of the first Si piece is bonded with the note hydrogen layer of the 2nd Si piece；
3b. continues to increase temperature to 600 DEG C, duration 40min, and the 2nd Si sector-meeting is broken at injection hydrogen layer, simultaneously
The extra Si of the 2nd Si piece plane of disruption is removed, 0.3 μm or so of thin-layer silicon can be retained in the oxide layer of the first Si piece；
3c. continues to increase temperature to 1050 DEG C or so, and the duration is about 2min, and then anneal 2h, enhances the first Si piece
With the bond strength of the 2nd Si piece.
Step 4, a piece of novel SOI substrate is constituted, as shown in Figure 7
In ultra-high vacuum environment, (pressure is about 10 to 4a.-6Pa in), it is annealed to room temperature；
4b. polish to obtained SOI substrate surface smooth using CMP process, finally obtains a piece of SOI substrate.System
Standby SOI substrate out, the synthesis thermal conductivity of BOX buried layer improve 20%, and outer layer growth quality increases.
Step 5, traditional SOI substrate is compared with the heat dissipation of novel SOI substrate
1a. processes fully- depleted insulator by traditional CMOS technology on traditional SOI substrate and novel SOI substrate respectively
Upper silicon (FD-SOI) n-channel metal oxide semiconductor field effect tube (MOSFETs).Grid and the voltage of drain electrode be respectively 3V and
8V passes through the temperature of the direct measurement device of high-resolution infrared thermal microscopy during device work.The temperature knot measured
Fruit change rate curve is as shown in figure 15, and abscissa represents the distance between drain electrode and source electrode in figure, and ordinate represents on device
Temperature.Triangle indicates the temperature change of device on traditional SOI substrate, and square indicates the temperature of device in novel SOI substrate
Variation.
Embodiment 2：
A kind of second of preparation method of single-layer metal channel SOI substrate, steps are as follows：
Step 1, the preparation of SOI substrate underlying substrate material, as shown in Figure 2, Figure 3, Figure 4.
1a. chooses the first Si piece, carries out thermal oxide to the upper surface of the first Si piece, silicon wafer is placed in furnace chamber first,
And furnace chamber is evacuated.Then, after exhausting vacuum, setting program is begun to warm up.After temperature reaches 1050 DEG C, quickly it is passed through
The purity oxygen of one atmospheric pressure.Then after leading to oxygen, 20h is kept, is being evacuated.Finally silicon wafer is saved in a vacuum,
It naturally rings to silicon chip extracting after room temperature.The oxidated layer thickness of first Si piece is 0.6 μm；
1b. polishes the first Si piece oxidation layer surface using CMP process.The oxide layer table of the first Si piece is fixed first
Polishing pad is placed on abrasive disk by face in the bottom of rubbing head.Then, when polishing, the rubbing head of rotation is pressed in
On the polishing pad of rotation.Then, lapping liquid is allowed to flow between silicon chip surface and polishing pad, lapping liquid can be evenly distributed on polishing
On pad.Then, the chemical substance in lapping liquid can react with Si piece surfacing, convert insoluble substance to readily soluble
Substance.Then, these chemical reactants are removed from Si piece surface by the micromechanics rubbing action of abrasive grain.It finally carries out clear
It washes, dry, obtain smooth oxide layer；
1c. uses photoetching, performs etching to the oxide layer of the first Si on piece, carries out gluing, bondline thickness to silicon wafer first
It is 1 μm, then the silicon wafer for being painted with glue is baked, 150 DEG C of temperature, time 2min.Using the ultraviolet light of wavelength 330nm to glue
Face is exposed, and silicon wafer and reticle are in close contact, and is developed with developer for negative photoresist to silicon wafer, time 5min, developer solution temperature
Degree is 40 DEG C, and silicon wafer is put into insulating box, and temperature is 190 DEG C, time 30min, and with infrared light irradiation 10min, apart from glue
Face 6cm corrodes silicon wafer using wet etching.Then, the remaining glue surface in silicon wafer is removed, finally silicon wafer is carried out clear
It washes, it is dry.Several channel regions etched, depth are 0.2 μm, 7 μm of width, 5 μm of channel spacing；
1d. is blocked with non-channel region of the cover material layer (such as resist) to the first Si piece oxide layer, using magnetic
Control sputtering carries out splash-proofing sputtering metal to the channel region in the first Si piece oxide layer.Firstly, making reaction chamber reach vacuum condition, generally
Pressure is controlled 2 × 10-5torr.Then, it is passed through argon gas into reaction chamber, and opens DC power supply.Then electricity can occur for argon gas
From generation argon ion and an electronics.Then, under the action of electric field, anode is flown in electrons acceleration, meanwhile, argon ion can add
Speed flies to the target of cathode, i.e. certain metal, so that target is knocked off the surface for reaching substrate, generates metallic film.It has sputtered
Bi Hou is purged using excess metal and barrier material layer of the CMP process to channel region non-in oxide layer, and has gold to sputtering
The channel surface of category carries out smooth.
Step 2, the preparation of SOI substrate upper layer basis material, as shown in Figure 5.
2a. chooses the 2nd Si piece, polish to the 2nd Si piece upper surface using CMP process smooth；
2b. carries out hydrogen ion injection to the 2nd Si piece, and the depth of injection is 0.1 μm.
Step 3, upper and lower level basis material is bonded, as shown in Figure 6
3a. is staggered relatively in ultra-high vacuum environment by the first Si piece and the 2nd Si piece, and pressure control is 10-6Pa, will
Temperature is increased to 370 DEG C, duration 2h, so that the oxide layer of the first Si piece is bonded with the note hydrogen layer of the 2nd Si piece；
3b. continues to increase temperature to 630 DEG C, duration 35min, and the 2nd Si sector-meeting is broken at injection hydrogen layer, simultaneously
The extra Si of the 2nd Si piece plane of disruption is removed, 0.3 μm or so of thin-layer silicon can be retained in the oxide layer of the first Si piece；
3c. continue increase temperature to 980 DEG C or so, the duration is about 2min, and then anneal 2h, enhancing the first Si piece and
The bond strength of 2nd Si piece piece.
Step 4, a piece of novel SOI substrate is constituted, as shown in Figure 7
In ultra-high vacuum environment, (pressure is about 10 to 4a.-6Pa in), it is annealed to room temperature；
4b. polish to obtained SOI substrate surface smooth using CMP process, finally obtains a piece of SOI substrate.
Step 5, traditional SOI substrate is compared with the heat dissipation of novel SOI substrate
1a. processes fully- depleted insulator by traditional CMOS technology on traditional SOI substrate and novel SOI substrate respectively
Upper silicon (FD-SOI) n-channel metal oxide semiconductor field effect tube (MOSFETs).Grid and the voltage of drain electrode be respectively 3V and
8V passes through the temperature of the direct measurement device of high-resolution infrared thermal microscopy during device work.The temperature knot measured
Fruit change rate curve is as shown in figure 16, and abscissa represents the distance between drain electrode and source electrode in figure, and ordinate represents on device
Temperature.Triangle indicates the temperature change of device on traditional SOI substrate, and square indicates the temperature of device in novel SOI substrate
Variation.
Embodiment 3：
A kind of the third preparation method of single-layer metal channel SOI substrate, steps are as follows：
Step 1, the preparation of SOI substrate basis material at the middle and upper levels, as shown in Fig. 8, Fig. 9, Figure 10.
1a. chooses the first Si piece, carries out injection hydrogen to the upper surface of the first Si piece, the depth of injection is 1.5 μm；
After 1b. has infused hydrogen, thermal oxide is carried out to the upper surface of the first Si piece, silicon wafer is placed in furnace chamber first, and handle
Furnace chamber is evacuated.Then, after exhausting vacuum, setting program is begun to warm up.After temperature reaches 1050 DEG C, it is quickly passed through one
The purity oxygen of atmospheric pressure.Then after leading to oxygen, 20h is kept, is being evacuated.Finally silicon wafer is saved in a vacuum, it is natural
It drops to silicon chip extracting after room temperature.Oxide layer with a thickness of 1 μm；
1c. polishes the first Si piece oxidation layer surface using CMP process, fixes the first Si piece first in rubbing head
Polishing pad is placed on abrasive disk by bottom.Then, when polishing, the rubbing head of rotation is pressed in the polishing pad of rotation
On.Then, lapping liquid is allowed to flow between silicon chip surface and polishing pad, lapping liquid can be evenly distributed on polishing pad.Then, it grinds
Chemical substance in grinding fluid can react with Si piece surfacing, convert insoluble substance to readily soluble substance.Then, lead to
The micromechanics rubbing action for crossing abrasive grain removes these chemical reactants from Si piece surface；
1d. uses photoetching, performs etching to the oxide layer of the first Si on piece, carries out gluing, bondline thickness to silicon wafer first
It is 1 μm, then the silicon wafer for being painted with glue is baked, 150 DEG C of temperature, time 2min.Using the ultraviolet light of wavelength 330nm to glue
Face is exposed, and silicon wafer and reticle are in close contact, and is developed with developer for negative photoresist to silicon wafer, time 5min, developer solution temperature
Degree is 40 DEG C, and silicon wafer is put into insulating box, and temperature is 190 DEG C, time 30min, and with infrared light irradiation 10min, apart from glue
Face 6cm corrodes silicon wafer using wet etching.Then, the remaining glue surface in silicon wafer is removed, finally silicon wafer is carried out clear
It washes, it is dry.Several channel regions etched, depth are 0.2 μm, 2.5 μm of width, 2.5 μm of channel spacing；
1e. is blocked with non-channel region of the cover material layer (such as resist) to the first Si piece oxide layer, using magnetic
Control sputtering, carries out sputtering certain metal to the channel region in the first Si piece oxide layer.Firstly, reaction chamber is made to reach vacuum condition,
General control pressure is 2 × 10-5torr.Then, it is passed through argon gas into reaction chamber, and opens DC power supply.Then argon gas can be sent out
Raw ionization generates argon ion and an electronics.Then, under the action of electric field, anode is flown in electrons acceleration, meanwhile, argon ion
The target of cathode, i.e. certain metal can be accelerated to fly to, so that target is knocked off the surface for reaching substrate, generate metallic film.It splashes
It after penetrating, is purged using excess metal of the CMP process to channel region non-in oxide layer, and has the channel of metal to sputtering
Surface carries out smooth.
Step 2, underlying substrate material is chosen, underlying substrate material can be the second Si piece.
Step 3, upper and lower level basis material is bonded, as shown in figure 11
3a. is staggered relatively in ultra-high vacuum environment by the first Si piece and the 2nd Si piece, and pressure control is 10-6Pa, temperature
Degree is increased to 400 DEG C, duration 1.5h, so that the 2nd Si piece upper surface is bonded with the oxide layer of the first Si piece；
3b. continues to increase temperature to 500 DEG C, duration 45min, so that a sector-meeting is broken at injection hydrogen, simultaneously
The extra Si of the first Si piece plane of disruption is removed, it can be in 1.2 μm or so of thin-layer silicon of the 2nd Si on piece reservation；
3c. continues to increase temperature to 1000 DEG C or so, and the duration is about 2min, and then anneal 2h, enhances the first Si piece
With the bond strength of the 2nd Si piece.
Step 4, a piece of novel SOI substrate is constituted, as shown in figure 12.
In ultra-high vacuum environment, (pressure is about 10 to 4a.-6) in, it is annealed to room temperature；
4b. polish to obtained SOI substrate smooth using CMP process, finally obtains a piece of SOI substrate.
Step 5, traditional SOI substrate is compared with the heat dissipation of novel SOI substrate
1a. processes fully- depleted insulator by traditional CMOS technology on traditional SOI substrate and novel SOI substrate respectively
Upper silicon (FD-SOI) n-channel metal oxide semiconductor field effect tube (MOSFETs).Grid and the voltage of drain electrode be respectively 3V and
8V passes through the temperature of the direct measurement device of high-resolution infrared thermal microscopy during device work.The temperature knot measured
Fruit change rate curve is as shown in figure 17, and abscissa represents the distance between drain electrode and source electrode in figure, and ordinate represents on device
Temperature.Triangle indicates the temperature change of device on traditional SOI substrate, and square indicates the temperature of device in novel SOI substrate
Variation.
Embodiment 4：
A kind of preparation method of double-level-metal channel SOI substrate, steps are as follows：
Step 1, the preparation of SOI substrate basis material at the middle and upper levels, as shown in Fig. 8, Fig. 9, Figure 10.
1a. chooses the first Si piece, carries out injection hydrogen to the upper surface of the first Si piece, the depth of injection is 1.2 μm；
After 1b. has infused hydrogen, thermal oxide is carried out to the upper surface of the first Si piece, silicon wafer is placed in furnace chamber first, and handle
Furnace chamber is evacuated.Then, after exhausting vacuum, setting program is begun to warm up.After temperature reaches 1050 DEG C, it is quickly passed through one
The purity oxygen of atmospheric pressure.Then after leading to oxygen, 20h is kept, is being evacuated.Finally silicon wafer is saved in a vacuum, it is natural
Room temperature is dropped to by silicon chip extracting.Oxide layer with a thickness of 1 μm；
1c. polishes the oxidation layer surface of the first Si piece using CMP process, fixes the first Si piece first in rubbing head
Bottom, polishing pad is placed on abrasive disk.Then, when polishing, the rubbing head of rotation is pressed in the polishing of rotation
On pad.Then, lapping liquid is allowed to flow between silicon chip surface and polishing pad, lapping liquid can be evenly distributed on polishing pad.Then,
Chemical substance in lapping liquid can react with Si piece surfacing, convert insoluble substance to readily soluble substance.Then,
These chemical reactants are removed from Si piece surface by the micromechanics rubbing action of abrasive grain；
1d. uses photoetching, performs etching to the oxide layer of the first Si on piece, carries out gluing, bondline thickness to silicon wafer first
It is 1 μm, then the silicon wafer for being painted with glue is baked, 150 DEG C of temperature, time 2min.Using the ultraviolet light of wavelength 330nm to glue
Face is exposed, and silicon wafer and reticle are in close contact, and is developed with developer for negative photoresist to silicon wafer, time 5min, developer solution temperature
Degree is 40 DEG C, and silicon wafer is put into insulating box, and temperature is 190 DEG C, time 30min, and with infrared light irradiation 10min, apart from glue
Face 6cm corrodes silicon wafer using wet etching.Then, the remaining glue surface in silicon wafer is removed, finally silicon wafer is carried out clear
It washes, it is dry.Several channel regions etched, depth are 0.4 μm, 6 μm of width, 6 μm of channel spacing；
1e. is blocked with non-channel region of the cover material layer (such as resist) to the first Si piece oxide layer, using magnetic
Control sputtering, carries out sputtering certain metal to the channel region in the first Si piece oxide layer.Firstly, reaction chamber is made to reach vacuum condition,
General control pressure is 2 × 10-5torr.Then, it is passed through argon gas into reaction chamber, and opens DC power supply.Then argon gas can be sent out
Raw ionization generates argon ion and an electronics.Then, under the action of electric field, anode is flown in electrons acceleration, meanwhile, argon ion
The target of cathode, i.e. certain metal can be accelerated to fly to, so that target is knocked off the surface for reaching substrate, generate metallic film.It splashes
It after penetrating, is purged using excess metal of the CMP process to channel region non-in oxide layer, and has the channel of metal to sputtering
Surface carries out smooth.
Step 2, in SOI substrate underlying substrate material preparation, as shown in Figure 2, Figure 3, Figure 4.
2a. chooses the 2nd Si piece, carries out thermal oxide to the upper surface of the 2nd Si piece, oxide layer with a thickness of 1 μm；
2b. polishes the oxidation layer surface of the 2nd Si piece using CMP process, Si piece fixed first rubbing head most
In the following, polishing pad is placed on abrasive disk.Then, when polishing, the rubbing head of rotation is pressed on the polishing pad of rotation.
Then, lapping liquid is allowed to flow between silicon chip surface and polishing pad, lapping liquid can be evenly distributed on polishing pad.Then, it grinds
Chemical substance in liquid can react with Si piece surfacing, convert insoluble substance to readily soluble substance.Then, pass through
The micromechanics rubbing action of abrasive grain removes these chemical reactants from Si piece surface；
2c. uses photoetching, performs etching to the oxide layer of the first Si on piece, carries out gluing, bondline thickness to silicon wafer first
It is 1 μm, then the silicon wafer for being painted with glue is baked, 150 DEG C of temperature, time 2min.Using the ultraviolet light of wavelength 330nm to glue
Face is exposed, and silicon wafer and reticle are in close contact, and is developed with developer for negative photoresist to silicon wafer, time 5min, developer solution temperature
Degree is 40 DEG C, and silicon wafer is put into insulating box, and temperature is 190 DEG C, time 30min, and with infrared light irradiation 10min, apart from glue
Face 6cm corrodes silicon wafer using wet etching.Then, the remaining glue surface in silicon wafer is removed, finally silicon wafer is carried out clear
It washes, it is dry.Several channel regions etched, depth are 0.4 μm, 6 μm of width, 6 μm of channel spacing；
2d. uses magnetron sputtering, carries out sputtering certain metal to the channel region in the 2nd Si piece piece oxide layer.Sputtering finishes
Afterwards, be purged using excess metal of the CMP process to channel region non-in oxide layer, and to sputtering have the channel surface of metal into
Row is smooth.
Step 3, upper and lower level basis material is bonded, as shown in figure 13
3a. is staggered relatively in ultra-high vacuum environment by the first Si piece and the 2nd Si piece, and pressure control is 10-6Pa, temperature
Degree is increased to 600 DEG C, duration 2h, so that the oxide layer of the first Si piece is bonded with the oxide layer of the 2nd Si piece；
3b. continues to increase temperature to 500 DEG C, duration 45min, so that the first Si sector-meeting occurs to break at injection hydrogen
It splits, while removing the extra Si of the first Si piece plane of disruption, it can be in 1.2 μm or so of thin-layer silicon of the 2nd Si on piece reservation；
3c. continues to increase temperature to 1000 DEG C or so, and the duration is about 2min, and then anneal 2h, so that the first Si piece
Enhance with the binding ability of the 2nd Si piece.
Step 4, a piece of novel SOI substrate is constituted, as shown in figure 14.
In ultra-high vacuum environment, (pressure is about 10 to 4a.-6Pa in), it is annealed to room temperature；
4b. polish to obtained SOI substrate smooth using CMP process, finally obtains a piece of SOI substrate.
Step 5, traditional SOI substrate is compared with the heat dissipation of novel SOI substrate
1a. processes fully- depleted insulator by traditional CMOS technology on traditional SOI substrate and novel SOI substrate respectively
Upper silicon (FD-SOI) n-channel metal oxide semiconductor field effect tube (MOSFETs).Grid and the voltage of drain electrode be respectively 3V and
8V passes through the temperature of the direct measurement device of high-resolution infrared thermal microscopy during device work.The temperature knot measured
Fruit change rate curve is as shown in figure 18, and abscissa represents the distance between drain electrode and source electrode in figure, and ordinate represents on device
Temperature.Triangle indicates the temperature change of device on traditional SOI substrate, and square indicates the temperature of device in novel SOI substrate
Variation.
Claims (10)
1. a kind of structure of SOI substrate, which is characterized in that including：First Si piece and the 2nd Si piece, using thermal oxidation method to first
Si piece upper surface is aoxidized, and certain thickness oxide layer is obtained, and is performed etching to the oxide layer, several channels are etched
Area, to channel region splash-proofing sputtering metal；Hydrogen ion is injected to the 2nd Si piece, obtains the Si piece that hydrogen ion is distributed at certain depth, the
Two Si pieces are located at the upper surface of the first Si piece, and the first Si piece oxide layer and the 2nd Si piece injection hydrogen ion surface are bonded, subtracted
The thickness of thin the 2nd Si piece of top layer forms SOI substrate to 0.05~0.3 μm.
2. the structure of SOI substrate as described in claim 1, which is characterized in that oxidated layer thickness is 0.2~1.2 μm.
3. the structure of SOI substrate as described in claim 1, it is characterised in that：Channel region depth, width and channel spacing foundation
Depending on needing.
4. the structure of SOI substrate as described in claim 1, it is characterised in that：Channel region cross sectional shape can be rectangle, triangle
One or more of shape, trapezoidal, parallelogram.
5. the structure of SOI substrate as described in claim 1, it is characterised in that：The metal of sputtering is chromium (Cr), tungsten (W), molybdenum
(Mo), the mixture of platinum (Pt), titanium (Ti), tantalum (Ta) and its they and other metals, the thermal expansion system of final metal alloy
Number is close with buried oxide layer.
6. the structure of SOI substrate as described in claim 1, it is characterised in that：Injecting hydrionic depth to the 2nd Si piece is
0.05~0.3 μm.
7. the structure of SOI substrate as described in claim 1, it is characterised in that：It can also be using thermal oxidation method to the 2nd Si piece
Aoxidized, obtain certain thickness oxide layer, the oxide layer is performed etching, form several channels, at the same to channel into
Row splash-proofing sputtering metal.The oxide layer of first Si piece is bonded with the oxide layer of the 2nd Si piece, obtains the substrate of dual oxide layer.
8. a kind of preparation method of SOI substrate structure, which is characterized in that including：
First Si piece and the 2nd Si piece are provided, thermal oxide is carried out to the first Si piece upper surface, oxidated layer thickness is 0.1~1.2 μm；
First Si piece oxide layer is polished；
The oxide layer of the first Si piece is performed etching, several channel regions are etched, depth is 0.2~0.5 μm, width
0.2~8 μm, 0.2~8 μm of channel spacing；
To channel region splash-proofing sputtering metal, finally the excess metal layer of channel region non-in oxide layer is purged；
Using the first Si piece a as underlying substrate material；
Hydrogen is injected in the 2nd Si piece, the depth of injection is 0.05~0.3 μm, as upper layer basis material；
The surface of 2nd Si piece injection hydrogen is bonded with the oxidation layer surface of the first Si piece, specially：Divide three ranks
Duan Shenggao temperature, the temperature elevating range of first stage are 300~400 DEG C, 2~3h of duration, realize the first Si piece and the 2nd Si
The bonding of piece；The temperature elevating range of second stage is 450~650 DEG C, 30~45min of duration, so that top layer silicon is thinned to thickness
Degree is 0.1~0.3 μm, and the temperature elevating range of phase III is 950~1050 DEG C, and the duration is about 2min, to enhance the first Si
The bond strength of piece and the 2nd Si piece；
In ultra-high vacuum environment, it is annealed to room temperature, takes out SOI substrate.
9. the preparation method of SOI substrate structure as claimed in claim 8, which is characterized in that channel region cross sectional shape can be
One or more of rectangle, triangle, trapezoidal, parallelogram.
10. the preparation method of SOI substrate structure as claimed in claim 9, which is characterized in that the technique that splash-proofing sputtering metal uses for
One of d.c. sputtering, radio-frequency sputtering, reactive sputtering, magnetron sputtering, collimated sputtering, splash-proofing sputtering metal be chromium (Cr), tungsten (W),
Molybdenum (Mo), platinum (Pt), titanium (Ti), tantalum (Ta) and its they and other metals mixture, the thermal expansion of final metal alloy
Coefficient is close with buried oxide layer.
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| KR20070076850A (en) * | 2006-01-20 | 2007-07-25 | 삼성전자주식회사 | Soi substrate and method for forming the same |
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