CN108572926B - Method and device for synchronizing caches of central processing units - Google Patents

Method and device for synchronizing caches of central processing units Download PDF

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CN108572926B
CN108572926B CN201710147292.5A CN201710147292A CN108572926B CN 108572926 B CN108572926 B CN 108572926B CN 201710147292 A CN201710147292 A CN 201710147292A CN 108572926 B CN108572926 B CN 108572926B
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central processing
processing unit
cache
memory
data
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CN108572926A (en
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张扬
罗犇
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Alibaba Cloud Computing Ltd
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Alibaba Group Holding Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

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Abstract

The invention discloses a method for synchronizing caches of central processing units, which comprises the following steps: determining a source central processing unit and a target central processing unit; and synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the destination central processing unit. The data in the cache of the central processing unit can be directly copied and synchronized to the corresponding areas of the caches of other central processing units, so that when the program runs, other central processing units can directly access the data from the local cache, the overhead is effectively reduced, and the running efficiency of the program is improved.

Description

Method and device for synchronizing caches of central processing units
Technical Field
The invention relates to a cache synchronization method for a central processing unit.
Background
An architecture that employs multiple physical Central Processing Units (CPUs) on one machine is becoming more common in the server field (referred to as NUMA architecture in the industry), each CPU has its own cache resource, and each CPU accesses its own cache much faster than other CPUs, but this part of cache can only be accessed by the CPU and may not be visible to other CPUs.
If an application is running on the CPU0 but the data to be accessed is currently within the cache of the CPU1, the existing approach is for the CPU to maintain synchronization between the cache and the memory (memory) through a mechanism called snoop.
When the CPU0 needs to access a piece of data, it triggers a snoop way to ascertain where the most recent data is. For example, when the latest data is located in the cache of another CPU1, it is necessary that the CPU1 synchronize the cache to the memory first, and then the CPU0 reads the memory to the cache, which is started when the CPU0 initiates an access request, so that the overhead caused by the entire access to the CPU0 is reflected in the execution delay of the process that initiates the request on the CPU 0.
The snoop method is a passive method, and when data stored by a non-local cache needs to be accessed, in addition to the cost of the snoop itself, once the latest data is ascertained to be in caches of other CPUs, additional data synchronization cost also needs to be introduced.
Therefore, the existing method for accessing the data of the caches of different CPUs has the problems of high cost and low operation efficiency.
Disclosure of Invention
The invention provides a method for synchronizing caches of central processing units, which comprises the following steps:
determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
Optionally, before determining the operation of the source central processing unit and the destination central processing unit, the method further includes:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
and if so, executing subsequent operation.
Optionally, the determining whether the condition for performing synchronization between caches belonging to the central processing unit is satisfied includes:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the condition of synchronization between caches of the central processing unit is satisfied.
Optionally, the determining whether the condition for performing synchronization between caches belonging to the central processing unit is satisfied includes:
judging whether an instruction for synchronizing the designated cache region to which the central processing unit belongs is acquired, wherein the instruction designates the designated regions of the target central processing unit and the memory;
and if the synchronization request is acquired, the synchronization condition among caches of the central processing unit is met.
Optionally, the determining the source central processor and the destination central processor includes:
taking the central processing unit with the updated cache region of the central processing unit corresponding to the designated region of the memory as a source central processing unit;
and determining a destination central processing unit.
Optionally, before the operation of synchronizing the data in the designated cache region of the source central processing unit to the corresponding cache region of the destination central processing unit, the method further includes:
and executing the operation corresponding to the write-back or write-through mark.
Optionally, the determining the source central processor and the destination central processor includes:
determining a source central processing unit by utilizing a synchronous memory and a cache module to which the central processing unit belongs;
and determining a destination central processing unit.
Optionally, the determining the source central processor and the destination central processor includes:
determining a source processor;
searching a relevant central processing unit corresponding to the specified area of the memory;
and taking other central processing units except the source central processing unit in the associated central processing unit as target central processing units.
Optionally, the synchronizing the data of the cache region designated by the source central processing unit to the corresponding cache region belonging to the destination central processing unit includes:
and directly synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by utilizing the synchronous memory and the cache module of the central processing unit without passing through the memory.
Optionally, before the module that utilizes the synchronous memory and the cache to which the central processing unit belongs directly synchronizes the data of the cache region to which the source central processing unit belongs to the corresponding cache region to which the destination central processing unit belongs, without using the memory, the method further includes:
and judging whether the modules of the synchronous memory and the cache of the central processing unit are idle or not.
Optionally, the modules of the synchronous memory and the central processing unit cache are deployed in: within the central processor or separately deployed from the central processor.
Optionally, the synchronizing the data of the cache region designated by the source central processing unit to the corresponding cache region belonging to the destination central processing unit includes:
and synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by using fast channel connection.
The invention also provides a method for triggering the cache of the synchronous central processing unit, which comprises the following steps:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, triggering the operation of the cache of the synchronous central processing unit.
Optionally, before the triggering the operation of synchronizing the caches of the central processing unit, the method further includes:
and executing the operation corresponding to the write-back or write-through mark.
The invention also provides a method for starting the cache of the synchronous central processing unit, which comprises the following steps:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and sending the instruction to start the cache of the synchronous central processing unit.
The invention also provides a method for operating the memory, which comprises the following steps:
setting the mark of the designated area of the memory as synchronization;
and according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs.
The invention also provides a device for synchronizing the caches of the central processing units, which comprises:
the determining unit is used for determining a source central processing unit and a destination central processing unit;
and the synchronization unit is used for synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the destination central processing unit.
Optionally, the method further comprises:
and the judging unit is used for judging whether the conditions for carrying out the synchronization between the caches of the central processing unit are met.
Optionally, the determining unit includes:
the first judgment subunit is configured to judge whether data of a cache area to which the central processing unit belongs, which corresponds to the specified area of the memory, is updated;
a mark judgment subunit, configured to, if updated, judge whether the mark of the designated area of the memory includes a synchronization mark and at least one of the following marks: write back flag or write through flag;
the device comprises a subunit, which is used for meeting the condition of synchronization between caches belonging to a central processing unit if the subunit is included.
Optionally, the determining unit includes:
the second judgment subunit is used for judging whether an instruction for synchronizing the specified cache region to which the central processing unit belongs is acquired, wherein the instruction specifies the specified regions of the target central processing unit and the memory;
and the acquisition subunit is used for meeting the condition of carrying out synchronization among caches belonging to the central processing unit if the acquisition subunit is acquired.
Optionally, the determining unit includes:
the source determining subunit is used for taking the updated central processing unit, which belongs to the cache region of the central processing unit corresponding to the specified region of the memory, as a source central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
Optionally, the method further comprises:
and the corresponding operation execution unit is used for executing the operation corresponding to the write-back or write-through mark.
Optionally, the determining unit includes:
the source determination second subunit is used for determining a source central processing unit by utilizing the synchronous memory and the cache module of the central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
Optionally, the determining unit includes:
a source determining subunit for determining a source processor;
the searching subunit is used for searching the associated central processing unit corresponding to the designated area of the memory;
and the sub-unit is used for taking other central processing units except the source central processing unit in the associated central processing unit as the target central processing unit.
Optionally, the synchronization unit is specifically configured to:
and directly synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by utilizing the synchronous memory and the cache module of the central processing unit without passing through the memory.
Optionally, the method further comprises:
and the idle judging unit is used for judging whether the modules of the synchronous memory and the cache of the central processing unit are idle or not.
The invention also provides a device for triggering the cache of the synchronous central processing unit, which comprises:
the judging unit is used for judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
a mark judgment unit, configured to, if updated, judge whether a mark of the designated area of the memory includes a synchronization mark and at least one of the following marks: write back flag or write through flag;
and the triggering unit is used for triggering the operation of the cache of the synchronous central processing unit if the cache is included.
Optionally, the method further comprises:
and the execution unit is used for executing the operation corresponding to the write-back or write-through mark.
The invention also provides a device for starting the cache of the synchronous central processing unit, which comprises:
the generating unit is used for generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and the sending unit is used for sending the instruction to start the cache of the synchronous central processing unit.
The present invention also provides a device for operating a memory, comprising:
the setting unit is used for setting the mark of the designated area of the memory to be synchronous;
and the synchronization unit is used for synchronizing the corresponding region of the cache to which the central processing unit belongs according to the mark.
The present invention also provides a machine-readable storage medium storing or carrying instructions for synchronizing caches of central processing units, the instructions when executed result in the following:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
The present invention also provides a machine-readable storage medium storing or carrying instructions for triggering a cache to which a synchronous central processing unit belongs, the instructions, when executed, causing the following operations:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache of the synchronous central processing unit is carried out.
The present invention also provides a machine-readable storage medium storing or carrying instructions for starting a cache to which a synchronous central processing unit belongs, the instructions, when executed, causing the following operations:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and sending the instruction to start the cache of the synchronous central processing unit.
The present invention also provides a machine-readable storage medium storing or carrying instructions for operating a memory, the instructions when executed result in the following operations:
setting the mark of the designated area of the memory as synchronization;
and according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs.
The present invention also provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for synchronizing a cache of a central processing unit, and after the device is powered on and the processor runs the program for implementing the method for synchronizing the cache of the central processing unit, the device executes the following operations:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
The present invention also provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for triggering a cache to which a synchronous central processing unit belongs, and after the device is powered on and the processor runs the program for implementing the method for triggering the cache to which the synchronous central processing unit belongs, the following operations are performed:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache of the synchronous central processing unit is carried out.
The present invention further provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for starting a cache to which a synchronous central processing unit belongs, and after the device is powered on and the processor runs the program for implementing the method for starting the cache to which the synchronous central processing unit belongs, the following operations are performed:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and sending the instruction to start the cache of the synchronous central processing unit.
The present invention also provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method of operating a memory, and after the device is powered on and the processor runs the program for implementing the method of operating the memory, the device executes the following operations:
setting the mark of the designated area of the memory as synchronization;
and according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs.
The invention also provides a cache operation access method for a multi-central processing unit architecture, which comprises the following steps: determining a source central processing unit and a target central processing unit of a multi-central processing unit architecture according to set conditions;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the target central processing unit operates and accesses the data of the region cached by the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
The invention also provides a device for cache operation access of a multi-central processing unit architecture, which comprises: the determining unit is used for determining a source central processing unit and a target central processing unit of the multi-central processing unit architecture according to set conditions;
the synchronization unit is used for synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the target central processing unit;
and the operation unit is used for the target central processing unit to operate and access the data of the region where the target central processing unit belongs to the cache.
Compared with the prior art, the method for synchronizing the caches of the central processing units has the advantages that data in the caches of the central processing units can be directly copied and synchronized to corresponding areas of caches of other central processing units, when a program runs, the other central processing units can directly access the data from the local caches, the expenditure is effectively reduced, and the running efficiency of the program is improved.
Compared with the prior art, the method for triggering the cache of the synchronous central processing unit has the advantages that the cache of the central processing unit is triggered to start to be synchronized by judging the memory mark. The function of the memory mark can be fully utilized, the realization is easy, and the efficiency is high.
Compared with the prior art, the method for starting the cache of the synchronous central processing unit has the advantages that the cache of the synchronous central processing unit is started in an instruction mode. And a flexible central processing unit cache synchronization mode can be provided for the program.
Compared with the prior art, the method for synchronizing the cache regions of the central processing unit has the advantages that flexible trigger conditions can be provided for cache synchronization of the central processing unit by marking the designated regions of the memory as synchronization and synchronizing the corresponding regions of the cache of the central processing unit according to the marks.
Compared with the prior art, the cache operation access method for the multi-central processing unit architecture has the advantages that caches of other central processing units can be synchronized to the local cache for operation access, and efficiency is improved.
Drawings
FIG. 1 is a diagram illustrating a method for synchronizing caches of central processing units according to a first embodiment of the present application;
FIG. 2 is a flowchart illustrating a method for synchronizing caches of central processing units according to a first embodiment of the present application;
FIG. 3 is a flowchart illustrating a method for triggering a cache to which a synchronous CPU belongs according to a second embodiment of the present application;
FIG. 4 is a flowchart illustrating a method for starting a cache to which a synchronous CPU belongs according to a third embodiment of the present application;
fig. 5 is a flowchart illustrating a method for operating a memory according to a fourth embodiment of the present disclosure;
fig. 6 is a block diagram illustrating an apparatus for synchronizing caches of central processing units according to a fifth embodiment of the present application;
fig. 7 is a block diagram illustrating an apparatus for triggering a cache to which a synchronous cpu belongs according to a sixth embodiment of the present application;
fig. 8 is a block diagram illustrating an apparatus for starting a cache to which a synchronous cpu belongs according to a seventh embodiment of the present application;
fig. 9 is a block diagram illustrating an apparatus for operating a memory according to an eighth embodiment of the present invention;
FIG. 10 is a flowchart illustrating a method for cache operation access in a multi-CPU architecture according to a seventeenth embodiment of the present application;
fig. 11 is a block diagram illustrating an apparatus for cache operation access in a multiple central processor architecture according to an eighteenth embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of implementation in many different ways than those herein set forth and of similar import by those skilled in the art without departing from the spirit of this application and is therefore not limited to the specific implementations disclosed below.
A first embodiment of the present application provides a method for synchronizing caches of central processing units, which is shown in fig. 1,
in a computer system having a plurality of central processing units, each of the central processing units (CPU0 and CPU1) has its own Cache (Cache), and DATA (DATA) used by an application program may exist in a designated Cache area (corresponding to the Cache to which CPU0 or CPU1 belongs) in addition to being stored in a Memory (Memory) so that the central processing units can process the DATA.
The designated cache region to which the central processing unit belongs is a cache region to which the central processing unit corresponding to the designated region of the memory belongs. The designated region of memory may be specified by an address of the memory. That is, the area in which the DATA (DATA) in the memory in the figure is located corresponds to the buffer areas of the CPU0 and the CPU1 that store the DATA. The region of memory is determined by an address of the memory.
After being processed by the CPU, the DATA may be updated to different values, for example, the DATA (DATA) in the memory in the figure is read into the cache of the CPU0, processed by TASK 0(TASK0) and updated to the latest value (DATA '), and when TASK 1(TASK1) of another CPU (e.g., CPU1) needs to access the latest value (DATA') of the DATA, a series of operations of searching for the position of the latest value (DATA ') of the DATA (in the cache of the CPU 0) and copying the latest value (DATA') to the corresponding cache region of the corresponding CPU (CPU1) needs to be started.
In addition to the location where the latest data needs to be searched in the memory and the caches of the CPUs, when the latest data exists in the caches of other CPUs (in the cache to which the CPU0 belongs in the figure), the existing method for copying the latest value of the data into the corresponding cache region of the corresponding CPU before the present application can only synchronize the latest value of the data from the cache of the CPU into the memory and then synchronize the latest value of the data from the memory into the cache of the CPU (CPU1) that needs to access the data.
Therefore, the existing method has the disadvantages of high time overhead, low speed and low efficiency.
The method provided by the embodiment of the application can copy the latest data to the cache of the central processing unit before the latest data is used by other central processing units. The flow chart is shown in fig. 2.
Before determining the operation of the source central processing unit and the destination central processing unit as shown in block 101, the current condition of the system may be determined first, and whether the condition for performing synchronization between caches belonging to the central processing units is satisfied is determined.
Specifically, the present embodiment provides the following two methods for determining whether the condition for performing synchronization between caches belonging to the central processing unit is satisfied:
in the first method, whether the condition for synchronizing caches of the central processing unit is met or not is judged by marking the designated area of the memory. Specifically, the following operations may be taken to determine:
firstly, whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated is judged. For example, the update condition of the data can be judged by using the modules of the synchronous memory and the cache of the central processing unit in the system.
The modules of the synchronous memory and the cache of the central processing unit monitor the cache of each central processing unit and the data in the memory, can obtain the updated information of the data and know the position of the latest data. The method is used for judging whether the data of the cache region of the central processing unit corresponding to the appointed region of the memory is updated easily and conveniently without extra development cost. For example, an Agent module of the multi-cpu system is a module that monitors cache data belonging to the cpu and synchronizes the cache and the memory belonging to the cpu in the snoop mechanism, and can use the Agent module to know whether data in the corresponding cache belonging to the cpu is updated.
After the data is updated, judging whether the mark of the designated area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag.
In a multi-CPU system, a Memory Type Register (MTRR for short) is composed of some Type registers (MSR registers), and attributes of different areas of a system Memory are marked to prompt Memory access behaviors of a CPU, such as whether caching (cache) is needed or not, whether the Memory needs to be immediately synchronized, and the like.
By setting the MTRR, one of the above tags can be marked on different areas of the system memory, and when the system starts the paging mode, a Page Table Entry (PTE for short) also has a corresponding tag. These tags are used to prompt the CPU for behavior after accessing the data.
The attribute flag of the memory region may include: UC (UnCacheable), WC (write combining), WP (write protected), WT (write through), WB (write Back), etc.
The tags of the memory by the PTE and the MTRR may be different, and when they are different, the mode with the most strict security to the data is selected, for example, the MTRR tag is WB, but when the PTE is WT, the CPU selects WT, that is, the data is written into the cache and simultaneously written into the memory.
In this embodiment, when one of the MTRR and the PTE marks a tag indicating synchronization (e.g., Remote Sync, RS for short) in the specified memory region, and the other one of the MTRR and the PTE marks WB or WT, it is considered that the condition for performing inter-cache synchronization to which the central processing unit belongs is satisfied. If one of MTRR or PTE marks the area appointed by the memory as one of UC/WP/WC, the condition of synchronization between caches belonging to the central processing unit can not be met regardless of whether the other mark is a mark for representing synchronization.
For example, when the designated region of the memory in the MTRR is marked as RS and the designated region of the memory in the PTE is marked as WT, or when the designated region of the memory in the MTRR is marked as WB and the designated region of the memory in the PTE is marked as RS, it is considered that the condition for performing inter-cache synchronization to which the central processing unit belongs is satisfied.
And judging whether the synchronization condition among caches of the central processing unit is met or not by judging whether the instruction for starting the synchronization operation is acquired or not.
The application program or the software per se usually knows the behavior of the application program or the software per se more, and can accurately predict the access behavior of the application program or the software per se to the data.
An application or program that can run on multiple central processors knows which data is likely to be accessed by multiple central processors, when which central processor needs to access which data, and whether the data is likely to be present in the caches to which the other central processors belong.
The application or software may send an instruction to initiate a synchronization operation before the central processor needs to use data that may be stored in other central processor caches. The method of this embodiment determines whether the condition for performing synchronization between caches belonging to the central processing unit is satisfied by whether the instruction is acquired.
If the instruction is not obtained, the condition for carrying out synchronization between caches of the central processing unit is considered not to be met, and the waiting is continued and whether the instruction is obtained or not is judged; and if the instruction is acquired, determining that the condition for carrying out the synchronization between the caches of the central processing unit is met.
The two methods can be combined to judge whether the conditions for carrying out the synchronization between the caches of the central processing unit are met. If one of the methods determines that the condition for performing the synchronization between the caches belonging to the central processing unit is satisfied, the current system is considered to satisfy the condition for performing the synchronization between the caches belonging to the central processing unit. Or when the two methods both obtain the condition of synchronization between the caches of the central processing unit, the system is considered to currently satisfy the condition of synchronization between the caches of the central processing unit. The specific situation may be determined according to the application scenario.
The two methods can provide flexible judgment whether the conditions for carrying out the synchronization between the caches of the central processing unit are met. Configuration and invocation are facilitated.
And when the current state of the system is judged to meet the condition of carrying out synchronization between caches of the central processing unit, determining a ground source central processing unit and a target central processing unit which correspond to the synchronous operation. The efficiency of subsequent operation can be higher by judging whether the current state meets the condition of carrying out the synchronization between the caches of the central processing unit before the subsequent operation.
Block 101, a source central processor and a destination central processor are determined.
There are various ways to determine the source cpu, and the present embodiment provides the following two ways to determine the source cpu:
in the foregoing, in the case where the condition that the synchronization between the caches of the central processing units is satisfied is determined by the first method, the central processing unit whose cache region of the central processing unit corresponding to the specified region of the memory is updated may be used as the source central processing unit.
For the case that the condition for performing synchronization between caches belonging to the central processing unit is determined to be satisfied by the method two, the source central processing unit may be determined by using the module of the synchronous memory and the cache belonging to the central processing unit in the method one: and taking the central processing unit with the latest data in the cache corresponding to the data in the designated area of the memory as a source central processing unit.
The module (such as an Agent module) of the cache to which the synchronous memory and the central processing unit belong can obtain the updated information of the data and know the position of the latest data, so that the source central processing unit can be conveniently and quickly determined by using the module.
For example, for the case that the condition for synchronizing the caches belonging to the central processing units is met by judging whether the instruction for synchronizing the specified cache regions belonging to the central processing units is obtained or not by adopting the second method, the identification of the target central processing unit is specified in the instruction, and accordingly, the central processing unit of the woodware can be determined.
In addition, for the case where the destination central processing unit has not been determined, the present embodiment also provides the following manner to determine the destination central processing unit: and searching the associated central processing unit corresponding to the specified area of the memory.
Specifically, the MSR register may be configured to record a base address of a segment of memory, where the segment of memory corresponds to a corresponding table of a memory-specified region and an associated central processing unit, and the content of each record is: the memory address and the identification of the associated central processing unit corresponding to the memory address.
The memory address corresponds to a designated area of the memory, and the associated central processing unit is a central processing unit which is likely to store data of the designated area of the memory or an updated value thereof.
And searching the corresponding table, wherein other central processing units except the source central processing unit in the associated central processing unit are used as target central processing units.
For example, if the memory address in the correspondence table is a, the memory address corresponds to the central processing unit 0, the central processing unit 1, the central processing unit 2 and the central processing unit 3, and the source central processing unit is the central processing unit 0, the central processing unit 1, the central processing unit 2 and the central processing unit 3 are used as the destination central processing unit.
By now being able to determine the source central processor and the destination central processor, the corresponding synchronization operations described in block 102 can be performed.
Before the synchronization operation described in block 102, for the case that the condition for performing inter-cache synchronization of the central processing unit is determined to be satisfied by the flag in the specified region of the memory, the operation corresponding to the corresponding write-back or write-through flag may also be performed.
For example, when the memory tags in the MTRR and the PTE are write-through (WT) and tag synchronization tags (e.g., RS), the corresponding operation of the WT is executed before the cache region to which the subsequent central processing unit belongs, and the data is written into the cache and also into the memory.
The operation can synchronize the memory and the cache of the corresponding central processing unit according to the meaning of the memory mark, and the synchronization between the subsequent caches of different central processing units is not influenced.
And 102, synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the destination central processing unit.
After determining the source central processing unit and the destination central processing unit corresponding to the synchronization operation, the synchronization operation may be performed, and specifically, the data in the cache region specified by the source central processing unit may be directly synchronized to the corresponding cache region belonging to the destination central processing unit without using the aforementioned synchronous memory and the cache module (e.g., Agent) to which the central processing unit belongs. The designated cache region to which the central processing unit belongs is a cache region corresponding to the designated memory region.
The module of the synchronous memory and the cache of the central processing unit can synchronize the data in the memory with the corresponding data in the cache of the central processing unit, and the data can be conveniently and quickly synchronized between the caches of different central processing units by utilizing the module.
Before the modules of the synchronous memory and the cache of the central processing unit are used for carrying out the memorability and the synchronization operation, whether the state is idle can be judged, and the corresponding synchronization is carried out by using the synchronous memory and the cache of the central processing unit only when the state is idle. Therefore, the read-write performance of the memory can not be influenced.
The modules of the synchronous memory and the cache of the central processing unit can be deployed in the central processing unit (for example, each central processing unit is deployed or only one central processing unit is deployed), or can be deployed outside the central processing unit to work as independent modules.
The synchronization operation in this block may also be to synchronize the data in the cache region designated by the source central processing unit to the corresponding cache region belonging to the destination central processing unit by using a Quick Path Interconnect (QPI). Therefore, the data of the cache region appointed by the source central processing unit can be directly synchronized to the corresponding cache region of the target central processing unit without a memory.
A second embodiment of the present application provides a method for triggering a cache to which a synchronous central processing unit belongs, a flowchart of which is shown in fig. 3, and the method includes the following operations:
at block 201, it is determined whether the data in the cache area of the central processing unit corresponding to the specified area of the memory is updated.
Whether the data is updated or not can be known by monitoring the data of the memory designated area and the designated cache area to which the corresponding central processing unit belongs, the operation in this frame can utilize the modules of the synchronous memory and the cache to which the central processing unit belongs to obtain the updated information of the data, and the more detailed description can refer to the description related to the first embodiment of the present application, which is not described herein again.
If the flag is updated, block 202 determines whether the flag in the designated area of the memory includes a synchronization flag and at least one of the following flags: write back flag or write through flag.
After the updated data information is obtained, the tag of the specified area of the memory, such as MTRR and PTE, is determined, and for a more detailed description, reference may be made to the description related to the first embodiment of the present application, which is not described herein again.
If yes, block 203 triggers the operation of the cache to which the synchronous central processing unit belongs.
And when the marks of the designated area of the memory comprise a mark for representing synchronization and a write-back mark or a synchronization mark and a write-through mark, triggering the operation of the cache to which the synchronous central processing unit belongs.
When the tag of the designated area of the memory includes a tag indicating synchronization and a write-back tag or a synchronization tag and a write-through tag, before the cache to which the synchronization central processing unit belongs, an operation corresponding to the write-back or write-through tag may be executed. Thereby not affecting the system to memory operation.
A third embodiment of the present application provides a method for starting a cache to which a synchronous central processing unit belongs, a flowchart of which is shown in fig. 4, and the method includes the following operations:
at block 301, an instruction to start a cache to which a synchronous central processing unit belongs is generated, where the instruction includes an identifier of a destination central processing unit and an identifier of a designated area of a memory.
When the latest data in the cache region of the central processing unit corresponding to the memory designated region may need to be synchronized, an instruction is generated, and the instruction designates the central processing unit which needs to use the latest data and the designated region of the memory.
For example, the identification of the central processing unit and the address of the memory may be specified to specify the designated areas of the central processing unit and the memory.
For more detailed description, reference may be made to the description related to the first embodiment of the present application, which is not repeated herein.
Block 302, the instruction is sent to start the cache to which the synchronous central processing unit belongs.
And after the instruction is generated, the instruction is sent to a preset receiver for managing synchronization so as to start corresponding synchronization operation.
A fourth embodiment of the present application provides a method for operating a memory, a flowchart of which is shown in fig. 5, and the method includes the following operations:
at block 401, a flag of a designated region of memory is set to synchronous.
And marking the memory area as a preset mark for representing synchronization. For example, the flag of the memory in the MTRR or PTE may be set to RS, and the specified area of the memory may be specified by the address of the memory. For detailed description, reference may be made to the description related to the first embodiment of the present application, which is not repeated herein.
Block 402 synchronizes the corresponding region of the cache to which the central processor belongs based on the tag.
After the mark of the designated area of the memory is set to be synchronous, corresponding operation is carried out according to the mark when the synchronous operation of the cache of the central processing unit is possibly required.
A fifth embodiment of the present application provides an apparatus for synchronizing caches of central processing units, a block diagram of which is shown in fig. 6, and the apparatus includes:
a determining unit 501, configured to determine a source central processing unit and a destination central processing unit;
a synchronizing unit 502, configured to synchronize data of the cache region specified by the source central processing unit to a corresponding cache region belonging to the destination central processing unit.
Optionally, the apparatus for synchronizing caches of the central processing units further includes:
and the judging unit is used for judging whether the conditions for carrying out the synchronization between the caches of the central processing unit are met.
Alternatively, the judging unit may include:
the first judgment subunit is configured to judge whether data of a cache area to which the central processing unit belongs, which corresponds to the specified area of the memory, is updated;
a mark judgment subunit, configured to, if updated, judge whether the mark of the designated area of the memory includes a synchronization mark and at least one of the following marks: write back flag or write through flag;
the device comprises a subunit, which is used for meeting the condition of synchronization between caches belonging to a central processing unit if the subunit is included.
Optionally, the determining unit may also include:
the second judgment subunit is used for judging whether an instruction for synchronizing the specified cache region to which the central processing unit belongs is acquired, wherein the instruction specifies the specified regions of the target central processing unit and the memory;
and the acquisition subunit is used for meeting the condition of carrying out synchronization among caches belonging to the central processing unit if the acquisition subunit is acquired.
Optionally, the determining unit includes:
the source determining subunit is used for taking the updated central processing unit, which belongs to the cache region of the central processing unit corresponding to the specified region of the memory, as a source central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
Optionally, the apparatus may further include:
and the corresponding operation execution unit is used for executing the operation corresponding to the write-back or write-through mark.
Optionally, the determining unit may also include:
the source determination second subunit is used for determining a source central processing unit by utilizing the synchronous memory and the cache module of the central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
Optionally, the determining unit may also include:
a source determining subunit for determining a source processor;
the searching subunit is used for searching the associated central processing unit corresponding to the designated area of the memory;
and the sub-unit is used for taking other central processing units except the source central processing unit in the associated central processing unit as the target central processing unit.
Optionally, the synchronization unit may be specifically configured to:
and directly synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by utilizing the synchronous memory and the cache module of the central processing unit without passing through the memory.
Optionally, the apparatus may further include:
and the idle judging unit is used for judging whether the modules of the synchronous memory and the cache of the central processing unit are idle or not.
A sixth embodiment of the present application provides an apparatus for triggering a cache to which a synchronous central processing unit belongs, a block diagram of which is shown in fig. 7, and the apparatus is characterized by including:
a determining unit 601, configured to determine whether data of a cache region to which a central processing unit belongs, corresponding to a specified region of a memory, is updated;
a flag determining unit 602, configured to determine, if the flag in the designated area of the memory is updated, whether the flag in the designated area of the memory includes a synchronization flag and at least one of the following flags: write back flag or write through flag;
and a triggering unit 603, configured to trigger an operation of synchronizing the caches of the central processing units if the cache is included in the cache.
Optionally, the apparatus may further include an execution unit, configured to execute an operation corresponding to the write-back or write-through flag.
A seventh embodiment of the present application provides an apparatus for starting a cache to which a synchronous central processing unit belongs, a block diagram of which is shown in fig. 8, and the apparatus includes:
a generating unit 701, configured to generate an instruction for starting a cache to which a synchronous central processing unit belongs, where the instruction includes an identifier of a target central processing unit and an identifier of a designated area of a memory;
a sending unit 702, configured to send the instruction to start the cache to which the synchronous central processing unit belongs.
An eighth embodiment of the present application provides an apparatus for operating a memory, a block diagram of which is shown in fig. 9, including:
a setting unit 801, configured to set a flag of a designated area of a memory to be synchronous;
a synchronization unit 802, configured to synchronize, according to the flag, a corresponding area of the cache to which the central processing unit belongs.
A ninth embodiment of the present application provides a machine-readable storage medium, where the storage medium stores or carries instructions for synchronizing caches of central processing units, and the instructions, when executed, cause the following operations:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
A tenth embodiment of the present application provides a machine-readable storage medium, where the storage medium stores or carries an instruction for triggering a cache to which a synchronous central processing unit belongs, and the instruction, when executed, causes the following operations:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache of the synchronous central processing unit is carried out.
An eleventh embodiment of the present application provides a machine-readable storage medium, where the storage medium stores or carries instructions for starting a cache to which a synchronous central processing unit belongs, and the instructions, when executed, cause the following operations:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and sending the instruction to start the cache of the synchronous central processing unit.
A twelfth embodiment of the present application provides a machine-readable storage medium storing or carrying instructions for operating a memory, the instructions being executable to cause the following:
setting the mark of the designated area of the memory as synchronization;
and according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs.
A thirteenth embodiment of the present application provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for synchronizing caches of central processing units, and after the device is powered on and the processor runs the program for implementing the method for synchronizing the caches of the central processing units, the device executes the following operations:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
A fourteenth embodiment of the present application provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for triggering a cache to which a central processing unit belongs, and after the device is powered on and the processor runs the program for implementing the method for triggering the cache to which the central processing unit belongs, the following operations are performed:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache of the synchronous central processing unit is carried out.
A fifteenth embodiment of the present application provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for starting a cache to which a synchronous central processing unit belongs, and after the device is powered on and the processor runs the program for implementing the method for starting the cache to which the synchronous central processing unit belongs, the following operations are performed:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory;
and sending the instruction to start the cache of the synchronous central processing unit.
A sixteenth embodiment of the present application provides an electronic device, including a storage medium and a processor, where the storage medium stores or carries a program for implementing a method for operating a memory, and after the device is powered on and the processor runs the program for implementing the method for operating the memory, the device executes the following operations:
setting the mark of the designated area of the memory as synchronization;
and according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs.
A seventeenth embodiment of the present application provides a method for accessing a cache operation of a multi-cpu architecture, a flowchart of which is shown in fig. 10, and the method includes the following operations:
block 1001, a source cpu and a destination cpu of a multi-cpu architecture are determined based on set conditions.
The set conditions include selection conditions for the source central processing unit, selection conditions for the target central processing unit, conditions for executing the method and the like, such as whether time meets the time requirement for executing the method or whether the system software and hardware states meet the requirement for executing the method. For a detailed description of the operation, reference may be made to the detailed description in the first embodiment of the present application, which is not repeated herein.
At block 1002, the data of the cache region designated by the source central processor is synchronized to the corresponding cache region to which the destination central processor belongs.
For a detailed description of the operation, reference may be made to the detailed description in the first embodiment of the present application, which is not repeated herein.
At block 1003, the destination central processing unit operates and accesses the cached data of the region to which the destination central processing unit belongs.
After the data in the cached area of the destination central processing unit is updated, the destination central processing unit may perform operations such as reading and writing on the data in the cached area.
An eighteenth embodiment of the present application provides an apparatus for cache operation access in a multiple central processing unit architecture, a block diagram of which is shown in fig. 11, and includes:
a determining unit 1101, configured to determine a source central processing unit and a destination central processing unit of the multi-central processing unit architecture according to a set condition.
A synchronizing unit 1102, configured to synchronize data of the cache region specified by the source central processing unit to a corresponding cache region to which the destination central processing unit belongs.
An operation unit 1103, configured to operate and access the data of the region cached by the destination central processing unit.
Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto, and variations and modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

Claims (40)

1. A method for synchronizing caches of a central processing unit, comprising:
the updating condition of the data is obtained by utilizing the synchronous memory and the cache module of the central processing unit to judge whether to carry out data synchronization;
if yes, determining a source central processing unit and a destination central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
2. The method of claim 1, wherein said determining the operation of the source central processor and the destination central processor further comprises:
judging whether the conditions for carrying out synchronization among caches of the central processing unit are met or not;
and if so, executing subsequent operation.
3. The method according to claim 2, wherein said determining whether the condition for performing the inter-cache synchronization of the central processing unit is satisfied comprises:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the condition of synchronization between caches of the central processing unit is satisfied.
4. The method according to claim 2, wherein said determining whether the condition for performing the inter-cache synchronization of the central processing unit is satisfied comprises:
judging whether an instruction for synchronizing the designated cache region to which the central processing unit belongs is acquired, wherein the instruction designates the designated regions of the target central processing unit and the memory;
and if the synchronization request is acquired, the synchronization condition among caches of the central processing unit is met.
5. The method of claim 3, wherein said determining a source central processor and a destination central processor comprises:
taking the central processing unit with the updated cache region of the central processing unit corresponding to the designated region of the memory as a source central processing unit;
and determining a destination central processing unit.
6. The method of claim 3, wherein before the operation of synchronizing the data of the designated cache region of the source central processor to the corresponding cache region of the destination central processor, the method further comprises:
and executing the operation corresponding to the write-back or write-through mark.
7. The method of claim 1, wherein said determining a source central processor and a destination central processor comprises:
determining a source central processing unit by utilizing a synchronous memory and a cache module to which the central processing unit belongs;
and determining a destination central processing unit.
8. The method of claim 1, wherein said determining a source central processor and a destination central processor comprises:
determining a source processor;
searching a relevant central processing unit corresponding to the specified area of the memory;
and taking other central processing units except the source central processing unit in the associated central processing unit as target central processing units.
9. The method according to claim 1, wherein the synchronizing the data of the designated cache region to which the source central processor belongs to the corresponding cache region to which the destination central processor belongs comprises:
and directly synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by utilizing the synchronous memory and the cache module of the central processing unit without passing through the memory.
10. The method according to claim 9, wherein before the operation of directly synchronizing the data in the cache region designated by the source cpu to the corresponding cache region of the destination cpu, the module using the synchronized memory and the cache of the cpu does not use the memory, the method further comprises:
and judging whether the modules of the synchronous memory and the cache of the central processing unit are idle or not.
11. The method according to claim 9, wherein the modules for synchronizing the caches of the cpus are deployed in: within the central processor or separately deployed from the central processor.
12. The method according to claim 1, wherein the synchronizing the data of the designated cache region to which the source central processor belongs to the corresponding cache region to which the destination central processor belongs comprises:
and synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by using fast channel connection.
13. A method for triggering a cache to which a synchronous central processing unit belongs, comprising:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not, including: judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not by utilizing the synchronous memory and the cache module of the central processing unit;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, triggering the operation of the cache to which the synchronous central processing unit belongs; wherein, the cache to which the synchronous central processing unit belongs comprises: and synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the destination central processing unit.
14. The method according to claim 13, wherein before the triggering the operation of synchronizing the caches of the central processors, the method further comprises:
and executing the operation corresponding to the write-back or write-through mark.
15. A method for starting a cache to which a synchronous central processing unit belongs, comprising:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory; wherein, the cache to which the synchronous central processing unit belongs comprises: synchronizing data of a cache region assigned by a source central processing unit to a corresponding cache region belonging to a target central processing unit;
sending the instruction to start the cache of the synchronous central processing unit;
before the target central processing unit is determined, the updating condition of the data is obtained by utilizing a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
16. A method of operating a memory, comprising:
setting the mark of the designated area of the memory as synchronization;
according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs; wherein, the corresponding region of the cache to which the synchronous central processing unit belongs comprises: synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
before determining the target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
17. An apparatus for synchronizing caches of central processing units, comprising:
the determining unit is used for determining a source central processing unit and a destination central processing unit;
the synchronization unit is used for synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the target central processing unit;
before determining a source central processing unit and a target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module to which the central processing unit belongs to judge whether data synchronization is carried out or not; if yes, the determining unit determines a source central processing unit and a destination central processing unit.
18. The apparatus of claim 17, further comprising:
and the judging unit is used for judging whether the conditions for carrying out the synchronization between the caches of the central processing unit are met.
19. The apparatus according to claim 18, wherein said determining unit comprises:
the first judgment subunit is configured to judge whether data of a cache area to which the central processing unit belongs, which corresponds to the specified area of the memory, is updated;
a mark judgment subunit, configured to, if updated, judge whether the mark of the designated area of the memory includes a synchronization mark and at least one of the following marks: write back flag or write through flag;
the device comprises a subunit, which is used for meeting the condition of synchronization between caches belonging to a central processing unit if the subunit is included.
20. The apparatus according to claim 18, wherein said determining unit comprises:
the second judgment subunit is used for judging whether an instruction for synchronizing the specified cache region to which the central processing unit belongs is acquired, wherein the instruction specifies the specified regions of the target central processing unit and the memory;
and the acquisition subunit is used for meeting the condition of carrying out synchronization among caches belonging to the central processing unit if the acquisition subunit is acquired.
21. The apparatus according to claim 19, wherein said determining unit comprises:
the source determining subunit is used for taking the updated central processing unit, which belongs to the cache region of the central processing unit corresponding to the specified region of the memory, as a source central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
22. The apparatus of claim 19, further comprising:
and the corresponding operation execution unit is used for executing the operation corresponding to the write-back or write-through mark.
23. The apparatus of claim 17, wherein said determining unit comprises:
the source determination second subunit is used for determining a source central processing unit by utilizing the synchronous memory and the cache module of the central processing unit;
and the destination determining subunit is used for determining the destination central processing unit.
24. The apparatus of claim 17, wherein said determining unit comprises:
a source determining subunit for determining a source processor;
the searching subunit is used for searching the associated central processing unit corresponding to the designated area of the memory;
and the sub-unit is used for taking other central processing units except the source central processing unit in the associated central processing unit as the target central processing unit.
25. The apparatus according to claim 17, wherein the synchronization unit is specifically configured to:
and directly synchronizing the data of the cache region appointed by the source central processing unit to the corresponding cache region of the target central processing unit by utilizing the synchronous memory and the cache module of the central processing unit without passing through the memory.
26. The apparatus of claim 25, further comprising:
and the idle judging unit is used for judging whether the modules of the synchronous memory and the cache of the central processing unit are idle or not.
27. An apparatus for triggering a cache to which a synchronous central processing unit belongs, comprising:
the judging unit is used for judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated; the determining unit is specifically configured to: judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not by utilizing the synchronous memory and the cache module of the central processing unit;
a mark judgment unit, configured to, if updated, judge whether a mark of the designated area of the memory includes a synchronization mark and at least one of the following marks: write back flag or write through flag;
the triggering unit is used for triggering the operation of the cache of the synchronous central processing unit if the cache of the synchronous central processing unit is included; wherein, the cache to which the synchronous central processing unit belongs comprises: and synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the destination central processing unit.
28. The apparatus of claim 27, further comprising:
and the execution unit is used for executing the operation corresponding to the write-back or write-through mark.
29. An apparatus for starting a cache to which a synchronous central processing unit belongs, comprising:
the generating unit is used for generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory; wherein, the cache to which the synchronous central processing unit belongs comprises: synchronizing data of a cache region assigned by a source central processing unit to a corresponding cache region belonging to a target central processing unit;
the sending unit is used for sending the instruction to start the cache of the synchronous central processing unit;
before the target central processing unit is determined, the updating condition of the data is obtained by utilizing a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
30. An apparatus for operating a memory, comprising:
the setting unit is used for setting the mark of the designated area of the memory to be synchronous;
the synchronization unit is used for synchronizing the corresponding region of the cache to which the central processing unit belongs according to the mark; wherein, the corresponding region of the cache to which the synchronous central processing unit belongs comprises: synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
before determining the target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
31. A machine-readable storage medium storing or carrying instructions for synchronizing caches of central processing units, the instructions when executed resulting in the following:
judging whether the conditions for carrying out the synchronization between the caches of the central processing unit are met or not, comprising the following steps: obtaining the updating condition of the data by utilizing the synchronous memory and the cache module of the central processing unit to judge whether the data synchronization is carried out or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
32. A machine-readable storage medium storing or carrying instructions for triggering synchronization of a cache to which a central processing unit belongs, the instructions when executed resulting in the following:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not, including: judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not by utilizing the synchronous memory and the cache module of the central processing unit;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache to which the synchronous central processing unit belongs is carried out; wherein, the cache to which the synchronous central processing unit belongs comprises: and synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the destination central processing unit.
33. A machine-readable storage medium storing or carrying instructions for initiating a cache of a synchronous central processing unit, the instructions when executed result in the following:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory; wherein, the cache to which the synchronous central processing unit belongs comprises: synchronizing data of a cache region assigned by a source central processing unit to a corresponding cache region belonging to a target central processing unit;
sending the instruction to start the cache of the synchronous central processing unit;
before the target central processing unit is determined, the updating condition of the data is obtained by utilizing a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
34. A machine-readable storage medium storing or carrying instructions for operating a memory, the instructions when executed resulting in the following operations:
setting the mark of the designated area of the memory as synchronization;
according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs; wherein, the corresponding region of the cache to which the synchronous central processing unit belongs comprises: synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
before determining the target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
35. An electronic device comprising a storage medium and a processor, wherein the storage medium stores or carries a program for implementing a method for synchronizing caches of central processing units, and the device is powered on and executes the program for implementing the method for synchronizing the caches of the central processing units by the processor, and then performs the following operations:
judging whether the conditions for carrying out the synchronization between the caches of the central processing unit are met or not, comprising the following steps: obtaining the updating condition of the data by utilizing the synchronous memory and the cache module of the central processing unit to judge whether the data synchronization is carried out or not;
if yes, determining a source central processing unit and a target central processing unit;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
36. An electronic device, comprising a storage medium and a processor, wherein the storage medium stores or carries a program for implementing a method for triggering a cache to which a central processing unit belongs, and after the device is powered on and the program for implementing the method for triggering the cache to which the central processing unit belongs is executed by the processor, the following operations are performed:
judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not, including: judging whether the data of the cache region of the central processing unit corresponding to the designated region of the memory is updated or not by utilizing the synchronous memory and the cache module of the central processing unit;
if the mark is updated, judging whether the mark of the appointed area of the memory comprises a synchronous mark and at least one of the following marks: write back flag or write through flag;
if yes, the operation of the cache to which the synchronous central processing unit belongs is carried out; wherein, the cache to which the synchronous central processing unit belongs comprises: and synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the destination central processing unit.
37. An electronic device, comprising a storage medium and a processor, wherein the storage medium stores or carries a program for implementing a method for starting a cache to which a synchronous central processing unit belongs, and when the device is powered on and the processor runs the program for implementing the method for starting the cache to which the synchronous central processing unit belongs, the following operations are performed:
generating an instruction for starting the cache of the synchronous central processing unit, wherein the instruction comprises an identification of a target central processing unit and an identification of a designated area of a memory; wherein, the cache to which the synchronous central processing unit belongs comprises: synchronizing data of a cache region assigned by a source central processing unit to a corresponding cache region belonging to a target central processing unit;
sending the instruction to start the cache of the synchronous central processing unit;
before the target central processing unit is determined, the updating condition of the data is obtained by utilizing a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
38. An electronic device, comprising a storage medium and a processor, wherein the storage medium stores or carries a program for implementing a method for operating a memory, and after the device is powered on and the processor runs the program for implementing the method for operating the memory, the device executes the following operations:
setting the mark of the designated area of the memory as synchronization;
according to the mark, synchronizing the corresponding region of the cache to which the central processing unit belongs; wherein, the corresponding region of the cache to which the synchronous central processing unit belongs comprises: synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
before determining the target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module of the central processing unit so as to judge whether to carry out data synchronization; if yes, determining a target central processing unit.
39. A method for cache operation access for a multiple central processor architecture, comprising:
the updating condition of the data is obtained by utilizing the synchronous memory and the cache module of the central processing unit to judge whether to carry out data synchronization;
if yes, determining a source central processing unit and a destination central processing unit of the multi-central processing unit architecture according to set conditions;
synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region of the target central processing unit;
the target central processing unit operates and accesses the data of the region cached by the target central processing unit;
the designated cache region to which the central processing unit belongs comprises a cache region to which the central processing unit belongs corresponding to the designated region of the memory.
40. An apparatus for cache operation access for a multiple central processor architecture, comprising:
the determining unit is used for determining a source central processing unit and a target central processing unit of the multi-central processing unit architecture according to set conditions;
the synchronization unit is used for synchronizing the data of the cache region assigned by the source central processing unit to the corresponding cache region assigned by the target central processing unit;
the operation unit is used for the target central processing unit to operate and access the data of the region cached by the target central processing unit;
before determining a source central processing unit and a target central processing unit, updating conditions of data are obtained by using a synchronous memory and a cache module to which the central processing unit belongs to judge whether data synchronization is carried out or not; if yes, the determining unit determines the source central processing unit and the destination central processing unit of the multi-central processing unit architecture according to set conditions.
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