CN108352322B - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

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CN108352322B
CN108352322B CN201680043436.6A CN201680043436A CN108352322B CN 108352322 B CN108352322 B CN 108352322B CN 201680043436 A CN201680043436 A CN 201680043436A CN 108352322 B CN108352322 B CN 108352322B
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semiconductor device
semiconductor
exposed
manufacturing
layer
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CN108352322A (en
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小笠原淳
本间史浩
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Shindengen Electric Manufacturing Co Ltd
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Shindengen Electric Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

A method of manufacturing a semiconductor device, comprising: a dopant supply step of supplying an n-type dopant to a first exposed region exposed from the n-type semiconductor layer in an exposed surface where the pn junction is exposed; a channel stopper forming step of forming a channel stopper to a first depth by introducing an n-type dopant into the n-type semiconductor layer by laser irradiation of the first exposed region; and an oxide film forming step of forming an oxide film so as to cover the exposed surface on which the trench stopper is formed and to expand the region of the trench stopper to a second depth deeper than the first depth.

Description

Method for manufacturing semiconductor device and semiconductor device
Technical Field
The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.
Background
Conventionally, a method of forming a Channel stopper (Channel stopper) for increasing the withstand voltage of a semiconductor device is generally known as follows: a Laser (Laser) is irradiated onto the bottom surface of the trench in a state where the dopant of the first conductivity type is supplied in advance, so that the dopant of the first conductivity type is introduced into the first semiconductor layer (see patent document 1). In the manufacturing method of patent document 1, since the channel stopper can be formed by laser scanning, a Mask (Mask) forming step is not required.
[ Prior Art document ]
[ patent document 1 ] Japanese patent application laid-open No. 2007-311655
In recent years, however, there has been an increasing demand for semiconductor devices in the market, such as those capable of ensuring normal operation even in a higher temperature environment. That is, the market demands a semiconductor device with higher reliability.
In view of the above problems, an object of the present invention is to provide: a method for manufacturing a semiconductor device and a semiconductor device capable of manufacturing a highly reliable semiconductor device.
Disclosure of Invention
A method for manufacturing a semiconductor device according to an aspect of the present invention includes: a semiconductor substrate preparation step of preparing a semiconductor substrate having an exposed surface where a pn junction formed at a junction between a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type opposite to the first conductivity type is exposed; a dopant supply step of supplying a first conductive type dopant to the first exposed region of the exposed surface where the first semiconductor layer is exposed; a channel stopper forming step of forming a channel stopper to a first depth by introducing the first conductive type dopant into the first semiconductor layer by laser irradiation of the first exposed region; and an oxide film forming step of forming an oxide film so as to cover the exposed surface on which the trench stopper is formed and to expand a region of the trench stopper to a second depth deeper than the first depth.
A semiconductor device according to an aspect of the present invention is manufactured by the above method for manufacturing a semiconductor device, including: a semiconductor element having the exposed surface; the channel stopper formed on the first exposed region of the semiconductor element; and the oxide film formed to cover the exposed surface of the semiconductor element.
Effects of the invention
According to the present invention, the first conductivity type dopant is diffused in the first semiconductor layer by heat treatment in the oxide film forming process. That is, the region of the channel stopper can be enlarged in the first semiconductor layer. Thus, even in a higher temperature environment, the expansion of the depletion layer in the reverse bias applied state can be suppressed.
Thus, the semiconductor device after manufacture can suppress the generation of leakage current. Therefore, the semiconductor device can be operated normally. That is, a highly reliable semiconductor device can be provided.
Brief description of the drawings
Fig. 1 is a sectional configuration diagram of a semiconductor device according to a first embodiment.
Fig. 2 is an explanatory view of a method for manufacturing the semiconductor device according to the first embodiment.
Fig. 3 is an explanatory view of a method for manufacturing the semiconductor device according to the first embodiment.
Fig. 4 is a diagram illustrating a semiconductor substrate dividing process according to the first embodiment.
Fig. 5 is an explanatory view of a method for manufacturing a semiconductor device according to the second embodiment.
Fig. 6 is an explanatory view of a method for manufacturing a semiconductor device according to the second embodiment.
Fig. 7 is a graph showing the relationship between the depth direction of the exposed surface and the dopant concentration after the channel stopper ring formation step.
Fig. 8 is a graph showing the relationship between the depth direction of the exposed surface and the dopant concentration before and after the oxide film formation step.
Detailed Description
[ first embodiment ] to provide a liquid crystal display device
Hereinafter, a first embodiment of the present invention will be described with reference to fig. 1 to 4.
(constitution of semiconductor device)
The semiconductor device according to this embodiment is a Mesa (Mesa) type semiconductor device in which a channel stopper is arranged. Next, the structure of the semiconductor device according to the present embodiment will be described with reference to fig. 1.
As shown in fig. 1, a semiconductor device 100 according to the present embodiment includes: a semiconductor element 100 c; a channel stopper 124; and an oxide film 126. Wherein the semiconductor element 100c has N-A first semiconductor layer 110 of type (first conductivity type), and p arranged on one main surface side of the first semiconductor layer 110+And a second semiconductor layer 112 of type (second conductivity type).
The semiconductor element 100c further includes n arranged on the other main surface side of the first semiconductor layer 110+And a third semiconductor layer 114 of type (first conductivity type). The semiconductor device 100 further includes: a glass layer 128; an anode electrode 130 formed on the surface of the second semiconductor layer 112; and a cathode electrode 132 formed on the surface of the third semiconductor layer 114.
The semiconductor element 100c further has a junction 111 where a pn junction formed at a junction between the first semiconductor layer 110 and the second semiconductor layer 112 is exposed. The channel stopper 124 is formed on the first exposed region 111a of the exposed surface 111 where the first semiconductor layer 110 is exposed. The oxide film 126 is formed to cover the exposed surface 111. A glass layer 128 is formed to cover the oxide film 126.
As shown in fig. 2 and 3, the method for manufacturing a semiconductor device according to the present embodiment includes the following steps. Next, the respective steps will be explained in order.
(Process for producing semiconductor multilayer Structure)
As shown in fig. 2(a), the semiconductor multilayer structure fabrication process is a process for fabricating a semiconductor multilayer structure 100 a. The semiconductor stacked structure 100a includes: n is-A first semiconductor layer 110 of type (first conductivity type); p arranged on one main surface side of the first semiconductor layer 110+A second semiconductor layer 112 of type (second conductivity type); and n arranged on the other principal surface side of the first semiconductor layer 110+And a third semiconductor layer 114 of type (first conductivity type).
In the manufacturing process of the semiconductor multilayer structure, first, n is selected from-Type silicon substrate (n)-Type first semiconductor layer) 110 to form p by diffusion of p-type dopant from one main surface thereof+And a second semiconductor layer 112. And, by starting from n-The n-type dopant of the other main surface of the type silicon substrate 110 is diffused to form n+And a third semiconductor layer 114. Thus, n can be produced-The first semiconductor layer 110 and p+A semiconductor multilayer structure 100a having a pn junction parallel to the main surface is formed at the junction between the second semiconductor layers 112. Then, by thermal oxidation, at p+Type second semiconductor layer112, a surface oxide film 120 is formed. And, by thermal oxidation, at n+A surface oxide film 122 is formed on the surface of the type third semiconductor layer 114.
The dopant concentration of the first semiconductor layer 110 is, for example, 2 × 1014cm-3. The second semiconductor layer 112 has a dopant concentration of, for example, 2 × 1019cm-3. The dopant concentration of the third semiconductor layer 114 is, for example, 2 × 1019cm-3. The thickness of the first semiconductor layer 110 is, for example, 150 μm. The thickness of the second semiconductor layer 112 is, for example, 60 μm. The thickness of the third semiconductor layer 114 is, for example, 40 μm.
(semiconductor substrate preparation Process)
As shown in fig. 2(a) and (b), the semiconductor substrate preparation step is a semiconductor substrate 110b preparation step in which a trench 118 is formed from one main surface side of the semiconductor multilayer structure 100a, and an exposed surface 111 where a pn junction is exposed is prepared on an inner surface of the trench 118. Wherein the pn junction is formed at a junction between the first semiconductor layer 110 and the second semiconductor layer 112.
The trench 118 is formed, for example, by etching. First, the surface oxide film 120 on the second semiconductor layer 112 is etched. Then, the semiconductor laminated structure 100a is further etched from the second semiconductor layer 112 side. In this way, the trench 118 having a depth exceeding the pn junction can be formed from the one main surface of the semiconductor multilayer structure 100 a. At this time, an exposed surface 111 is formed on the inner surface of the groove 118. The exposed surface 111 includes a first exposed region 111a where the first semiconductor layer 110 is exposed and a second exposed region 111b where the second semiconductor layer 112 is exposed. As the etching solution, for example, hydrofluoric acid (HF) and nitric acid (HNO) are used3) And acetic acid (CH)3COOH) (for example, HF: HNO3：CH3COOH＝1:4:1)。
The width of the trench 118 is, for example, 300 μm, and the depth of the trench 118 is, for example, 90 μm.
(pretreatment step)
The pretreatment step is a step of subjecting the first exposed region 111a of the exposed surface 111, in which the first semiconductor layer 110 is exposed, to a hydrophobic treatment.
The hydrophobic treatment is performed by, for example, immersing the first exposed region 111a in a hydrophobic treatment solution. As the hydrophobic treatment solution, for example, hydrofluoric acid (HF) and nitric acid (HNO) can be preferably used3) The mixed solution of (1). And HF: HNO3More preferably, the ratio is 1: 25. The time for immersing the first exposed region 111a is preferably 1 to 3 minutes. The temperature for immersing the first exposed region 111a is preferably 20 to 30 ℃. After the immersion, the first exposed region 111a is cleaned with water, for example.
(dopant supplying step)
As shown in fig. 2(c), the dopant supply step is a step of supplying n-type dopant 10 to first exposed region 111 a.
The dopant supply process is performed by, for example, applying a liquid containing n-type dopant 10 to the first exposed region 111 a. As the liquid containing n-type dopant 10, for example, a liquid obtained by dissolving a phosphorus compound (e.g., pyrophosphoric acid) in an organic solvent (e.g., ethanol) can be preferably used. As a method of coating, a known method such as a dipping method, a spinning (Spinner) method, or a spraying method can be used.
The amount of n-type dopant 10 provided to the first exposed region 111a is adjusted to: in the channel stopper forming step described later, the dopant concentration of the channel stopper 124 (see fig. 3 a) formed in the first exposed region 111a is set to an optimum concentration (for example, 1 × 10)19cm-3)。
(channel stopper Ring formation Process)
As shown in fig. 3(a), the channel stopper forming step is a step of forming a channel stopper 124 by introducing n-type dopant 10 into the first semiconductor layer 110.
The n-type dopant 10 is introduced, for example, by laser irradiation of the first exposed region 111 a. A green laser having a wavelength of 532nm, for example, can be used. The laser is pulsed at a frequency of, for example, 30kHz with pulses and is scanned along the trench 118 at a speed of 300 mm/sec. In this step, the trench stopper 124 is formed to a predetermined depth (first depth).
In this process, a channel stopper 124 is formed along the trench 118. The channel stopper 124 may be only one. In the present embodiment, the two channel stopper rings 124, 124 are formed to be spaced apart from each other by 60 μm in the width direction of the trench 118.
After the laser irradiation is completed, the remaining n-type dopant 10 is removed. The removal of the dopants is for example performed by etching. For example, the same etching solution as used in the semiconductor substrate preparation step can be used.
(oxide film formation step)
As shown in fig. 3(b), the oxide film forming step is a step of forming an oxide film 126 so as to cover the exposed surface 111 after the channel stopper ring forming step and before the glass layer forming step described later.
The oxide film 126 is formed by, for example, a thermal oxidation method using dry oxygen. Thus, a silicon oxide film is formed on the inner surface of the trench 118.
The oxide film 126 is formed by, for example, introducing the semiconductor substrate 100b into a diffusion furnace and then treating the substrate while releasing oxygen. The treatment temperature is preferably 900 ℃ or higher. The time is preferably 90 minutes at a treatment temperature of 900 ℃.
The thickness of the oxide film 126 is preferably in the range of 5nm to 60nm, and the thickness is preferably 50 nm. If the thickness of the oxide film 126 is less than 5nm, the effect of reducing the reverse current may not be obtained. On the other hand, if the thickness of the oxide film 126 exceeds 60nm, the glass layer 128 may not be formed by the electrophoresis method in a glass layer forming step to be described later.
(glass layer Forming Process)
As shown in fig. 3 c, the glass layer forming step is a step of forming a glass layer 128 for Passivation (Passivation) so as to cover the exposed surface 111 with a glass composition.
In the glass layer forming step, first, a glass composition is laminated on the inner surface of the trench 118 and the surface of the semiconductor substrate 100b in the vicinity thereof by an electrophoresis method. Then, the laminated glass composition is fired. By this, the glass layer 128 is formed. As a result, the exposed surface 111 on the inner surface of the trench 118 is covered with the glass layer 128 through the oxide film 126.
The firing temperature of the glass composition is, for example, 900 ℃. The firing time of the glass composition is, for example, 15 to 30 minutes at a firing temperature of 900 ℃.
The glass composition is, for example: containing at least SiO2、Al2O3、B2O3And at least two alkaline earth metal oxides selected from the group consisting of ZnO, CaO, BaO, and MgO, and substantially not containing Pb, As, Sb, Li, Na, and K.
The glass composition is preferably one comprising: SiO 22In the range of 49.5 mol% to 64.3 mol%, Al2O3The content of (B) is in the range of 3.7 mol% to 14.8 mol%, B2O3The glass composition has a content of ZnO of 8.4 to 17.9 mol%, a content of ZnO of 3.9 to 14.2 mol%, and a content of alkaline earth metal oxide of 7.4 to 12.9 mol%.
The term "comprising a specific component" as used herein means that the specific component alone is contained, and means that the specific component may be contained in addition to the specific component. The substantial absence of a specific element means that the specific element is not contained as a component, and does not mean that a glass composition in which the specific element is mixed as a dopant is excluded from raw materials of each component constituting the glass. Note that the oxide not containing a specific element and the nitride not containing the specific element represent an oxide not containing the specific element and a nitride of the specific element.
Mixing SiO2The reason why the content of (B) is set in the range of 49.5 to 64.3 mol% is as follows: if SiO2When the content of (b) is less than 49.5 mol%, the chemical resistance of the glass layer 128 may be reduced, or the insulating property of the glass layer 128 may be reduced. While if SiO2If the content of (2) exceeds 64.3 mol%, the firing temperature of the glass composition may be increased.
Mixing Al2O3The content of (a) is set to 3.7 mol% to 14.8 mol%The reason for the range of l% is as follows: if Al is present2O3When the content of (b) is less than 3.7 mol%, the chemical resistance of the glass layer 128 may be reduced, or the insulating property of the glass layer 128 may be reduced. And if Al2O3If the content of (2) exceeds 14.8 mol%, the firing temperature of the glass composition may be increased.
B is to be2O3The reason why the content of (B) is set in the range of 8.4 to 17.9 mol% is as follows: if B is present2O3When the content of (2) is less than 8.4 mol%, the firing temperature of the glass composition may be increased. And if B2O3If the content of (2) exceeds 17.9 mol%, B (boron) may diffuse into the semiconductor substrate 100B during firing of the glass composition, thereby lowering the insulation properties.
The reason why the content of ZnO is set to be in the range of 3.9 mol% to 14.2 mol% is as follows: if the content of ZnO is less than 3.9 mol%, the firing temperature of the glass composition may be increased. On the other hand, if the content of ZnO exceeds 14.2 mol%, the chemical resistance of the glass layer 128 may be reduced, or the insulating property of the glass layer 128 may be reduced.
The reason why the content of the alkaline earth metal oxide is set to be in the range of 7.4 mol% to 12.9 mol% is as follows: if the content of the alkaline earth metal oxide is less than 7.4 mol%, the firing temperature of the glass composition may be increased. On the other hand, if the content of the alkaline earth metal oxide exceeds 12.9 mol%, the chemical resistance of the glass layer 128 may be reduced, or the insulating property of the glass layer 128 may be reduced.
The glass composition is preferably one having an average linear expansion coefficient of 3.33X 10 in a temperature range of 50 to 550 DEG C-6～4.08×10-6Glass compositions within the range.
The glass composition according to the present embodiment can be produced, for example, by the following method. First, a raw material (SiO) was blended2、Al(OH)3、H3BO3、ZnO、CaCO3、Mg(OH)2BaO) in such a manner that the above-mentioned composition ratio (molar ratio) is obtained. Then, the raw materials are fully stirred by a stirrerAnd (4) stirring. Subsequently, the stirred raw material is put into a platinum crucible which is heated to a predetermined temperature (for example, 1550 ℃) in an electric furnace, and melted for a predetermined time (for example, 30 to 120 minutes). Subsequently, the raw material melt is flowed to a water-cooled roll. In this way, a Glass flake (Glass flake) can be obtained. Finally, the glass flakes are ground in a Ball mill (Ball mill) to a defined average particle size. In this way, a powdery glass composition can be obtained.
(electrode formation step)
In the electrode forming process, first, a Photoresist (Photoresist) is formed so as to cover the surface of the glass layer 128. Next, a portion other than the portion for forming the anode electrode 130 on the one main surface of the semiconductor substrate 100b is masked (Mask) with a photoresist. Next, the surface oxide film 120 is etched. Thus, the surface oxide film 120 is removed from the portion of the one main surface of the semiconductor substrate 100b where the anode electrode 130 is to be formed. Further, the surface oxide film 122 is also removed from the other main surface of the semiconductor substrate 100 b. Next, the semiconductor substrate 100b is subjected to plating treatment. In this way, the anode electrode 130 can be formed on the portion of the semiconductor substrate 100b from which the oxide film 120 has been removed from the upper surface of the one main surface. The cathode electrode 132 is formed on the other main surface of the semiconductor substrate 100 b.
(semiconductor substrate cutting Process)
As shown in fig. 4, the semiconductor substrate dicing step is a step of dicing the semiconductor substrate 100b into chips to manufacture the semiconductor device 100. FIG. 4(b) is a sectional view taken along line A-A in FIG. 4 (a).
As shown in fig. 4(a) and (b), the semiconductor substrate Dicing step is performed by Dicing the semiconductor substrate 100b along a Dicing Line (Dicing Line) DL passing through the center of the trench 118 in the width direction, for example, using a Dicing saw (Dicing saw). As shown in fig. 4(c), the semiconductor substrate 100b is thus formed into a chip, and the semiconductor device 100 as a mesa pn diode can be manufactured.
As described above, according to the method of manufacturing a semiconductor device of the present embodiment, in the oxide film forming step after the trench stopper ring forming step, the oxide film 126 is formed so as to cover the exposed surface 111. This allows n-type dopant 10 introduced into first exposed region 111a of exposed surface 111 to diffuse in first semiconductor layer 110 by the heat applied when oxide film 126 is formed. In this regard, description will be made with reference to fig. 8.
As shown in fig. 8, after the oxide film forming step, n-type dopant 10 is thermally diffused to a position deeper from exposed surface 111 than before the oxide film forming step. As a result, the concentration peak of n-type dopant 10 in the vicinity of exposed surface 111 is lowered after the oxide film forming step, and the width of the peak is diffused to a position deeper than exposed surface 111. That is, in the oxide film forming step, the region of the channel stopper 124 is enlarged to a second depth deeper than the first depth in the channel stopper forming step.
This can suppress the expansion of the depletion layer in the reverse bias voltage applied state, and as a result, can suppress the generation of a leakage current. Therefore, the semiconductor device 100 with high reliability can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the dopant can be introduced to a deeper position without increasing the laser power. This can suppress the generation of surface defects due to laser irradiation. Therefore, the semiconductor device 100 after manufacturing can suppress the generation of the leakage current.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the processing is performed at a temperature of 900 ℃ or higher in the oxide film forming step. In this way, n-type dopant 10 serving as channel stopper 124 can be diffused to a position sufficiently deep from exposed surface 111.
In the method for manufacturing a semiconductor device according to the present embodiment, in the glass layer forming step, the glass layer 128 is formed by firing a layer made of a glass composition formed so as to cover the exposed surface 111. In this way, n-type dopant 10 introduced into first exposed surface 111a of exposed surfaces 111 can be diffused in first semiconductor layer 110 by the heat applied during firing. This can further suppress the expansion of the depletion layer in the reverse bias voltage applied state, and as a result, the generation of the leakage current can be further suppressed. Therefore, the semiconductor device 100 with higher reliability can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, by performing the hydrophobic treatment in the pretreatment step, the concentration of n-type dopant 10 introduced into first semiconductor layer 110 can be increased by laser irradiation in the channel stopper ring formation step. In this regard, description will be made with reference to fig. 7.
The example in fig. 7 shows the results of the following processing. First, in the pretreatment step of the present embodiment, a mixed solution of hydrofluoric acid and nitric acid (HF: HNO) is used31:25) to be subjected to hydrophobic treatment. Next, in the dopant supply step, a liquid in which pyrophosphate is dissolved in ethanol is applied by a dipping method. Next, in the channel stopper forming step, a green laser beam having a wavelength of 632nm was irradiated with a pulse oscillation at a frequency of 30 kHz.
The comparative example is a result of performing the dopant supply step and the channel stopper formation step under the same conditions as in the example without performing the hydrophobic treatment in the pretreatment step in the present embodiment.
In the examples, the concentration of n-type dopant 10 was higher than in the comparative examples regardless of the depth (position) from exposed surface 111. For example, the concentration peak of n-type dopant 10 in the vicinity of exposed surface 111 is 10 in comparative example19/cm3And in the embodiment, is about 1020/cm3And (4) respectively. Therefore, in order to increase the concentration of the channel stopper, it is effective to perform the hydrophobic treatment in the pretreatment step.
Therefore, even in a higher temperature environment, the expansion of the depletion layer in the reverse bias voltage applied state can be suppressed, and therefore the generation of the leakage current can be suppressed. Thus, the semiconductor device 100 can be operated normally. That is, the semiconductor device 100 with higher reliability can be provided.
In the method for manufacturing a semiconductor device according to the present embodiment, in the glass layer forming step, the glass layer 128 is formed by firing a layer made of a glass composition formed so as to cover the exposed surface 111. In this way, n-type dopant 10 introduced into first exposed surface 111a of exposed surfaces 111 can be diffused in first semiconductor layer 110 by the heat applied during firing. This can further suppress the expansion of the depletion layer in the reverse bias voltage applied state, and as a result, the generation of the leakage current can be further suppressed. Therefore, the semiconductor device 100 with higher reliability can be provided.
In the method of manufacturing a semiconductor device according to the present embodiment, the oxide film 126 is formed so as to cover the exposed surface 111 in the oxide film forming step after the trench stopper ring forming step and before the glass layer forming step. In this way, the heat applied when forming n-type dopant 10 introduced into first exposed surface 111a of exposed surfaces 111 through oxide film 126 can be diffused in first semiconductor layer 110. In this regard, description will be made with reference to fig. 8.
As shown in fig. 8, after the oxide film forming step, n-type dopant 10 is thermally diffused to a position deeper from exposed surface 111 than before the oxide film forming step. As a result, the concentration peak of n-type dopant 10 in the vicinity of exposed surface 111 is lowered after the oxide film forming step, and the width of the peak is diffused to a position deeper than exposed surface 111. That is, in the oxide film forming step, the region of the channel stopper 124 is enlarged to a second depth deeper than the first depth in the channel stopper forming step.
This can suppress the expansion of the depletion layer in the reverse bias voltage applied state, and as a result, can suppress the generation of a leakage current. Therefore, the semiconductor device 100 with higher reliability can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the dopant can be introduced to a deeper position without increasing the laser power. This can suppress the generation of surface defects due to laser irradiation. Therefore, the semiconductor device 100 after manufacturing can suppress the generation of the leakage current.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition As the raw material of the glass layer 128 does not substantially contain Pb, As, and Sb which are substances that impose a load on the environment. This reduces the load on the environment. Further, the glass layer 128 is composed of a lead-free glass having a lower dielectric constant than a lead-containing glass. By doing so, even if a reverse bias voltage is applied to a resin-encapsulated semiconductor device formed by molding the semiconductor device 100 with a resin in a high-temperature environment, it is possible to suppress high-density ions from being induced at the interface between the molding resin and the glass layer 128 and at the interface between the glass layer 128 and the first semiconductor layer 110. As a result, the reverse bias resistance at high temperatures can be improved as compared with a conventional resin-encapsulated semiconductor device formed by molding a semiconductor device obtained using a lead-containing glass with a resin.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition as the raw material of the glass layer 128 does not substantially contain L1, Na, and K. Thus, even if B (boron) is contained in the glass composition, B (boron) does not diffuse from the glass layer 128 into silicon during firing of the glass composition. Thus, the highly reliable semiconductor device 100 can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, since the semiconductor device is formed by including at least SiO2、Al2O3、B2O3A layer of a glass composition for semiconductor junction protection comprising glass fine particles made of a molten solution obtained by melting at least two alkaline earth metal oxides selected from the group consisting of ZnO, CaO, BaO, and MgO, and substantially not containing Pb, As, Sb, Li, Na, and K As raw materials is fired to form glass layer 128, and therefore the glass composition can be further fired at a relatively low temperatureAnd (5) line firing. Thus, the glass composition is less likely to be crystallized during firing of the glass composition. As a result, the semiconductor device 100 having low reverse leakage current can be stably manufactured.
Further, according to the method for manufacturing a semiconductor device of the present embodiment, SiO is contained in the glass composition2In the range of 49.5 mol% to 64.3 mol%, Al2O3The content of (B) is in the range of 3.7 mol% to 14.8 mol%, B2O3The content of (B) is in the range of 8.4 to 17.9 mol%, the content of ZnO is in the range of 3.9 to 14.2 mol%, and the content of alkaline earth metal oxide is in the range of 7.4 to 12.9 mol%. In this way, it is possible to suppress: the firing temperature of the glass composition increases, the chemical resistance of the glass layer 128 decreases, or the insulating property of the glass layer 128 decreases.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition has an average linear expansion coefficient of 3.33 × 10 in a temperature range of 50 ℃ to 550 ℃-6～4.08×10-6Within the range. In this way, since the glass composition has a linear expansion coefficient close to that of silicon, the semiconductor base body 100b can be prevented from being bent in the manufacturing process.
In the method of manufacturing a semiconductor device according to this embodiment, the exposed surface 111 is the surface of the trench 118, and is formed so as to reach the first semiconductor layer 110 after separating the second semiconductor layer 112 into mesa shapes. Thus, the trench stopper 124 can be disposed on the bottom surface of the trench 118 in the mesa semiconductor device 100. As a result, even when the depletion layer of the pn junction is diffused at a high voltage, the depletion layer is terminated at the channel stopper 124 and is not exposed to the chip dividing surface. Thus, the mesa semiconductor device 100 can have a high breakdown voltage.
[ second embodiment ]
Next, a second embodiment of the present invention will be explained. The semiconductor device according to this embodiment is a planar (planar Type) semiconductor device in which a channel stopper is disposed. Next, the structure of the semiconductor device according to the present embodiment will be described with reference to fig. 6 (d).
As shown in fig. 6(d), the semiconductor device according to the present embodiment includes: having n-A first semiconductor layer 210 of type (first conductivity type), and p arranged on one principal surface side of the first semiconductor layer 210+A semiconductor element of the second semiconductor layer 212 of type (second conductivity type); a channel stopper 224; and an oxide film 226.
The semiconductor element 200c further includes n arranged on the other principal surface side of the first semiconductor layer 210+And a type (first conductivity type) third semiconductor layer 214. The semiconductor device further includes: a glass layer 228; an anode electrode 230 formed on the surface of the second semiconductor layer 212; and a cathode electrode 232 formed on the surface of the third semiconductor layer 214.
The semiconductor element 200c further has a junction 211 where a pn junction formed at a junction between the first semiconductor layer 210 and the second semiconductor layer 212 is exposed. The channel stopper 224 is formed on the first exposed region 211a of the exposed surface 211 where the first semiconductor layer 210 is exposed. The oxide film 226 is formed to cover the exposed surface 211. A glass layer 228 is formed to cover the oxide film 226.
As shown in fig. 5 and 6, the method for manufacturing a semiconductor device according to the present embodiment includes the following steps. Next, the respective steps will be explained in order.
(semiconductor substrate preparation Process)
As shown in fig. 5(a) to (c), the semiconductor multilayer structure fabrication process is a process for fabricating a semiconductor multilayer structure 200 a. The semiconductor stacked structure 200a includes: n is-A first semiconductor layer 210 of type (first conductivity type); p arranged on one main surface side of the first semiconductor layer 210+A second semiconductor layer 212 of type (second conductivity type); and n arranged on the other principal surface side of the first semiconductor layer 210+And a type (first conductivity type) third semiconductor layer 214.
In the semiconductor substrate preparation step, for example, first, as shown in FIG. 5(a), n is+N on the type semiconductor layer 214-The type epitaxial layer 210 is stacked. Next, as shown in FIG. 5(b)After mask M1 was formed, at n, through mask M1-P-type dopants (e.g., B (boron) ions) are introduced into a predetermined region of the surface of the epitaxial layer 210 by ion implantation. The mask M1 is arranged to open a part of one main surface of the semiconductor base 200 a. Then, p is formed by thermal diffusion+The type diffusion 212. Subsequently, the mask M1 is removed. By this, the semiconductor base 200a is prepared. At this time, an exposed surface 211 is formed on one main surface of the semiconductor substrate 200 a. The exposed surface 211 is composed of a first exposed region 211a where the first semiconductor layer 210 is exposed and a second exposed region 211b where the second semiconductor layer 212 is exposed.
(pretreatment step)
The pretreatment step is a step of subjecting the first exposed region 211a of the exposed surface 211, in which the first semiconductor layer 210 is exposed, to a hydrophobic treatment.
The hydrophobic treatment is performed, for example, by immersing the first exposed region 211a in a hydrophobic treatment solution. As the hydrophobic treatment solution, it is preferable to use hydrofluoric acid (HF) and nitric acid (HNO)3) The mixed solution of (1).
(dopant supplying step)
As shown in fig. 5(c), the dopant supply step is a step of supplying n-type dopant 20 to first exposed region 211 a.
The dopant supply process is performed by, for example, applying a liquid containing n-type (first conductivity type) dopant 20 to the first exposed region 211 a. The liquid containing the N-type dopant 20 is preferably a liquid obtained by dissolving a phosphorus compound in an organic solvent, for example, as in the first embodiment. As a method of coating, a known method such as a dipping method, a spin (Spinner) method, or a spray method can be used as in the first embodiment.
(channel stopper Ring formation Process)
As shown in fig. 5 d, the channel stopper forming step is a step of forming a channel stopper 224 by introducing n-type (first conductivity type) dopant 20 into the first semiconductor layer 210.
n-type dopant 20 is introduced by irradiating a predetermined region of first exposed region 211a with laser light, as in the first embodiment.
(oxide film formation step)
As shown in fig. 5(e), the oxide film forming step is a step of forming an oxide film 226 so as to cover the exposed surface 211 after the channel stopper ring forming step and before the glass layer forming step described later.
The oxide film 226 is formed by, for example, a thermal oxidation method using dry oxygen as in the first embodiment. Thus, the oxide film 226 is formed on the one main surface of the semiconductor substrate 200 a. At this time, the surface oxide film 222 is formed on the other main surface of the semiconductor substrate 200 a.
(glass layer Forming Process)
As shown in fig. 6(a), the glass layer forming step is a step of forming a passivation glass layer 228 to cover the exposed surface 211 with a glass composition.
In the glass layer forming step, the glass composition is laminated on one surface side of the semiconductor substrate 200a by an electrophoresis method, as in the first embodiment. Then, the laminated glass composition is fired. As a result, the exposed surface 211 is covered with the glass layer 228 through the oxide film 226.
As the glass composition, a composition having the same composition as that of the first embodiment can be preferably used. As the glass composition, a composition having the same linear expansion coefficient as that of the first embodiment can be preferably used.
(etching Process)
As shown in fig. 6(b) and (c), the etching step is a step of forming an oxide film 226 and a glass layer 228 on a predetermined region of one main surface of the semiconductor substrate 200 a.
In the etching step, for example, a mask M2 is formed on one principal surface side of the semiconductor base 200a so as to cover the interface between the first exposed region 211a and the second exposed region 211 b. Next, the glass layer 228 and the oxide film 226 are etched. In this way, the oxide film 226 and the glass layer 228 can be formed only in a predetermined region. At this time, the oxide film 222 is removed from the other main surface of the semiconductor substrate 200 a.
(electrode formation step)
As shown in fig. 6(d), the electrode forming step is a step of forming an anode electrode 230 and a cathode electrode 232 on the semiconductor substrate 200 a.
In the motor forming step, after the mask M2 is removed, the anode electrode 230 is formed on the region surrounded by the glass layer 228 on the one main surface of the semiconductor substrate 200 a. Further, a cathode electrode 232 is formed on the rear surface of the semiconductor substrate 200 a.
(semiconductor substrate cutting Process)
The semiconductor substrate dicing step is a step of dicing the semiconductor substrate 200a into chips using a dicing saw or the like, as in the first embodiment. As a result, as shown in fig. 6(d), the semiconductor base 200a is formed into a chip, and a semiconductor device as a planar pn diode is manufactured.
As described above, according to the method for manufacturing a semiconductor device of the present embodiment, the same effects as those of the first embodiment can be obtained. That is, in the oxide film forming step after the trench stopper forming step, the oxide film 226 is formed so as to cover the exposed surface 211. Therefore, the first conductive dopant 20 introduced into the first exposed region 211a of the exposed surface 211 can be diffused in the first semiconductor layer 210 by the heat applied when the oxide film 226 is formed. In this way, since the expansion of the depletion layer can be suppressed when reverse bias is applied, the generation of leakage current can be suppressed. Thus, a highly reliable semiconductor device can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the processing is performed at a temperature of 900 ℃ or higher in the oxide film forming step. In this way, first conductive type dopant 20 serving as channel stopper 224 can be diffused to a sufficient depth from exposed surface 211.
In the method for manufacturing a semiconductor device according to the present embodiment, in the glass layer forming step, the glass layer 228 is formed by firing a layer made of a glass composition formed so as to cover the exposed surface 211. Therefore, the first conductive dopant 20 introduced into the first exposed surface 211a of the exposed surfaces 211 can be diffused in the first semiconductor layer 210 by the heat applied during firing. This can further suppress the expansion of the depletion layer in the reverse bias voltage applied state, and as a result, the generation of the leakage current can be further suppressed. Therefore, a semiconductor device with higher reliability can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, by performing the hydrophobic treatment in the pretreatment step, the concentration of the first conductive type dopant 20 introduced into the first semiconductor layer 210 can be increased by laser irradiation in the channel stopper ring formation step. As a result, even in a higher temperature environment, the expansion of the depletion layer at the time of reverse bias application can be suppressed, and the generation of leakage current can be suppressed. Therefore, the semiconductor device can be normally operated. That is, a highly reliable semiconductor device can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition As the raw material of the glass layer 228 does not substantially contain Pb, As, and Sb which are substances that impose a load on the environment. This reduces the load on the environment. Further, the glass layer 228 is composed of a lead-free glass having a lower dielectric constant than a lead-containing glass. Thus, even when a reverse bias voltage is applied to a resin-encapsulated semiconductor device formed by molding a semiconductor device with a resin in a high-temperature environment, it is possible to suppress high-density ions from being induced at the interface between the molding resin and the glass layer 228 and at the interface between the glass layer 228 and the first semiconductor layer 210. As a result, the reverse bias resistance at high temperatures can be improved as compared with a conventional resin-encapsulated semiconductor device formed by molding a semiconductor device obtained using a lead-containing glass with a resin.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition as a raw material of the glass layer 228 does not substantially contain L1, Na, and K. Thus, even if B (boron) is contained in the glass composition, B (boron) does not diffuse from the glass layer 128 into silicon during firing of the glass composition. Thus, a highly reliable semiconductor device can be provided.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, since the semiconductor device is formed by including at least SiO2、Al2O3、B2O3The glass layer 228 is formed by firing a layer composed of a glass composition for semiconductor junction protection, which is composed of glass fine particles made of a molten liquid obtained by melting raw materials containing substantially no Pb, As, Sb, Li, Na, and K, and at least two alkaline earth metal oxides selected from ZnO, CaO, MgO, and BaO. Thus, the glass composition is less likely to be crystallized during firing of the glass composition. As a result, a semiconductor device with low reverse leakage current can be stably manufactured.
Further, according to the method for manufacturing a semiconductor device of the present embodiment, SiO is contained in the glass composition2In the range of 49.5 mol% to 64.3 mol%, Al2O3The content of (B) is in the range of 3.7 mol% to 14.8 mol%, B2O3The content of (B) is in the range of 8.4 to 17.9 mol%, the content of ZnO is in the range of 3.9 to 14.2 mol%, and the content of alkaline earth metal oxide is in the range of 7.4 to 12.9 mol%. In this way, it is possible to suppress: the firing temperature of the glass composition increases, the chemical resistance of the glass layer 228 decreases, or the insulating property of the glass layer 228 decreases.
In addition, according to the method for manufacturing a semiconductor device of the present embodiment, the glass composition has an average linear expansion coefficient of 3.33 × 10 in a temperature range of 50 ℃ to 550 ℃-6～4.08×10-6Within the range. In this way, since the glass composition has a linear expansion coefficient close to that of silicon, the semiconductor base 200a can be prevented from being bent in the manufacturing process.
Although the preferred embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to the above embodiments. The shapes and combinations of the components of the site in the above embodiment are merely examples. Therefore, the present invention can be variously modified in accordance with design requirements and the like without departing from the gist of the present invention.
In the method for manufacturing a semiconductor device of the present invention, the pretreatment step may not be performed. In the method for manufacturing a semiconductor device of the present invention, the glass layer forming step may not be performed.
The method of manufacturing a semiconductor device of the present invention may include at least a semiconductor substrate preparation step, a dopant supply step, a channel stopper ring formation step, and an oxide film formation step.
The semiconductor device of the present invention may include at least a semiconductor element, a channel stopper, and an oxide film.
In the above embodiments, the first conductivity type was described as n-type and the second conductivity type was described as p-type, but the present invention is not limited to this. The first conductivity type may be a p-type, and the second conductivity type may be an n-type.
In the above embodiment, the laser irradiation is performed using the green laser beam, but the present invention is not limited to this. The laser irradiation can be preferably performed by a visible laser beam or a near-infrared laser beam (for example, Nd — YAG laser beam) other than green laser beam.
In the above embodiment, a liquid in which pyrophosphoric acid is dissolved in an organic solvent is used as the liquid containing the n-type dopant, but the present invention is not limited thereto. For example, a liquid obtained by dissolving a phosphorus compound or an arsenic compound other than pyrophosphoric acid in various organic solvents can also be used.
In the above-described embodiments, the present invention has been described by taking a pn diode as an example of a semiconductor device, but the present invention is not limited to this. The present invention can be applied to other power semiconductor devices such as diodes other than pn diodes (e.g., pin diodes, schottky diodes, etc.), transistors (e.g., bipolar transistors, MOSFETs, IGBTs, etc.), thyristors, and triodes.
Description of the symbols
10. 20 … n-type (first conductivity type) dopant; 100 … semiconductor devices; 100a … semiconductor stack configuration; 100b, 200a … semiconductor substrate; 100c … semiconductor element; 110. 210 … a first semiconductor layer; 111. 211 … exposed surface; 111a, 211a … first exposed area; 111b, 211b … second exposed area; 112. 212 … second semiconductor layer; 114. 214 … a third semiconductor layer; 120. 122, 222 … surface oxidation film; 124. 224 … channel stopper; 126. 226 … oxide film; 128. 228 … glass layer; 130. 230 … an anode electrode; 132. 232 … cathode electrode

Claims (10)

1. A method for manufacturing a semiconductor device, comprising:
a semiconductor substrate preparation step of preparing a semiconductor substrate having an exposed surface exposed to a pn junction formed at a junction between a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, the exposed surface being formed of a first exposed region exposed to the first semiconductor layer and a second exposed region exposed to the second semiconductor layer;
a pretreatment step of subjecting only the first exposed region of the exposed surface to a hydrophobic treatment in which only the first exposed region is immersed in a hydrophobic treatment solution;
a dopant supply step of supplying a first conductive type dopant to a first exposed region of the exposed surface where the first semiconductor layer is exposed;
a channel stopper forming step of forming a channel stopper to a first depth by introducing the first conductive type dopant into the first semiconductor layer by laser irradiation of the first exposed region; and
and an oxide film forming step of forming an oxide film by thermal oxidation treatment at a predetermined temperature so as to cover the exposed surface on which the trench stopper is formed and to expand a region of the trench stopper to a second depth deeper than the first depth.
2. The method for manufacturing a semiconductor device according to claim 1, wherein:
wherein the thermal oxidation treatment is performed at a temperature of 900 ℃ or higher for 90 minutes in the oxide film forming step.
3. The method for manufacturing a semiconductor device according to claim 1, wherein:
wherein the method comprises a glass layer forming step of forming a glass layer by firing the layer made of the glass composition after forming the layer made of the glass composition and covering the oxide film.
4. The method for manufacturing a semiconductor device according to claim 3, wherein:
wherein the glass composition does not substantially contain Pb.
5. The method for manufacturing a semiconductor device according to claim 3, wherein:
wherein the glass composition does not substantially contain As, Sb, Li, Na, K.
6. The method for manufacturing a semiconductor device according to claim 3, wherein:
wherein the glass composition contains at least SiO2、B2O3、Al2O3At least two alkaline earth metal oxides selected from the group consisting of ZnO, CaO, MgO, and BaO, and substantially not containing Pb, As, Sb, Li, Na, and K.
7. The method for manufacturing a semiconductor device according to claim 6, wherein:
wherein, in the glass composition,
SiO2the content of (B) is in the range of 49.5 mol% to 64.3 mol%,
Al2O3the content of (B) is in the range of 3.7 mol% to 14.8 mol%,
B2O3the content of (B) is in the range of 8.4 mol% to 17.9 mol%,
the content of ZnO is within the range of 3.9 mol% to 14.2 mol%,
the content of the alkaline earth metal oxide is in the range of 7.4 to 12.9 mol%.
8. The method for manufacturing a semiconductor device according to claim 3, wherein:
wherein the glass composition has an average linear expansion coefficient of 3.33 x 10 in a temperature range of 50 ℃ to 550 ℃-6～4.08×10-6Within the range.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein:
wherein the exposed surface is an inner surface of a groove formed to separate the second semiconductor layer into a mesa shape and reach the first semiconductor layer.
10. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 9, comprising:
a semiconductor element having the exposed surface;
the channel stopper formed on the first exposed region of the semiconductor element; and
the oxide film is formed to cover the exposed surface of the semiconductor element.
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