CN108022549B - Logic circuit, shift register, drive circuit and display panel - Google Patents
Logic circuit, shift register, drive circuit and display panel Download PDFInfo
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- CN108022549B CN108022549B CN201810105816.9A CN201810105816A CN108022549B CN 108022549 B CN108022549 B CN 108022549B CN 201810105816 A CN201810105816 A CN 201810105816A CN 108022549 B CN108022549 B CN 108022549B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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Abstract
The invention discloses a logic circuit, a shift register, a driving circuit and a display panel, wherein the logic circuit comprises six switch units; the control ends of the first and fifth switch units are connected to the first input end; the first end of the first switch unit, the control end of the third switch unit and the first end are connected to the first power voltage end; the second end of the first switch unit is connected with the first end of the second switch unit; the second and fourth switch unit control terminals are connected to the second input terminal; the second end of the third switching unit and the first end of the fourth switching unit are connected with the control end of the sixth switching unit; the second end of the second switch unit and the first end of the sixth switch unit are connected to the output end; the second end of the fourth switch unit is connected with the first end of the fifth switch unit; second terminals of the fifth and sixth switching units are connected to the second power supply voltage terminal. The method and the device can eliminate the influence of impurity substitution brought by conduction when the grid source voltage is zero or the grid floating, eliminate the loss of threshold voltage, improve the process and reduce the cost.
Description
Technical Field
The present invention relates to the field of circuit control technologies, and in particular, to a logic circuit, a shift register, a driving circuit, and a display panel.
Background
The and gate circuit is one of the logic circuits commonly used in digital circuits, and for a two-input and gate, when two input signals are both at high level, the output is at high level, otherwise, the output is at low level. Meanwhile, various logic circuits are often designed in the device based on the requirements of circuit control or function realization, for example, in the display field, the related logic circuit control is usually realized by a TFT transistor.
The prior AND gate structure is mainly manufactured by two types of MOS transistors or TFTs at the same time, and the AND gate circuit is generally formed by a structure of a NAND gate and a NOT gate, namely, the prior AND gate circuit in the display field is a design circuit mixed by P-type and N-type TFT transistors, and the design has obvious disadvantages in terms of process and cost due to two different processes.
Therefore, in the process of implementing the present application, the inventors found that how to eliminate the influence of impurity substitution caused by zero gate-source voltage or conduction at the time of gate floating when an oxide TFT transistor constitutes an and circuit is an important problem to be solved urgently by the related art.
Disclosure of Invention
In view of the above, the present invention is directed to a logic circuit, a shift register, a driving circuit and a display panel, which can eliminate the influence of impurity substitution caused by the turn-on of the relevant logic circuit when the gate-source voltage is zero or the gate floating is performed, so as to eliminate the loss of the threshold voltage, improve the process and reduce the cost.
In view of the above object, in a first aspect of the present application, there is provided a logic circuit comprising: a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit and a sixth switch unit; the control end of the first switch unit and the control end of the fifth switch unit are both connected to a first input end; the first end of the first switching unit, the control end of the third switching unit and the first end of the third switching unit are connected to a first power supply voltage end; the second end of the first switch unit is connected with the first end of the second switch unit; the control end of the second switch unit and the control end of the fourth switch unit are both connected to a second input end; the second end of the third switching unit and the first end of the fourth switching unit are both connected with the control end of the sixth switching unit; the second end of the second switch unit and the first end of the sixth switch unit are both connected to the output end; the second end of the fourth switch unit is connected with the first end of the fifth switch unit; a second terminal of the fifth switching unit and a second terminal of the sixth switching unit are both connected to a second power supply voltage terminal; the control end is used for controlling the connection or disconnection of the first end and the second end of the corresponding switch unit.
Optionally, the logic circuit further includes a second capacitor; the first end of the second capacitor is connected to the control end of the second switch unit, and the second end of the second capacitor is connected to the second end of the second switch unit.
Optionally, the logic circuit further includes a first capacitor; the first end of the first capacitor is connected to the control end of the first switch unit, and the second end of the first capacitor is connected to the second end of the first switch unit.
Optionally, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all thin film transistors; the control end in the switch unit is a grid electrode, the first end in the switch unit is a source electrode or a drain electrode, and the second end in the switch unit is a drain electrode or a source electrode corresponding to the first end.
Optionally, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all N-type thin film transistors.
Optionally, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are MOS transistors.
Optionally, the first power supply voltage terminal is connected to a high voltage reference signal; the second power supply voltage terminal is connected with a low voltage reference signal.
In a second aspect of the present application, there is also provided a shift register including the logic circuit of any one of the above.
In a third aspect of the present application, there is also provided a driving circuit including the logic circuit of any one of the above.
In a fourth aspect of the present application, there is also provided a display panel including the shift register or the driving circuit.
As can be seen from the above, the logic circuit, the shift register, the driving circuit and the display panel provided by the invention can realize corresponding logic control by using a uniform switch unit through a reasonably designed circuit control mode, so that the process can be optimized and the cost can be reduced compared with the prior art; meanwhile, the unified switch unit is used to avoid the loss of output voltage caused by different threshold voltages, and the influence of impurity substitution caused by conduction of related logic circuits when the grid source voltage is zero or the grid electrode flowing can be eliminated. Therefore, the logic circuit can improve the circuit control effect, improve the process and reduce the cost.
Drawings
FIG. 1 is a schematic diagram of an embodiment of a logic circuit provided in the present invention;
fig. 2 is a schematic structural diagram of another embodiment of a logic circuit provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
The method aims to solve the process difficulty caused by the fact that an N-type TFT and a P-type TFT are used for designing and designing a logic gate circuit in the prior art, and meanwhile eliminates the influence that an oxide TFT is likely to be opened when Vgs is 0v usually and eliminates the loss of threshold voltage of an output end. An improved logic circuit design is presented.
In the first embodiment, the first step is,
in order to overcome the problem of using two types of TFTs simultaneously in the prior art, a new logic control structure of the circuit needs to be designed accordingly, and in one embodiment of the present application, the logic circuit includes: a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit and a sixth switch unit; the control end of the first switch unit and the control end of the fifth switch unit are both connected to a first input end; the first end of the first switching unit, the control end of the third switching unit and the first end of the third switching unit are connected to a first power supply voltage end; the second end of the first switch unit is connected with the first end of the second switch unit; the control end of the second switch unit and the control end of the fourth switch unit are both connected to a second input end; the second end of the third switching unit and the first end of the fourth switching unit are both connected with the control end of the sixth switching unit; the second end of the second switch unit and the first end of the sixth switch unit are both connected to the output end; the second end of the fourth switch unit is connected with the first end of the fifth switch unit; a second terminal of the fifth switching unit and a second terminal of the sixth switching unit are both connected to a second power supply voltage terminal; the control terminal is used for controlling the connection or disconnection of the first terminal and the second terminal of the corresponding switch unit, and when the control terminal is at a high potential, the first terminal and the second terminal are connected.
For example, when the first power voltage terminal is connected to a high voltage reference signal and the second power voltage terminal is connected to a low voltage reference signal, if the first input terminal is at a high level and the second input terminal is at a low level, the first switching unit and the fifth switching unit are turned on, the second switching unit and the fourth switching unit are turned off, the control terminal of the sixth switching unit is at a high level and is turned on, and the output terminal outputs a low potential corresponding to the second power voltage; similarly, if the second input end is at a high level and the first input end is at a low level, the second switch unit and the fourth switch unit are turned on, the first switch unit and the fifth switch unit are in an off state, the gate high potential of the sixth switch unit is turned on, and the output end outputs a low potential; when the first input end and the second input end are both high potential, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit and the fifth switch unit are all switched on, the control end of the sixth switch unit is in turn-off state for low level, and the output end outputs high level; when the first input end and the second input end are both low potential, the first switch unit, the second switch unit, the fourth switch unit and the fifth switch unit are turned off, the sixth switch unit is turned on at high level, and the output end outputs low level.
Therefore, through the structural design of the logic circuit, corresponding logic control can be realized by using the same switch unit, and further adverse effects caused by a plurality of TFTs and depletion TFTs in the prior art can be overcome.
In some optional embodiments of the present application, the logic circuit further comprises a second capacitor; the first end of the second capacitor is connected to the control end of the second switch unit, and the second end of the second capacitor is connected to the second end of the second switch unit. Therefore, the output end of the switch unit can be fully conducted through the added capacitor, the switching speed is higher when the low level of the circuit is switched to the high level, and the problem of output voltage loss caused by different threshold voltages can be solved.
Preferably, the logic circuit further comprises a first capacitor; the first end of the first capacitor is connected to the control end of the first switch unit, and the second end of the first capacitor is connected to the second end of the first switch unit. Therefore, the control ends corresponding to the two output ends can improve the conversion speed by increasing the capacitance, and the circuit control effect is further improved.
According to the embodiment, the logic circuit can realize corresponding logic control by using a uniform switch unit through a reasonably designed circuit control mode, so that the process can be optimized and the cost can be reduced compared with the prior art; meanwhile, the unified switch unit is used to avoid the loss of output voltage caused by different threshold voltages, and the influence of impurity substitution caused by conduction of related logic circuits when the grid source voltage is zero or the grid electrode flowing can be eliminated. Therefore, the logic circuit can improve the circuit control effect, improve the process and reduce the cost.
In the second embodiment, the first embodiment of the method,
fig. 1 is a schematic structural diagram of an embodiment of a logic circuit provided in the present invention. Specifically, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit are all thin film transistors; the control end in the switch unit is a grid electrode, the first end in the switch unit is a source electrode or a drain electrode, and the second end in the switch unit is a drain electrode or a source electrode corresponding to the first end.
Referring to fig. 1, the first power voltage terminal is at a high potential, the second power voltage terminal is at a low potential, and the six switch units are all thin film transistors (T1, T2, T3, T4, T5, T6). The logic circuit is embodied as follows: when the first input terminal U1 is at a high level and the second input terminal U2 is at a low level, the first switching unit T1 and the fifth switching unit T5 are turned on, the second switching unit T2 and the fourth switching unit T4 are in an off state, the gate of the sixth switching unit T6 is at a high level and thus turned on, and the output terminal U0 outputs a low level; similarly, when the second input terminal U2 is at a high level and the first input terminal U1 is at a low level, the second switch unit T2 and the fourth switch unit T4 are turned on, the first switch unit T1 and the fifth switch unit T5 are turned off, the gate of the sixth switch unit T6 is turned on at a high potential, and the output terminal U0 outputs a low potential; when the first input terminal U1 and the second input terminal U2 are both at a high level, the first switch unit T1, the second switch unit T2, the third switch unit T3, the fourth switch unit T4 and the fifth switch unit T5 are turned on, the gate of the sixth switch unit T6 is turned off at a low level, and the output terminal U0 outputs a high level; when the first input terminal U1 and the second input terminal U2 are both at a low potential, the first switch unit T1, the second switch unit T2, the fourth switch unit T4, and the fifth switch unit T5 are turned off, the gate of the sixth switch unit T6 is turned on at a high level, and the output terminal U0 outputs a low level. Therefore, the following logic control relationship is realized in the logic circuit:
if U1 is 0 and U2 is 0, then U0 is 0;
if U1 is 1 and U2 is 0, then U0 is 0;
if U1 is 0, and U2 is 1, then U0 is 0;
if U1 is 1 and U2 is 1, then U0 is 1;
where "1" refers to high level and "0" refers to low level. U1, U2 represent two input signals; u0 represents the output signal. Therefore, the present embodiment realizes a better logic circuit function through a circuit structure, and can eliminate the influence of unstable floating state caused by the depletion TFT and the adverse influence of possible turn-on when the gate-source voltage of the depletion oxide TFT is zero.
Preferably, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all N-type thin film transistors.
It should be noted that the above embodiments are described by using TFTs as examples, but the present application is not limited to using only TFTs; for example, the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit may be MOS transistors. Of course, other types of switching devices may be used, and the application is not limited thereto.
In the third embodiment, the first step is that,
fig. 2 is a schematic structural diagram of another embodiment of the logic circuit provided in the present invention. As can be seen from the figure, the logic circuit structure in this embodiment is obtained by adding two capacitors to the logic circuit shown in fig. 1, wherein one end of the first capacitor C1 is connected to the control terminal and the gate of the first switch unit T1, and the other end is connected to the second terminal, i.e., the source or the drain, of the first switch unit T1. Similarly, two ends of the second capacitor C2 are respectively connected to the control end and the second end of the first switch unit T2; the rest of the structure remains unchanged, and the description of this embodiment is not repeated. The capacitor is added at the control end of the switch unit, so that the output end of the TFT can be fully conducted, the switching speed is higher when the low level of the circuit is switched to the high level, and the problem of output voltage loss caused by different threshold voltages of the TFT is solved. It should be noted that, the present application is not limited to the two capacitors added in the figure, and a capacitor structure may also be added at a corresponding position of another switch unit according to a control requirement.
In the fourth embodiment, the first step is that,
based on the logic circuits described in the above embodiments, the present application may also apply the logic circuits to various devices or units, for example, may apply to a shift register including the logic circuits described in any of the above embodiments. Or may also be applied to a driving circuit including the logic circuit described in any of the above embodiments. Further alternatively, the present invention may be applied to a display panel including the shift register or the driver circuit.
In some alternative embodiments of the present application, a circuit portion for performing and logic operation processing in a scan driver circuit in a display device may be implemented by a logic circuit described in any of the above embodiments. The logic circuit is applied to a shift register circuit or a scanning circuit in an array substrate.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the invention, also features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity.
In addition, well known power/ground connections to Integrated Circuit (IC) chips and other components may or may not be shown within the provided figures for simplicity of illustration and discussion, and so as not to obscure the invention. Furthermore, devices may be shown in block diagram form in order to avoid obscuring the invention, and also in view of the fact that specifics with respect to implementation of such block diagram devices are highly dependent upon the platform within which the present invention is to be implemented (i.e., specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the invention, it should be apparent to one skilled in the art that the invention can be practiced without, or with variation of, these specific details. Accordingly, the description is to be regarded as illustrative instead of restrictive.
While the present invention has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic ram (dram)) may use the discussed embodiments.
The embodiments of the invention are intended to embrace all such alternatives, modifications and variances that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, substitutions, improvements and the like that may be made without departing from the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. A logic circuit, comprising: a first switch unit, a second switch unit, a third switch unit, a fourth switch unit, a fifth switch unit and a sixth switch unit; the control end of the first switch unit and the control end of the fifth switch unit are both connected to a first input end; the first end of the first switching unit, the control end of the third switching unit and the first end of the third switching unit are connected to a first power supply voltage end; the second end of the first switch unit is connected with the first end of the second switch unit; the control end of the second switch unit and the control end of the fourth switch unit are both connected to a second input end; the second end of the third switching unit and the first end of the fourth switching unit are both connected with the control end of the sixth switching unit; the second end of the second switch unit and the first end of the sixth switch unit are both connected to the output end; the second end of the fourth switch unit is connected with the first end of the fifth switch unit; a second terminal of the fifth switching unit and a second terminal of the sixth switching unit are both connected to a second power supply voltage terminal; the control end is used for controlling the connection or disconnection of the first end and the second end of the corresponding switch unit;
the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit and the sixth switch unit are all thin film transistors of the same type or MOS transistors of the same type.
2. The logic circuit according to claim 1, further comprising a second capacitor; the first end of the second capacitor is connected to the control end of the second switch unit, and the second end of the second capacitor is connected to the second end of the second switch unit.
3. The logic circuit according to claim 1 or 2, further comprising a first capacitor; the first end of the first capacitor is connected to the control end of the first switch unit, and the second end of the first capacitor is connected to the second end of the first switch unit.
4. The logic circuit according to claim 1, wherein when the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all thin film transistors, the control terminal of the switch unit is a gate, the first terminal of the switch unit is a source or a drain, and the second terminal of the switch unit is a drain or a source corresponding to the first terminal.
5. The logic circuit according to claim 4, wherein the first switch unit, the second switch unit, the third switch unit, the fourth switch unit, the fifth switch unit, and the sixth switch unit are all N-type thin film transistors.
6. The logic circuit of claim 1, wherein the first supply voltage terminal is connected to a high voltage reference signal; the second power supply voltage terminal is connected with a low voltage reference signal.
7. A shift register, characterized in that it comprises a logic circuit according to any of claims 1-6.
8. A driver circuit, characterized in that the driver circuit comprises a logic circuit according to any one of claims 1-6.
9. A display panel comprising the shift register of claim 7 or the driver circuit of claim 8.
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| US7514961B2 (en) * | 2007-02-16 | 2009-04-07 | Chi Mei Optoelectronics Corporation | Logic circuits |
| KR101523952B1 (en) * | 2008-12-31 | 2015-06-01 | 삼성전자주식회사 | Semiconductor device and method for fabricating the same |
| KR101622827B1 (en) * | 2014-04-16 | 2016-05-19 | 성균관대학교산학협력단 | Logig gate using schmitt trigger circuit |
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| CN1435947A (en) * | 2002-01-31 | 2003-08-13 | 株式会社东芝 | Logical circuit and semiconductor device |
| CN101404493A (en) * | 2008-02-05 | 2009-04-08 | 杨曙辉 | Analog probability AND gate circuit designed by CMOS transistor |
| CN101547004A (en) * | 2009-05-12 | 2009-09-30 | 威盛电子股份有限公司 | And gate circuit |
| CN204046571U (en) * | 2014-08-22 | 2014-12-24 | 浙江工业大学 | A kind of three input generic logic gate circuits |
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