CN107919400A - A kind of InSe transistors and preparation method thereof - Google Patents

A kind of InSe transistors and preparation method thereof Download PDF

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Publication number
CN107919400A
CN107919400A CN201710927704.7A CN201710927704A CN107919400A CN 107919400 A CN107919400 A CN 107919400A CN 201710927704 A CN201710927704 A CN 201710927704A CN 107919400 A CN107919400 A CN 107919400A
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inse
layer
grid
thin film
protective layers
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CN107919400B (en
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钟旻
陈寿面
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Shanghai IC R&D Center Co Ltd
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Shanghai Integrated Circuit Research and Development Center Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78681—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te

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Abstract

The invention discloses a kind of InSe transistors, including：Grid；Gate dielectric on grid；Crystal growth substrate layer on gate dielectric；InSe thin film channel layers on crystal growth substrate layer above grid；Around the InSe protective layers of InSe thin film channel layers, source-drain area is equipped with the InSe protective layers of grid both sides top position；Passivation layer on InSe thin film channels layer and InSe protective layers, passivation layer are closed InSe thin film channels layer to be isolated from the outside.The present invention can effectively prevent the incident InSe resolution problems during transistor fabrication processes, and can be compatible with existing CMOS technology, preparation process simple possible, can conveniently prepare small size, large-scale InSe transistor arrays.The invention also discloses a kind of preparation method of InSe transistors.

Description

A kind of InSe transistors and preparation method thereof
Technical field
The present invention relates to semiconductor integrated circuit manufacturing process technology field, more particularly, to a kind of InSe transistors And preparation method thereof.
Background technology
As feature sizes of semiconductor devices presses Moore's Law Scaling, chip integration is continuously improved, and tradition is based on Silicon semiconductor device has been difficult to meet that the performance of device and circuit and power consumption will again due to technological limits and various negative effects Ask.Domestic and international major scientific research institution and semiconductor maker study various new materials and new device structure one after another, existing to substitute Some silicon semiconductor devices.
In recent years, graphene is because the electron mobility of its superelevation is (up to 200000cm2/ Vs) become the hot spot studied, but It is due to that graphene does not possess band gap (bandgap) so that its dim future in the application similar to transistor.
In October, 2016, the father Andre Geim (An Deliehaimu) of graphene exist《Nature Nanotechnology》(《Natural nanosecond science and technology》) on publish thesis, prepare the two-dimentional InSe of micron order dimension of picture first (indium selenide) thin film transistor (TFT), and find when indium selenide film only has the thickness of several layers of atoms, its performance is significantly better than silicon Electrical attributes.
Different with graphene, the energy gap of indium selenide is quite big, has good switching characteristic.Therefore, made using indium selenide The transistor made for raceway groove replaces existing silicon transistor, will become following preparation ultrahigh speed, high-performance semiconductor device A kind of selection.
At present, preparing the technological difficulties of InSe thin film transistor (TFT)s has two：
1) InSe film chemicals property is unstable, it is easy to is decomposed by the oxygen in air and aqueous vapor, is prepared by transistor Technological requirement is very high.
2) preparation of InSe films must be on specific substrate, its technique and conventional CMOS technology are incompatible, it is difficult to Prepare small size, large-scale InSe transistor arrays.
The content of the invention
It is an object of the invention to overcome drawbacks described above existing in the prior art, there is provided a kind of InSe transistors and its preparation Method.
To achieve the above object, technical scheme is as follows：
The present invention provides a kind of InSe transistors, include from bottom to top：
Grid；
Gate dielectric on grid；
Crystal growth substrate layer on gate dielectric；
InSe thin film channel layers on crystal growth substrate layer above grid；
Around the InSe protective layers of InSe thin film channel layers, in the InSe protective layers of grid both sides top position Equipped with source-drain area；
Passivation layer on InSe thin film channels layer and InSe protective layers, the passivation layer seal InSe thin film channels layer Close to be isolated from the outside.
Preferably, further include：Source-drain electrode on source-drain area, the interlayer dielectric below crystal growth substrate layer Layer, and the Semiconductor substrate below interlayer dielectric layer；Gate dielectric on the grid and grid is located at interlayer Jie In electric layer.
Preferably, the grid is used to have and formed by the metal material of oxidation characteristic, and the gate dielectric uses grid The metal oxide of pole is formed；The crystal growth substrate layer uses h-BN, β-Si3N4, any one material in SiC formed.
Preferably, the InSe films atomic layer level thickness in the InSe thin film channels layer is 3-15 layers.
Preferably, the InSe protective layers are used forms with the two dimensional crystal material for being doped characteristic.
Present invention also offers a kind of preparation method of above-mentioned InSe transistors, comprise the following steps：
Step S01：There is provided a surface has the Semiconductor substrate of interlayer dielectric layer, and one is formed on the interlayer dielectric layer Groove；
Step S02：Gate metal material is deposited, forms metal gates in a groove；
Step S03：Metal gates upper surface is set to be oxidized to form metal oxide, as gate dielectric；
Step S04：Crystal growth substrate layer and InSe protective layers are sequentially formed in above-mentioned device surface；
Step S05：InSe protective layers are patterned, and source-drain area is formed in InSe protective layers；
Step S06：Protected in InSe and InSe thin film channel layers are formed within layer pattern；
Step S07：Passivation layer is formed on InSe thin film channels layer and InSe protective layers.
Preferably, in step S03, by annealing process, the metal gates upper surface in groove is aoxidized, forms metal Oxide.
Preferably, in step S05, by photoetching, doping and etching, the InSe protection layer patterns with cavity are formed, and Source-drain area is formed in the doped region of InSe protective layers；In step S06, by certainly on the crystal growth substrate layer above grid Alignment growth InSe films, to protect the cavity area within layer pattern to form InSe thin film channel layers in InSe.
Preferably, InSe films, passivation material are deposited in same vacuum equipment.
Preferably, further include：Step S08：Source-drain area in both sides carries out metal deposit and polishing, forms source-drain electrode.
The present invention can effectively prevent the incident InSe resolution problems during transistor fabrication processes, and can Compatible with existing CMOS technology, preparation process simple possible, can conveniently prepare small size, large-scale InSe transistor arrays Row.
Brief description of the drawings
Fig. 1 is a kind of InSe transistor arrangements schematic diagram of a preferred embodiment of the present invention；
Fig. 2 is a kind of preparation method flow chart of InSe transistors of a preferred embodiment of the present invention；
Fig. 3-Figure 10 is that the processing step for preparing InSe transistors in a preferred embodiment of the present invention according to the method for Fig. 2 shows It is intended to.
Embodiment
Below in conjunction with the accompanying drawings, the embodiment of the present invention is described in further detail.
It should be noted that in following embodiments, when embodiments of the present invention are described in detail, in order to clear Ground represents the structure of the present invention in order to illustrate, special not draw to the structure in attached drawing according to general proportion, and has carried out part Amplification, deformation and simplified processing, therefore, should avoid in this, as limitation of the invention to understand.
In embodiment of the invention below, referring to Fig. 1, Fig. 1 is one kind of a preferred embodiment of the present invention InSe transistor arrangement schematic diagrames.As shown in Figure 1, a kind of InSe transistors of the present invention, include at least from bottom to top：Grid 103rd, gate dielectric 104, crystal growth substrate layer 105, InSe thin film channels layer 106 and InSe protective layers 107, passivation layer 108 grade device architectures.
Please refer to Fig.1.Gate dielectric, which is connected, is arranged in the grid of lower floor and the crystal growth substrate positioned at upper strata Between layer；The size of grid and gate dielectric is less than the size of crystal growth substrate layer, and can be located substantially at crystal growth lining Medium position below bottom.Interlayer dielectric layer 102 is equipped with the lower floor of crystal growth substrate layer is also connectable；The grid and Gate dielectric on grid is arranged in interlayer dielectric layer.Semiconductor is equipped with the lower floor of interlayer dielectric layer is also connectable Substrate 101.
The grid, which can use, to be had and can be formed by the metal material of oxidation characteristic, such as Al, Ag, Cu etc..The grid is situated between Electric layer can use the metal oxide of grid be formed, such as when grid uses Al, and Ag, Cu are when metal makes, then gate dielectric Layer can use Al, and the metal oxide of Ag, Cu etc. make.
The crystal growth substrate layer can use h-BN (hexagonal boron nitride), β-Si3N4(β phases Si3N4), it is any in SiC A kind of material makes to be formed.
Crystal growth substrate layer can cooperatively form the gate dielectric layer of metal gates with gate dielectric.
Please refer to Fig.1.On the corresponding crystal growth substrate layer positioned above grid, equipped with InSe (indium selenide) film ditch Channel layer.Around InSe thin film channels layer, with InSe thin film channels layer InSe protective layers are equipped with layer；Also, positioned at grid two In the InSe protective layers of side top position equipped with InSe transistors source-drain area (i.e. side be source region, opposite side be leakage Area).
The InSe films atomic layer level thickness of the InSe thin film channels layer can be 3-15 layers.
The InSe protective layers can be used with the two dimensional crystal material system that can be doped characteristic and chemical property stabilization Formed, such as graphene, graphite phase carbon nitride, molybdenum disulfide.The InSe protective layers can adulterate P, B, C, Se etc..It is so-called Chemical property stablize refers in the air that two dimensional crystal material can be at normal temperatures keep property of thin film stablize, will not with air Oxygen, hydrone etc. react, and cause film to be decomposed or be denatured.
Please refer to Fig.1.On the part InSe protective layers positioned at InSe thin film channels layer and InSe thin film channels layer periphery Also it is connected and is equipped with passivation layer；InSe films are wrapped up using the passivation layer and InSe protective layers, to InSe film ditches Channel layer implements closing, is isolated from the outside InSe films, efficiently avoid the exposure of InSe films in atmosphere, maintains InSe The chemical property of film is stablized, so as to ensure that the performance and yield of device.
Source-drain electrode 109 can be also equipped with the source-drain area of InSe protective layers both sides.Source-drain electrode can use metal material Make, be, for example, Cu.
Below by way of embodiment and attached drawing, a kind of preparation method of above-mentioned InSe transistors of the present invention is carried out Describe in detail.
Referring to Fig. 2, Fig. 2 is a kind of preparation method flow chart of InSe transistors of a preferred embodiment of the present invention；Together When, Fig. 3-Figure 10 is referred to, Fig. 3-Figure 10 is to prepare InSe transistors according to the method for Fig. 2 in a preferred embodiment of the present invention Processing step schematic diagram.As shown in Fig. 2, a kind of preparation method of above-mentioned InSe transistors of the present invention, comprises the following steps：
Step S01：There is provided a surface has the Semiconductor substrate of interlayer dielectric layer, and one is formed on the interlayer dielectric layer Groove.
Refer to Fig. 3.First, conventional Semiconductor substrate 201 can be used, grows forming layer in Semiconductor substrate 201 Between dielectric layer 202.Interlayer dielectric layer 202 can be formed using conventional material.
Then, groove 203 can be formed by photoetching, etching technics on the interlayer dielectric layer 202.In the present embodiment In, the depth of groove 203 can be 60nm (nanometer).
Step S02：Gate metal material is deposited, forms metal gates in a groove.
Refer to Fig. 4.Then, gate metal material is deposited in groove 203, and glossing can be used to remove groove The unnecessary metal material in 203 outsides, so as to form metal gates 204 in a groove.In the present embodiment, gate metal material can For Al.
Step S03：Metal gates upper surface is set to be oxidized to form metal oxide, as gate dielectric.
Refer to Fig. 5.Then, aoxidized by annealing process, the gate metal upper surface of metal gates in groove, Metal oxide is formed, as gate dielectric 205.In the present embodiment, gate dielectric material Al2O3, thickness can be 2nm。
Step S04：Crystal growth substrate layer and InSe protective layers are sequentially formed in above-mentioned device surface.
Refer to Fig. 6.Afterwards, it is sequentially depositing to form crystal growth substrate layer on gate dielectric and interlayer dielectric layer 206 and InSe protective layers 207.In the present embodiment, crystal growth substrate layer material can be hexagonal boron nitride (h-BN), and thickness is 10nm.InSe protective layers can be molybdenum disulfide, thickness 6nm.
Step S05：InSe protective layers are patterned, and source-drain area is formed in InSe protective layers.
Refer to Fig. 7.Then, by photoetching, doping and etching, InSe protective layers 207 are patterned, are formed middle InSe protection layer patterns with cavity；And using the property adulterated of InSe protective layer materials, by being entrained in InSe protective layers Doped region formed source-drain area 208.In the present embodiment, using the molybdenum disulfide InSe protections in grid both sides top position C is adulterated in layer, to form source-drain area 208.
Step S06：Protected in InSe and InSe thin film channel layers are formed within layer pattern.
Refer to Fig. 8.Then, InSe films 209 are grown by autoregistration on the crystal growth substrate layer above grid, To protect the cavity area within layer pattern, i.e. among InSe protection layer patterns to form InSe thin film channel layers in InSe.At this In embodiment, the methods of can using epitaxial growth method or atomic deposition, grows InSe films 209, and is deposited in vacuum equipment InSe films.
Step S07：Passivation layer is formed on InSe thin film channels layer and InSe protective layers.
Refer to Fig. 9.Then, in the same vacuum equipment of deposition InSe films, in InSe thin film channels layer and InSe Continue deposit passivation layer material on protective layer, and by photoetching and etching, in InSe films and InSe thin film channels layer periphery Passivation layer 210 is formed on the InSe protective layers of part.In the present embodiment, passivation layer can be Si3N4, thickness is in 100nm or so.
It can also continue to perform step S08：Source-drain area in both sides carries out metal deposit and polishing, forms source-drain electrode.
Please refer to Fig.1 0.Finally, the enterprising row metal deposition of source and drain zone position in passivation layer both sides, and it is flat by polishing Change, form the source-drain electrode 211 concordant with passivation layer surface.In the present embodiment, the material of source-drain electrode can be Cu.
The present invention is in order to avoid damaging InSe thin film channel layers when forming grid, it is proposed that is initially formed grid Method.The gate metal material such as Al that use of the present invention can aoxidize, after anneal oxidation, densification is formed in Al gate surfaces Continuous Al2O3Oxide skin(coating), can be used as gate dielectric.Using the crystal growth substrate layer of the formation such as h-BN, be conducive to two sulphur Change the deposition of molybdenum InSe protective layers and InSe films, and crystal growth substrate layer can and Al2O3Collectively form InSe transistors Gate dielectric layer.Molybdenum disulfide InSe protective layers are first deposited on h-BN crystal growth substrate layers, then by photoetching, doping and Etching technics, source and drain areas are formed above grid both sides.And it can then lead on the h-BN crystal growth substrate layers above grid The mode for crossing autoregistration growth deposits InSe films, forms InSe thin film channel layers.After InSe thin film depositions, in same vacuum Continue deposit passivation layer in equipment, InSe films are wrapped up jointly using the InSe protective layers of passivation layer and source-drain area, are had Avoid to effect InSe exposures in atmosphere, the chemical property for maintaining InSe films is stablized, so as to ensure that the performance of device And yield.The present invention can effectively ensure that the stabilization of InSe film performances, while can be compatible with traditional cmos process, can prepare Small size, large-scale InSe transistor arrays.
In conclusion the present invention makes metal gates surface form gate dielectric by anneal oxidation, and pass through autoregistration It is grown in deposition InSe films on crystal growth substrate layer；In addition, made using the two dimensional crystal material stablized with chemical property For the protective layer of InSe raceway grooves both sides, InSe films ingress of air when making source-drain area is prevented to be decomposed；Utilize doping process Two dimensional crystal material can be made to become source-drain area；On the other hand, the passivation layer on InSe films and InSe are in same vacuum equipment Deposition, it also avoid InSe by the possibility of air separation.It can effectively prevent using the method for the present invention during transistor technology The decomposition of InSe, and, preparation process simple possible compatible with existing CMOS technology.
It is above-described to be merely a preferred embodiment of the present invention, the embodiment and the patent guarantor for being not used to the limitation present invention Scope, therefore the equivalent structure change that every specification and accompanying drawing content with the present invention is made are protected, similarly should be included in In protection scope of the present invention.

Claims (10)

1. a kind of InSe transistors, it is characterised in that include from bottom to top：
Grid；
Gate dielectric on grid；
Crystal growth substrate layer on gate dielectric；
InSe thin film channel layers on crystal growth substrate layer above grid；
Around the InSe protective layers of InSe thin film channel layers, it is equipped with the InSe protective layers of grid both sides top position Source-drain area；
Passivation layer on InSe thin film channels layer and InSe protective layers, the passivation layer by InSe thin film channels layer close with It is isolated from the outside.
2. InSe transistors according to claim 1, it is characterised in that further include：Source-drain electrode on source-drain area, Interlayer dielectric layer below crystal growth substrate layer, and the Semiconductor substrate below interlayer dielectric layer；The grid Gate dielectric on pole and grid is located in interlayer dielectric layer.
3. InSe transistors according to claim 2, it is characterised in that the grid, which uses, to be had by the gold of oxidation characteristic Belong to material to be formed, the gate dielectric is formed using the metal oxide of grid；The crystal growth substrate layer using h-BN, β-Si3N4, any one material in SiC formed.
4. InSe transistors according to claim 1, it is characterised in that the InSe films in the InSe thin film channels layer Atomic layer level thickness is 3-15 layers.
5. InSe transistors according to claim 1, it is characterised in that the InSe protective layers, which use to have, is doped spy The two dimensional crystal material of property is formed.
6. the preparation method of the InSe transistors described in a kind of claim 3, it is characterised in that comprise the following steps：
Step S01：There is provided a surface has the Semiconductor substrate of interlayer dielectric layer, and it is recessed that one is formed on the interlayer dielectric layer Groove；
Step S02：Gate metal material is deposited, forms metal gates in a groove；
Step S03：Metal gates upper surface is set to be oxidized to form metal oxide, as gate dielectric；
Step S04：Crystal growth substrate layer and InSe protective layers are sequentially formed in above-mentioned device surface；
Step S05：InSe protective layers are patterned, and source-drain area is formed in InSe protective layers；
Step S06：Protected in InSe and InSe thin film channel layers are formed within layer pattern；
Step S07：Passivation layer is formed on InSe thin film channels layer and InSe protective layers.
7. the preparation method of InSe transistors according to claim 6, it is characterised in that in step S03, pass through lehr attendant Skill, is aoxidized the metal gates upper surface in groove, forms metal oxide.
8. the preparation method of InSe transistors according to claim 6, it is characterised in that in step S05, by photoetching, Doping and etching, form the InSe protection layer patterns with cavity, and form source-drain area in the doped region of InSe protective layers；Step In rapid S06, InSe films are grown by autoregistration on the crystal growth substrate layer above grid, to protect layer pattern in InSe Within cavity area formed InSe thin film channel layers.
9. the preparation method of InSe transistors according to claim 6, it is characterised in that deposited in same vacuum equipment InSe films, passivation material.
10. the preparation method of InSe transistors according to claim 6, it is characterised in that further include：Step S08：Two The source-drain area of side carries out metal deposit and polishing, forms source-drain electrode.
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CN113066905A (en) * 2021-04-12 2021-07-02 山东大学 Method for preparing indium selenide photoelectric detector by photoetching technology

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