CN107768353A - Stack package structure and preparation method thereof - Google Patents
Stack package structure and preparation method thereof Download PDFInfo
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- CN107768353A CN107768353A CN201710965103.5A CN201710965103A CN107768353A CN 107768353 A CN107768353 A CN 107768353A CN 201710965103 A CN201710965103 A CN 201710965103A CN 107768353 A CN107768353 A CN 107768353A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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Abstract
The present invention provides a kind of stack package structure and preparation method thereof, wherein, the stack package structure includes what is set gradually from bottom to top：First chip, the second chip, plastic packaging layer, metal wiring layer and the export point being made on the metal wiring layer, the plastic packaging layer coat second chip completely.The present invention solves the problems, such as that size differs less Multichip stacking encapsulation；Its stud bump making technique is simple, and cost is low；And do not need flatening process dew metal column to realize interconnection, realizing cost further reduces；And salient point homogeneity is good.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of stack package structure and preparation method thereof.
Background technology
MEMS (Micro-Electro-Mechanical System, MEMS) chip and CMOS
Semiconductor (Complementary Metal Oxide Semiconductor, CMOS) stacked package, usually uses large scale core
Small-size chips (such as MEMS chip) are stacked on piece (such as CMOS chip), while in the long salient point of large size chip spare area, it is convex
Point is higher than small-size chips, finally by salient point upside-down mounting to pcb board.
As shown in figure 1, if CMOS chip 10 is more or less the same with the size of MEMS chip 20, parallel MEMS chip on CMOS chip
Insufficient space, will be unable to complete stud bump making.
As shown in Fig. 2 according to TMV mode, the plating metal in vertical through hole, conductive pole is formed, by CMOS chip
10 electrically lead to the back side of MEMS chip 20, then are connected up, do salient point.
However, the program fills the metal column (being more than 100 μm) not less than MEMS chip stack height, cost in through-holes
Height, technology difficulty is big, and metal column high level of homogeneity can not ensure.And metal stud is into rear, it is also necessary to which gold is exposed in planarization
Belong to post, cause cost further to increase.
Therefore, the chip stack package being more or less the same for size, it is badly in need of a kind of new solution.
The content of the invention
The present invention is intended to provide a kind of stack package structure and preparation method thereof, to overcome in the prior art on the first chip
It is insufficient existing for the encapsulation technology for the second chip that stack size is more or less the same.
In order to solve the above technical problems, the technical scheme is that：
A kind of stack package structure, it includes what is set gradually from bottom to top：First chip, the second chip, plastic packaging layer, gold
Category wiring layer and the export point being made on the metal wiring layer, the plastic packaging layer coat second chip completely.
As the improvement of the stack package structure of the present invention, first chip has functional surfaces, set on the functional surfaces
The first salient point is equipped with, the region that first salient point is not provided with the functional surfaces is provided with the second salient point, and described first is convex
Point forms the exit of first chip, and the metal wiring layer is connected with first salient point, and second chip leads to
Second salient point is crossed with first chip to be connected.
As the improvement of the stack package structure of the present invention, the height of first salient point is not more than 50 μm.
As the improvement of the stack package structure of the present invention, first salient point is directly arranged on weld pad, or is set
In to weld pad it is electrical carry out rearrangement metal interconnection line on.
As the improvement of the stack package structure of the present invention, glue is also filled with around second salient point.
As the improvement of the stack package structure of the present invention, protective layer is additionally provided with the metal wiring layer, it is described
Opening is provided with protective layer, the export point goes out from the opening exposure.
In order to solve the above technical problems, another technical scheme of the present invention is：
A kind of preparation method of stack package structure as described above, it comprises the following steps：
S1, a wafer is provided, wafer includes some first chip dies, the first salient point is made on each crystal particle function face；
S2, the second chip with the second salient point is provided, second chip is arranged at crystal grain by its second salient point
The region of the first salient point, corresponding one second chip of any crystal grain are not provided with functional surfaces；
S3, plastic packaging is carried out to the second chip on the functional surfaces, form plastic packaging layer, and the plastic packaging layer is subtracted
It is thin；
S4, it is open on the plastic packaging layer, to expose the first salient point of the wafer；
S5, make metal wiring layer on the surface of the opening and plastic packaging layer, the metal wiring layer in the opening
It is connected with the first salient point exposed；
S6, export point is made on the metal wiring layer.
As the improvement of the preparation method of the stack package structure of the present invention, the step S2 also includes：By described second
Flip-chip it is arranged at the region that the first salient point is not provided with the functional surfaces, and by the MEMS chip and the functional surfaces
On metal interconnection line be connected.
As the improvement of the preparation method of the stack package structure of the present invention, the opening opened up exposes first salient point
Surface or section.
As the improvement of the preparation method of the stack package structure of the present invention, the preparation method of the stack package structure is also
Including：Reduction processing is carried out to the back side of the wafer, the step is between step S3 and step S4.
As the improvement of the preparation method of the stack package structure of the present invention, the back side of the wafer after being thinned is bonded temporarily
One support plate.
As the improvement of the preparation method of the stack package structure of the present invention, obtained packaging body is cut, obtained
Single packaging body.
In order to solve the above technical problems, another technical scheme of the present invention is：
A kind of stack package structure, it includes what is set gradually from bottom to top：First chip, the second chip, plastic packaging layer, gold
Category wiring layer and the export point that is made on the metal wiring layer, the back side or section of second chip are from the modeling
Sealing is exposed and goes out.
In order to solve the above technical problems, another technical scheme of the present invention is：
A kind of preparation method of stack package structure as described above, it comprises the following steps：
S1 ', a wafer is provided, wafer includes some first chip dies, the first salient point is made on each crystal particle function face；
S2 ', the second chip with the second salient point is provided, second chip is arranged at crystal grain by its second salient point
The region of the first salient point, corresponding one second chip of any crystal grain are not provided with functional surfaces；
S3 ', plastic packaging is carried out to the second chip on the functional surfaces, form plastic packaging layer, and the plastic packaging layer is subtracted
It is thin, and expose the back side or section of second chip；
S4 ', it is open on the plastic packaging layer, to expose the first salient point of the wafer；
S5 ', metal wiring layer is made on the back side or section of the opening and the second chip, in the opening
Metal wiring layer is connected with the first salient point exposed；
S6 ', export point is made on the metal wiring layer.
In order to solve the above technical problems, another technical scheme of the present invention is：
A kind of stack package structure, including the first chip, and the second chip thereon is stacked, the first core outside stack region
Prepared by piece surface have some first salient points, and plastic packaging layer at least wraps up the first salient point and the second chip side wall, and on the first salient point
Opening is left, be open interior paving metal level, and the metal level extends to plastic packaging layer and covers the upper edge of opening, and export is formed at metal level
On, fill and cover opening.
Compared with prior art, the beneficial effects of the invention are as follows：Interconnection structure between stacked chips of the present invention is small, duty
Than small, and export point is larger in the upper surface arrangement space of stacked chips, solves size and differs less multi-chip stacking envelope
Dress problem；Its stud bump making technique is simple, and cost is low；And do not need flatening process dew metal column to realize interconnection, realize
Cost further reduces；And salient point homogeneity is good.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments described in invention, for those of ordinary skill in the art, on the premise of not paying creative work,
Other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of existing schematic diagram of method for packing；
Fig. 2 is the schematic diagram of existing another method for packing；
Fig. 1-1 to Fig. 1-7 is the principle of the manufacture craft of the embodiment 1 of the preparation method of the stack package structure of the present invention
Figure；
Fig. 2-1 to Fig. 2-5 is the principle of the manufacture craft of the embodiment 2 of the preparation method of the stack package structure of the present invention
Figure；
Fig. 3-1 to 3-6 is the process principle figure that support plate is bonded in embodiment 2；
Fig. 4 is the structural representation of an embodiment of the stack package structure of the present invention；
Fig. 5 is the structural representation of another embodiment of the stack package structure of the present invention；
Fig. 6 is the structural representation of another embodiment of the stack package structure of the present invention.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of protection of the invention.
The preparation method of the stack package structure of the present invention comprises the following steps：
1st, a wafer is provided, wafer includes some first chip dies, the first salient point is made on each crystal particle function face；
The 2nd, the second chip with the second salient point is provided, second chip is arranged at the work(by its second salient point
The region of the first salient point is not provided with energy face；
3rd, plastic packaging is carried out to the second chip on the functional surfaces, forms plastic packaging layer, and the plastic packaging layer is thinned；
4th, it is open on the plastic packaging layer, to expose the first salient point of the wafer；
5th, metal wiring layer is made, the metal wiring layer in the opening is connected with the first salient point exposed；
6th, export point is made on the metal wiring layer.
7th, obtained packaging body is cut, obtains single packaging body.
Technical scheme is illustrated with reference to specific embodiment.Meanwhile for structure narration
Convenient, the identical structure in embodiment 1 and embodiment 2 continues to use unified label.Wafer is CMOS in embodiment 1 and embodiment 2
Wafer, the first chip are CMOS chip, and the second chip is MEMS chip.
Embodiment 1
As shown in Fig. 1-1 to 1-7, the preparation method of the present embodiment comprises the following steps：
S1, CMOS wafer 100 is provided, the first salient point 101 is made on its functional surfaces.
Wherein, first salient point 101 is short salient point, and it is used to electrically draw the weld pad of CMOS wafer 100.Described
One salient point 101 directly can be made on weld pad, can also be made in the metal interconnecting wires of progress rearrangement electrical to weld pad
Lu Shang.Preferably, the height of first salient point 101 is not more than 50 μm.First salient point 101 is selected from：Tin, copper, aluminium, silver,
Gold, nickel, the one or more of titanium.
S2, the MEMS chip 200 with the second salient point is provided, the MEMS chip 200 is set by its second salient point
In the region that the first salient point 101 is not provided with the functional surfaces.
Wherein, the second salient point on the MEMS chip 200 forms for pre-production, to realize the electricity of MEMS chip 200
Property draw.The MEMS chip 200 is the chip after being thinned, and so can effectively reduce the thickness of packaging body.The MEMS chip
200 can be the element of any MEMS-type state, and it can be selected from：One in action sensing device, less radio-frequency element, oscillator
Kind.The action sensing device can be gyroscope (Gyroscope/Gyro) and accelerometer (Accelerometer) etc.；It is described
Less radio-frequency element can be RF switches and wave filter (Filter) etc..
When arranging the MEMS chip 200, the upside-down mounting of MEMS chip 200 is arranged on the functional surfaces and is not provided with
The region of first salient point 101, and the MEMS chip 200 is connected with the metal interconnection line on the functional surfaces.Meanwhile
Some CMOS crystal grain are included in the CMOS wafer 100, should ensure that any CMOS crystal grain is corresponding when arranging the MEMS chip 200
One MEMS chip 200, to form MEMS-CMOS stacked structures.
In addition, the step S3 also includes：Before plastic packaging, glue is filled around second salient point.So set
Put, be advantageous to increase the firmness of MEMS chip 200, then carry out the plastic packaging of MEMS chip 200 again.
S3, plastic packaging is carried out to the MEMS chip 200 on the functional surfaces, form plastic packaging layer 300, and to the plastic packaging layer
300 are thinned.
In the present embodiment, when the plastic packaging layer 300 is thinned, thinned size is controlled, ensures the back side of MEMS chip 200
It is not exposed out, is arranged such, form the packaging body coated completely, increases reliability.
S4, it is open on the plastic packaging layer 300, to expose the first salient point 101 of the CMOS wafer 100.
Wherein, the mode of the opening is selected from：One kind in machine cuts, laser ablation, dry etching.In addition, open up
Opening 301 expose the surface or section of first salient point 101, the so electric connection in order to the first salient point 101.
In addition, between step S3 and S4, i.e., after plastic packaging processing, before opening processing, the stack package structure
Preparation method also includes：Reduction processing is carried out to the back side of the CMOS wafer 100, to reduce the integral thickness of packaging body.
Meanwhile in order to ensure the intensity of plastic-sealed body after being thinned, the back side ephemeral key unification support plate of the CMOS wafer 100 after being thinned should
Support plate carries out dismounting processing after encapsulation finishes.
S5, metal wiring layer 302 is made on the surface of the opening and plastic packaging layer 300, the metal in the opening
Wiring layer 302 is connected with the first salient point 101 exposed.
Specifically, the wiring layer in the opening is connected with first salient point 101 exposed, and along described
The inwall of opening extends to the surface of the plastic packaging layer 300.In addition, before export point 304 is made, in addition to：In the gold
Layer protective layer is laid on category wiring layer 302, and is open on the protective layer, is exposed for 304 phases of the export point
The region of metal wiring layer 302 of connection.Wherein, the protective layer can be welding resisting layer or insulating barrier.
S6, export point 304 is made on the metal wiring layer 302.
S7, obtained packaging body is cut, obtain single packaging body.
Embodiment 2
The step of the present embodiment, is substantially same as Example 1, and distinctive points are, when carrying out the reduction processing of plastic packaging layer 300,
The back side of MEMS chip 200 is exposed, or even exposes MEMS section, fully to reduce the height of packaging body.
As shown in Fig. 2-1 to 2-5, the preparation method of the present embodiment comprises the following steps：
S1 ', CMOS wafer 100 is provided, the first salient point 101 is made on its functional surfaces；
S2 ', the MEMS chip 200 with the second salient point is provided, the MEMS chip 200 is set by its second salient point
In the region that the first salient point 101 is not provided with the functional surfaces；
S3 ', plastic packaging is carried out to the MEMS chip 200 on the functional surfaces, form plastic packaging layer 300, and to the plastic packaging layer
300 are thinned, and expose the back side or section of the MEMS chip 200；
S4 ', it is open on the plastic packaging layer 300, to expose the first salient point 101 of the CMOS wafer 100；
S5 ', metal wiring layer 302 is made on the back side or section of the opening and MEMS chip 200, it is described to open
Metal wiring layer 302 in mouthful is connected with the first salient point 101 exposed；
S6 ', export point 304 is made on the metal wiring layer 302.
As shown in Fig. 3-1 to 3-6, in addition, between step S3 ' and S4 ', i.e., after plastic packaging processing, before opening processing,
The preparation method of the stack package structure also includes：Reduction processing is carried out to the back side of the CMOS wafer 100, to reduce
The integral thickness of packaging body.Meanwhile in order to ensure the intensity of plastic-sealed body after being thinned, the back side of the CMOS wafer 100 after being thinned
Ephemeral key unifies support plate 400, and the support plate 400 carries out dismounting processing after encapsulation finishes.
Other steps of the present embodiment are identical with example 1, no longer carry out repeated description herein.
As shown in figure 4, the preparation method provided based on embodiment 1, the present invention also provides one kind and obtained by the preparation method
The stack package structure arrived, the stack package structure include what is set gradually from bottom to top：CMOS chip 100, MEMS chip
200th, plastic packaging layer 300, metal wiring layer 302 and the export point 304 being made on the metal wiring layer 302, the plastic packaging
Layer 300 coats the MEMS chip 200 completely.
Wherein, the CMOS chip 100 has functional surfaces, and the first salient point 1001, the work(are provided with the functional surfaces
The region that first salient point 1001 is not provided with energy face is provided with the second salient point 1002.Wherein, first salient point 1001
The exit of the CMOS chip 100 is formed, the metal wiring layer 302 is connected with first salient point 1001.Preferably,
The height of first salient point 1001 is not more than 50 μm.In addition, first salient point 1001 can be directly arranged on weld pad,
It can be arranged on the metal interconnection line of progress rearrangement electrical to weld pad.
The MEMS chip 200 is connected by the upside-down mounting of the second salient point 1002 with the CMOS chip 100.It is described
When MEMS chip 200 is packaged in integral with the CMOS chip 100, the corresponding MEMS chip 200 of any CMOS chip.In addition,
In order to increase the fastness of the MEMS chip 200, glue is also filled with around second salient point 1002.
In addition, protective layer 305, such as welding resisting layer, insulating barrier are additionally provided with the metal wiring layer 302.The guarantor
Opening is provided with sheath 305, the export point 304 goes out from the opening exposure.
As shown in figure 5, in addition, the preparation method provided based on embodiment 2, the present invention also provide one kind by the making side
The stack package structure that method obtains, the structure is similar to the stacked structure by the gained of embodiment 1, and difference is the MEMS chip
200 back side or section expose from the plastic packaging layer 300.
Specifically, the stack package structure includes what is set gradually from bottom to top：CMOS chip 100, MEMS chip
200th, plastic packaging layer 300, metal wiring layer 302 and the export point 304 being made on the metal wiring layer 302, the MEMS
The back side or section of chip 200 expose from the plastic packaging layer 300.
As shown in fig. 6, being based on identical inventive concept, the present invention also provides the stack package structure of another structure.Tool
Body, a kind of stack package structure, including the first chip 100, and stack the second chip 200 thereon.Outside stack region
Prepared by one 100, core surface have some first salient points 101, and plastic packaging layer 300 at least wraps up the first salient point 101 and the second chip 200
Side wall, and opening is left on the first salient point 101, be open interior paving metal level 302.The back side of second chip 200 is cut
Face exposes from the plastic packaging layer 00.The metal level 302 extends to plastic packaging layer 300 and covers the upper edge of opening, export 304 shapes of point
Into on metal level 302, filling and cover opening.Protective layer 303 is additionally provided with second chip 200 and plastic packaging layer 300.
Wherein, first chip 100 can be CMOS chip, and the second chip can be MEMS chip.In summary, the present invention stacks
Interconnection structure between chip is small, and dutycycle is small, and export point is larger in the upper surface arrangement space of stacked chips, solves chi
The very little less Multichip stacking encapsulation problem of difference；Its stud bump making technique is simple, and cost is low；And flatening process dew is not needed
Metal column interconnects to realize, realizing cost further reduces；And salient point homogeneity is good.
It is obvious to a person skilled in the art that the invention is not restricted to the details of above-mentioned one exemplary embodiment, Er Qie
In the case of without departing substantially from spirit or essential attributes of the invention, the present invention can be realized in other specific forms.Therefore, no matter
From the point of view of which point, embodiment all should be regarded as exemplary, and be nonrestrictive, the scope of the present invention is by appended power
Profit requires rather than described above limits, it is intended that all in the implication and scope of the equivalency of claim by falling
Change is included in the present invention.Any reference in claim should not be considered as to the involved claim of limitation.
Moreover, it will be appreciated that although the present specification is described in terms of embodiments, not each embodiment is only wrapped
Containing an independent technical scheme, this narrating mode of specification is only that those skilled in the art should for clarity
Using specification as an entirety, the technical solutions in the various embodiments may also be suitably combined, forms those skilled in the art
It is appreciated that other embodiment.
Claims (15)
1. a kind of stack package structure, it is characterised in that the stack package structure includes what is set gradually from bottom to top：First
Chip, the second chip, plastic packaging layer, metal wiring layer and the export point being made on the metal wiring layer, the plastic packaging layer
Second chip is coated completely.
2. stack package structure according to claim 1, it is characterised in that first chip has functional surfaces, described
The first salient point is provided with functional surfaces, the region that first salient point is not provided with the functional surfaces is provided with the second salient point,
First salient point forms the exit of first chip, and the metal wiring layer is connected with first salient point, described
Second chip is connected by second salient point with first chip.
3. stack package structure according to claim 2, it is characterised in that the height of first salient point is not more than 50 μ
m。
4. stack package structure according to claim 1, it is characterised in that first salient point is directly arranged at weld pad
On, or be arranged on the metal interconnection line of progress rearrangement electrical to weld pad.
5. stack package structure according to claim 1, it is characterised in that be also filled with glue around second salient point
Water.
6. stack package structure according to claim 1, it is characterised in that guarantor is additionally provided with the metal wiring layer
Sheath, opening is provided with the protective layer, and the export point goes out from the opening exposure.
It is 7. a kind of if any one of claim 1 to 6 is the preparation method of stack package structure, it is characterised in that the making side
Method comprises the following steps：
S1, a wafer is provided, wafer includes some first chip dies, the first salient point is made on each crystal particle function face；
S2, the second chip with the second salient point is provided, second chip is arranged at crystal particle function by its second salient point
The region of the first salient point, corresponding one second chip of any crystal grain are not provided with face；
S3, plastic packaging is carried out to the second chip on the functional surfaces, form plastic packaging layer, and the plastic packaging layer is thinned；
S4, it is open on the plastic packaging layer, to expose the first salient point of first chip；
S5, make metal wiring layer on the surface of the opening and plastic packaging layer, the metal wiring layer in the opening with it is sudden and violent
The first salient point exposed is connected；
S6, export point is made on the metal wiring layer.
8. the preparation method of stack package structure according to claim 7, it is characterised in that the step S2 also includes：
Second flip-chip is arranged to the region that the first salient point is not provided with the functional surfaces, and by second chip with
Metal interconnection line on the functional surfaces is connected.
9. the preparation method of stack package structure according to claim 7, it is characterised in that the opening opened up exposes institute
State the surface or section of the first salient point.
10. the preparation method of stack package structure according to claim 7, it is characterised in that the stack package structure
Preparation method also include：Carry out reduction processing to the back side of first chip, the step between step S3 and step S4 it
Between.
11. the preparation method of stack package structure according to claim 10, it is characterised in that the first core after being thinned
The back side ephemeral key unification support plate of piece.
12. the preparation method of stack package structure according to claim 7, it is characterised in that enter to obtained packaging body
Row cutting, obtains single packaging body.
13. a kind of stack package structure, it is characterised in that the stack package structure includes what is set gradually from bottom to top：The
One chip, the second chip, plastic packaging layer, metal wiring layer and the export point being made on the metal wiring layer, described second
The back side or section of chip go out from plastic packaging layer exposure.
A kind of 14. preparation method of stack package structure as claimed in claim 13, it is characterised in that the preparation method bag
Include following steps：
S1 ', a wafer is provided, wafer includes some first chip dies, the first salient point is made on each crystal particle function face；
S2 ', the second chip with the second salient point is provided, second chip is arranged at crystal particle function by its second salient point
The region of the first salient point, corresponding one second chip of any crystal grain are not provided with face；
S3 ', plastic packaging is carried out to the second chip on the functional surfaces, form plastic packaging layer, and the plastic packaging layer is thinned, and
Expose the back side or section of second chip；
S4 ', it is open on the plastic packaging layer, to expose the first salient point of the wafer；
S5 ', make metal wiring layer on the back side or section of the opening and the second chip, the metal in the opening
Wiring layer is connected with the first salient point exposed；
S6 ', export point is made on the metal wiring layer.
15. a kind of stack package structure, including the first chip, and stack the second chip thereon, it is characterised in that stack region
Prepared by outer the first chip surface have some first salient points, and plastic packaging layer at least wraps up the first salient point and the second chip side wall, and
Opening is left on first salient point, be open interior paving metal level, and the metal level extends to plastic packaging layer and covers the upper edge of opening, export shape
Into on metal level, filling and cover opening.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108511409A (en) * | 2018-04-19 | 2018-09-07 | 苏州晶方半导体科技股份有限公司 | The wafer-level packaging method and its encapsulating structure of semiconductor chip |
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