CN107564824B - Chip packaging structure and packaging method - Google Patents
Chip packaging structure and packaging method Download PDFInfo
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- CN107564824B CN107564824B CN201710718543.0A CN201710718543A CN107564824B CN 107564824 B CN107564824 B CN 107564824B CN 201710718543 A CN201710718543 A CN 201710718543A CN 107564824 B CN107564824 B CN 107564824B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
- H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15158—Shape the die mounting substrate being other than a cuboid
- H01L2924/15159—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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Abstract
The invention relates to the technical field of chip packaging, and discloses a chip packaging method which comprises the following steps: arranging a plurality of first chips on a carrier; packaging the first chip to form a first packaging body; a groove body is formed in the first packaging body between the adjacent first chips; and arranging a second chip above the groove body and electrically connected with the first chip. Therefore, on one hand, the groove body is arranged to provide a required cavity and a required sealing structure for the second chip, on the other hand, the groove body is arranged on the formed first packaging body, the size of the packaging structure of various chips in the horizontal and vertical directions is reduced, and the miniaturization of the packaging structure is guaranteed. In addition, the packaging method is simple and easy to implement.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging structure and a chip packaging method.
Background
In the field of integrated circuit chip packaging technology, how to reduce packaging cost and improve production efficiency while ensuring that chip functions are not affected and packaging volume is not increased has become a very important and urgent research topic internationally. The stacked chip packaging technology is a new technology for stacking and packaging a plurality of chips with different functions and sizes.
The prior art discloses a packaging method for a package integrated with a power supply transmission system, which includes the following steps: 1) providing a carrier; 2) adopting an electroplating process to form a first metal connecting column on the surface of the carrier; 3) arranging an active module and a passive module on the surface of the carrier, wherein the first metal connecting column is formed on the surface of the carrier, and forming a second metal connecting column on the surfaces of the active module and the passive module, wherein the active module and the passive module form an active 2.5D intermediate plate, and the active 2.5D intermediate plate is used as a power transmission power chip; 4) packaging and molding the first metal connecting column, the active module, the passive module and the second metal connecting column by using a plastic packaging material, and removing part of the plastic packaging material to expose the first metal connecting column and the second metal connecting column; 5) forming a rewiring layer on the surface of the plastic packaging material, wherein the rewiring layer electrically connects the first metal connecting column, the active module and the passive module; the active module, the passive module and the rewiring layer jointly form a power supply transmission system; the power supply transmission system is suitable for converting a high voltage provided by an external power supply into a plurality of different low voltages and providing a plurality of low-voltage power supply tracks; 6) providing an electric chip, arranging the electric chip on the surface of the rewiring layer, and realizing the butt joint of the electric chip and the low-voltage power supply track through a plurality of micro-bumps; 7) peeling the carrier.
The above packaging technology has the following defects: 1. the electric chip is arranged on the surface of the rewiring layer through the plurality of micro-bumps, on one hand, the arrangement of the micro-bumps increases the thickness of the whole packaging structure to a certain extent, on the other hand, for the electric chip with certain requirement on space, extra space needs to be additionally provided for the electric chip, for example, the electric chip is realized by increasing the height of the micro-bumps, the thickness of the packaging structure is undoubtedly greatly increased, and the miniaturization of the packaging volume is not facilitated; 2. the outer surface of the power utilization chip is exposed outside, the sealing performance is poor, the power utilization chip is easily damaged, and the reliability is greatly reduced.
Disclosure of Invention
Therefore, the technical problem to be solved by the invention is as follows: for a chip with a certain space requirement, how to reduce the whole packaging volume after the chip is stacked and packaged.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
the invention provides a chip packaging method, which comprises the following steps:
arranging a plurality of first chips on a carrier;
packaging the first chip to form a first packaging body;
a groove body is formed in the first packaging body between the adjacent first chips;
and arranging a second chip above the groove body and electrically connected with the first chip.
Optionally, before or after the step of disposing the first chip on the carrier, the method further includes the following steps:
and arranging a plurality of first connecting columns on the electrodes of the first chip, wherein the first connecting columns are arranged on one side of the first chip far away from the carrier.
Optionally, after the step of forming a slot on the first package between the adjacent first chips, the method further includes the following steps:
and thinning one side of the first packaging body, which is far away from the carrier, to expose the top of the first connecting column.
Optionally, the step of disposing the second chip above the tank and electrically connecting with the first chip specifically includes:
wiring is carried out on the surface of the first packaging body, and the first chip is connected with the second chip;
and forming a plurality of second connecting columns on the surface of the first packaging body, wherein the second connecting columns are electrically connected with the first chip.
Optionally, after the step of disposing the second chip above the tank and electrically connecting the second chip to the first chip, the method further includes the following steps:
and packaging the second chip and the second connecting column onto the first packaging body to form a second packaging body, and exposing the top of the second connecting column.
The invention also provides a chip packaging structure, comprising:
the first packaging body is internally provided with a plurality of first chips, and a groove body is arranged on the first packaging body between the adjacent first chips;
and the second packaging body is directly formed on the first packaging body, and a plurality of second chips are arranged in the second packaging body and are arranged above the groove body and electrically connected with the first chips.
Optionally, a wiring layer is further disposed on the surface of the first package body, a plurality of first connection pillars are disposed on the first chip, and the wiring layer is connected to the first connection pillars;
the second chip is electrically connected with the first chip through the wiring layer.
Optionally, a second connection pillar is disposed on the wiring layer, and a top of the second connection pillar extends out of the second package body.
Compared with the prior art, the technical scheme of the invention has the following advantages:
the chip packaging method provided by the invention comprises the following steps of firstly, arranging a plurality of first chips on a carrier; packaging the first chip to form a first package body; then, a groove body is arranged on the first packaging body between the adjacent first chips; and finally, arranging the second chip above the groove body and electrically connecting the second chip with the first chip.
The existing chip packaging method generally packages chips to be packaged together in a layer-by-layer stacking mode, a packaging body is of a complete plane structure, in order to ensure the miniaturization of the packaging volume, the structures between the chips and the packaging body are often compact, and for special chips such as MEMS (micro-electromechanical systems) chips, the chips need to be sealed firstly and then stacked for packaging, or in special environments such as ultra-clean and inert gas atmosphere, so that the three-dimensional size of final packaging is greatly increased, and the miniaturization of the packaging volume is not facilitated. According to the chip packaging method, the groove body is formed in the first packaging body between the adjacent first chips, and the second chip is arranged above the groove body and electrically connected with the first chips. Therefore, on one hand, the groove body is arranged to provide a required cavity and a required sealing structure for the second chip, on the other hand, the groove body is arranged on the formed first packaging body, the size of the packaging structure of various chips in the horizontal and vertical directions is reduced, and the miniaturization of the packaging structure is guaranteed. In addition, the packaging method is simple and easy to implement.
The chip packaging method further comprises the step of arranging a plurality of first connecting columns on the electrodes of the first chip, wherein the first connecting columns are arranged on one side, far away from the carrier, of the first chip. Because the first chip needs to be packaged into the first packaging body subsequently, the electrodes on the first chip can be led out of the packaging body by arranging the first connecting columns on the electrodes of the first chip. In addition, the step of providing the first connection pillars may be performed before or after the step of providing the first chip on the carrier, which may be determined according to the actual situation.
The chip packaging method provided by the invention further comprises the step of thinning one side of the first packaging body, which is far away from the carrier, so that the top of the first connecting column is exposed. When the first package is formed, the first connection pillar on the first chip may not be completely exposed, which may affect the leading-out of the first chip electrode. Therefore, the side, away from the carrier, of the first packaging body is thinned so as to completely expose the first connecting column, and the normal operation of the subsequent packaging process is ensured. Meanwhile, only the top area of the first connecting column is exposed, and other areas of the chip are still of an integrated structure, so that the stability and reliability of the chip packaging structure and the use safety are guaranteed.
The chip packaging method provided by the invention comprises the steps of arranging a second chip above a groove body and electrically connecting the second chip with a first chip, wherein wiring is firstly carried out on the surface of the first packaging body, and the first chip is connected with the second chip; and forming a plurality of second connecting columns on the surface of the first packaging body, wherein the second connecting columns are electrically connected with the first chip. The first chip is electrically connected with the second chip by wiring on the surface of the formed first packaging body, and the second connecting column electrically connected with the first chip is formed on the surface of the first packaging body, so that the electrode of the first chip can be conveniently led out of the packaging body in the subsequent process.
The chip packaging method further comprises the step of packaging the second chip and the second connecting column on the first packaging body to form a second packaging body, and exposing the top of the second connecting column. The increase of the process steps enables the second chip and the second connecting column to be packaged and molded, the second chip is completely wrapped, the sealing performance of the second chip is enhanced, and the second chip is further protected. In addition, the top of the second connecting column is exposed out of the second packaging body, and the exposed top of the second connecting column is used as a connecting terminal of the first chip in the whole packaging structure as the second connecting column is electrically connected with the first chip.
The chip packaging structure provided by the invention comprises: a first packaging body internally provided with a plurality of first chips, wherein a groove body is arranged on the first packaging body between the adjacent first chips; and a second packaging body which is directly formed on the first packaging body and is internally provided with a plurality of second chips, wherein the second chips are arranged above the groove body and are electrically connected with the first chips.
The packaging body in the existing chip packaging structure is generally a complete plane structure, in order to ensure the miniaturization of the packaging volume, the structure between the chip and the packaging body and between the chip and the packaging body is often compact, and for special chips such as MEMS chips, the packaging body needs to be sealed and then stacked in a vacuum environment or in special environments such as ultra-clean and inert gas atmosphere, so that the three-dimensional size of final packaging can be greatly increased, and the miniaturization of the packaging volume is not facilitated.
In the chip packaging structure provided by the application, the groove body is arranged to provide a required cavity and a required sealing structure for the second chip, and the groove body is arranged on the formed first packaging body, so that the size of the packaging structure of various chips in the horizontal direction and the vertical direction is reduced, and the miniaturization of the packaging structure is ensured. In addition, the first chip is wrapped by the first packaging body comprehensively, and the second chip is wrapped by the second packaging body comprehensively to form an integrated structure of the first chip and the second chip, so that the sealing performance of the first chip and the second chip is enhanced, and the reliability of the whole packaging structure is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIGS. 1 to 9 are schematic views of a chip packaging process according to an embodiment of the present invention;
description of reference numerals:
1-a carrier; 2-an adhesive layer; 3-a first chip; 4-a first connecting column; 5-a first package; 6-groove body; 7-a wiring layer; 71-a pad; 72-connecting wires; 8-a second chip; 9-glue sealing body; 10-a second connecting column; 11-second package.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The embodiment provides a chip packaging method, which comprises the following steps:
step S1, disposing several first chips 3 on carrier 1. The first chip 3 is not limited to one kind of chip, and may be various different or not all the same kind of chips.
As an implementation manner of this embodiment, step S1 specifically includes the following steps:
step S11, providing a carrier 1, wherein the carrier 1 is generally a silicon slide;
step S12, forming an adhesive layer 2 on the carrier 1, specifically, spin-coating a photosensitive temporary bonding glue, such as a UV glue, on the carrier 1 by spin-coating;
step S13, attaching each first chip 3 to the adhesive layer 2 on the carrier 1 by a bonding process, wherein the first chips 3 are arranged in a matrix.
Step S2, disposing a plurality of first connection pillars 4 on the electrode of the first chip 3, wherein the first connection pillars 4 are disposed on a side of the first chip 3 away from the carrier 1; the first connecting posts 4 are made of conductive metal, preferably copper, and the first connecting posts 4 correspond to the contact electrodes on the first chip 3 one by one. The first connection posts 4 are arranged to facilitate the extraction of the electrodes on the first chip 3 from the first package 5 to be formed later.
It should be noted that step S2 may be performed before step S13, and the object of the present invention can be achieved as well, which falls within the protection scope of the present invention.
Step S3, encapsulating the first chip 3 to form a first encapsulation body 5; specifically, the first chip 3 and the first connection pillars 4 on the first chip 3 are encapsulated and molded by a plastic encapsulation process to form a first encapsulation body 5.
Step S4, forming a groove 6 on the first package 5 between the adjacent first chips 3; specifically, the groove body 6 is formed by a cutting process, or when the first package is formed in step S3, the groove body 6 is directly formed by a plastic package mold, and the groove body 6 is not connected to the carrier 1 and the adjacent first chip 3.
Step S5, thinning the side of the first package 5 away from the carrier 1 to expose the top of the first connecting pillar 4; specifically, the polishing process is adopted for thinning treatment, so that the top of the first connecting column 4 is exposed, and the groove body 6 is ensured to have a certain depth.
When the first package 5 is formed, the first connection posts 4 on the first chip 3 may not be completely exposed, which may affect the extraction of the electrodes of the first chip 3. Therefore, step S5 thins the side of the first package 5 away from the carrier 1 to completely expose the first connecting pillars 4, so as to ensure that the subsequent packaging process is performed normally, and at the same time, only the top regions of the first connecting pillars are exposed, and other regions of the chip are still of an integrated structure, so as to ensure the stability and reliability of the chip packaging structure and the safety of use.
Step S6, arranging the second chip 8 above the groove body 6 and electrically connecting with the first chip 3;
as an implementation manner of this embodiment, step S6 specifically includes the following steps:
step S61, wiring on the surface of the first package 5, and connecting the first chip 3 and the second chip 8;
as an implementation manner of this embodiment, step S61 specifically includes the following steps:
step S611, forming a pad 71 on the top of each exposed first connection pillar 4 on the surface of the first package 5;
step S612, electrically connecting the adjacent first chips 3 by connecting some of the bonding pads 71 on the adjacent first chips 3;
step S613, the second chip 8 is disposed above the slot 6 by flip-chip mounting, and the second chip 8 is electrically connected to the pads 71 on the first chip 3 on both sides of the slot 6. For example, the second chip 8 has a protrusion on the upper surface, and the protrusion may be disposed in the slot 6 to reduce the stacking thickness of the first chip 3 and the second chip 8; or the upper surface of the second chip 8 is a non-flat surface, and the non-flat area can be placed in the slot body 6 to stabilize the second chip 8 and facilitate the subsequent packaging step.
In step S614, an adhesive sealing body 9 is formed in the peripheral region between the second chip 8 and the first package 5 to enhance the sealing performance of the second chip 8.
Step S62, forming a plurality of second connection posts 10 on the surface of the first package 5, wherein the second connection posts 10 are electrically connected to the first chip 3. Specifically, the second connection post 10 is formed on the pad 71 at the top of the first connection post 4 exposed on the surface of the first package body 5, or the second connection post 10 is formed in other areas on the surface of the first package body 5, and then the second connection post 10 is electrically connected with the pad 71 at the top of the first connection post 4, wherein the second connection post 10 is made of a metal material, preferably a copper material. The second connection posts 10 are arranged to further lead the electrodes of the first chip 3 out of the second package 11 in the subsequent process.
Step S62 may be performed before step S613, and the object of the present invention can be achieved similarly, which falls within the scope of the present invention.
Step S7, packaging the second chip 8 and the second connection stud 10 onto the first package 5 to form a second package 11, and exposing the top of the second connection stud 10; specifically, the second chip 8 and the second connection column 10 are packaged and molded by a plastic package process to form the second package body 11, and the top of the second connection column 10 is ensured to be exposed, and the second package body 11 can also be thinned by a polishing process to ensure that the top of the second connection column 10 is completely exposed.
Step S7 enables the second chip 8 and the second connecting stud 10 to be packaged and molded, and the second chip 8 is completely wrapped, so as to enhance the sealing performance of the second chip 8 and further protect the second chip 8. In addition, the top of the second connection column 10 exposes the second package 11, and since the second connection column 10 is electrically connected to the first chip 3, the exposed top of the second connection column 10 serves as a connection terminal of the first chip 3 in the whole package structure.
Step S8, removing the carrier 1; specifically, the carrier 1 is separated from the first package 5 by irradiating with UV light based on the carrier 1 coated with the UV glue, and the carrier 1 is irradiated with other light based on other temporary bonding glue having photosensitivity, which also falls within the protection scope of the present invention.
And step S9, cutting to form single stacked packaged chips.
The existing chip packaging method generally packages chips to be packaged together in a layer-by-layer stacking mode, a packaging body is of a complete plane structure, in order to ensure the miniaturization of the packaging volume, the structures between the chips and the packaging body are often compact, and for special chips such as MEMS (micro-electromechanical systems) chips, the chips need to be sealed firstly and then stacked for packaging, or in special environments such as ultra-clean and inert gas atmosphere, so that the three-dimensional size of final packaging is greatly increased, and the miniaturization of the packaging volume is not facilitated.
According to the chip packaging method provided by the application, the groove body 6 is formed in the first packaging body 5 between the adjacent first chips 3, and the second chip 8 is arranged above the groove body 6 and is electrically connected with the first chips 3. Therefore, on one hand, the groove body 6 is arranged to provide a required cavity and a required sealing structure for the second chip 8, on the other hand, the groove body 6 is arranged on the formed first packaging body 5, the size of the packaging structure of various chips in the horizontal and vertical directions is reduced, and the miniaturization of the packaging structure is guaranteed. In addition, the packaging method is simple and easy to implement.
Example 2
The embodiment provides a chip package structure, which comprises a first package body 5 and a second package body 11.
The first package 5 is internally provided with a plurality of first chips 3, and the first package 5 between adjacent first chips 3 is provided with a groove 6. The first chips 3 are arranged in a matrix, the first chips 3 are not limited to one type of chip, and may be different types or not of the same type, and the slot 6 is not connected to the adjacent first chips 3.
The second package 11 is directly disposed on the first package 5, and a plurality of second chips 8 are disposed in the second package, and the second chips 8 are disposed above the slot 6 and electrically connected to the first chip 3.
As an implementation manner of this embodiment, a wiring layer 7 is further disposed on the first package 5, a plurality of first connection pillars 4 are disposed on the first chip 3, and the wiring layer 7 is connected to the first connection pillars 4; the second chip 8 is electrically connected to the first chip 3 through the wiring layer 7. The first connection pillars 4 are made of metal, preferably copper, and have top portions exposed on the surface of the first package 5, and the wiring layer 7 includes pads 71 electrically connected to the exposed top portions of the first connection pillars 4, and connection wires 72 connecting the pads 71 on the adjacent first chips 3. The second chip 8 is electrically connected to the pad 71 on the first chip 3.
As an implementation manner of this embodiment, a second connection post 10 is disposed on the wiring layer 7, and a top of the second connection post 10 extends out of the second package 11. Specifically, the second connection posts 10 are made of metal, preferably copper, and can be directly electrically connected to the pads 71 on the top of the first connection posts 4, or can be disposed on other areas of the surface of the first package 5 and electrically connected to the pads 71 on the first chip 3 through the connection wires 72.
As an implementation manner of the present embodiment, an adhesive sealing body 9 is disposed in a peripheral region between the second chip 8 and the first package 5 to enhance the sealing performance of the second chip 8.
As an implementation manner of the present embodiment, the first chip 3 is attached to the carrier 1. Specifically, an adhesive layer 2 is disposed on the carrier 1, the first chip 3 is fixedly connected to the carrier 1 through the adhesive layer 2, the carrier 1 is generally a silicon-carrying sheet, and the adhesive layer 2 may be a photosensitive temporary bonding adhesive, such as UV adhesive or the like.
In the chip package structure provided by this embodiment, the slot 6 is configured to provide a required cavity and a required sealing structure for the second chip 8 (a special chip such as an MEMS chip, needs to be in a vacuum environment, or in special environments such as an ultra-clean and inert gas atmosphere); or for the second chip 8 with a protrusion on the surface, the protrusion can be arranged in the groove body 6 to reduce the stacking thickness of the first chip 3 and the second chip 8; or the upper surface of the second chip 8 is a non-flat surface, the non-flat area can be placed in the slot body 6 to stabilize the second chip 8 and facilitate the subsequent packaging step. The groove body 6 is arranged on the formed first packaging body 5, so that the sizes of the packaging structures of various chips in the horizontal and vertical directions are reduced, and the miniaturization of the packaging structures is ensured. In addition, first chip 3 is wrapped up by first packaging body 5 is comprehensive, and second chip 8 is wrapped up by second packaging body 11 is comprehensive, has strengthened first chip 3 and second chip 8's leakproofness, forms the integrated into one piece structure of first chip and second chip, has improved whole packaging structure's reliability.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (8)
1. A chip packaging method is characterized by comprising the following steps:
arranging a plurality of first chips (3) on a carrier (1);
packaging the first chip (3) to form a first packaging body (5);
a groove body (6) is formed in the first packaging body (5) between the adjacent first chips (3);
arranging a second chip (8) above the tank body (6) and electrically connecting the second chip with the first chip (3); a closed cavity is formed between the second chip (8) and the groove body (6).
2. The chip packaging method according to claim 1, wherein the step of disposing the first chip (3) on the carrier (1) further comprises, before or after, the steps of:
a plurality of first connecting columns (4) are arranged on the electrodes of the first chip (3), and the first connecting columns (4) are arranged on one side, far away from the carrier (1), of the first chip (3).
3. The chip packaging method according to claim 2, wherein after the step of forming the slot (6) in the first package (5) between the adjacent first chips (3), the method further comprises the following steps:
and thinning one side of the first packaging body (5) far away from the carrier (1) to expose the top of the first connecting column (4).
4. The chip packaging method according to claim 3, wherein the step of disposing the second chip (8) above the slot (6) and electrically connecting with the first chip (3) comprises:
wiring is carried out on the surface of the first packaging body (5), and the first chip (3) is connected with the second chip (8);
and forming a plurality of second connecting columns (10) on the surface of the first packaging body (5), wherein the second connecting columns (10) are electrically connected with the first chip (3).
5. The chip packaging method according to claim 4, wherein after the step of disposing the second chip (8) above the slot (6) and electrically connecting with the first chip (3), the method further comprises the following steps:
and packaging the second chip (8) and the second connecting column (10) onto the first packaging body (5) to form a second packaging body (11), and exposing the top of the second connecting column (10).
6. A chip package structure, comprising:
the chip packaging structure comprises a first packaging body (5), a plurality of first chips (3) are arranged in the first packaging body (5), and a groove body (6) is formed in the first packaging body (5) between the adjacent first chips (3);
a second packaging body (11) directly formed on the first packaging body (5) and internally provided with a plurality of second chips (8), wherein the second chips (8) are arranged above the groove body (6) and are electrically connected with the first chips (3); a closed cavity is formed between the second chip (8) and the groove body (6).
7. The chip packaging structure according to claim 6, wherein a wiring layer (7) is further disposed on the surface of the first packaging body (5), a plurality of first connection pillars (4) are disposed on the first chip (3), and the wiring layer (7) is connected to the first connection pillars (4);
the second chip (8) is electrically connected to the first chip (3) via the wiring layer (7).
8. The chip packaging structure according to claim 7, wherein a second connection post (10) is disposed on the wiring layer (7), and a top of the second connection post (10) extends out of the second package body (11).
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101740552A (en) * | 2008-11-25 | 2010-06-16 | 南茂科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
| US7999359B2 (en) * | 2007-01-26 | 2011-08-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with electromagnetic shield |
| CN103620772A (en) * | 2011-04-22 | 2014-03-05 | 泰塞拉公司 | Multi-chip module with stacked face-down connected dies |
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2017
- 2017-08-21 CN CN201710718543.0A patent/CN107564824B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7999359B2 (en) * | 2007-01-26 | 2011-08-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with electromagnetic shield |
| CN101740552A (en) * | 2008-11-25 | 2010-06-16 | 南茂科技股份有限公司 | Multi-chip packaging structure and manufacturing method thereof |
| CN103620772A (en) * | 2011-04-22 | 2014-03-05 | 泰塞拉公司 | Multi-chip module with stacked face-down connected dies |
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